CN113949344A - RC oscillator with stable frequency - Google Patents

RC oscillator with stable frequency Download PDF

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Publication number
CN113949344A
CN113949344A CN202111053838.3A CN202111053838A CN113949344A CN 113949344 A CN113949344 A CN 113949344A CN 202111053838 A CN202111053838 A CN 202111053838A CN 113949344 A CN113949344 A CN 113949344A
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generating circuit
comparator
pmos tube
switch
capacitor
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CN113949344B (en
Inventor
李世彬
牛成钰
潘磊
苟胤宝
郝运晗
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention discloses an RC oscillator with stable frequency, which is an RC oscillator with low temperature drift and high power supply rejection ratio, has the characteristics of simple structure, small influence by temperature and power supply voltage and stable frequency, and comprises a reference generating circuit, a reference generating circuit and a reference voltage generating circuit, wherein the reference generating circuit is used for generating fixed bias current and bias voltage, and the bias voltage is generated by the bias current flowing through a bias resistor; an oscillation generating circuit for generating a periodic signal having a frequency related only to the resistance and the capacitance using a reference of the reference generating circuit; the feedback regulating circuit is used for regulating the comparison reference voltage of the comparator according to the delay change of the comparator in the oscillation generating circuit and eliminating the delay influence of the comparator; the logic circuit is used for receiving the signal of the oscillation generating circuit and controlling the switching of a switch in the oscillation generating circuit to generate a periodic clock signal; the reference generating circuit is connected with the oscillation generating circuit, the oscillation generating circuit is connected with the logic circuit, and the feedback adjusting circuit is connected with the oscillation generating circuit.

Description

RC oscillator with stable frequency
Technical Field
The invention relates to the technical field of oscillating circuits, in particular to an RC oscillator with stable frequency.
Background
With the rapid development of the field of integrated circuits, oscillator modules as a frequency source for chips become increasingly indispensable. The RC oscillator has the advantages of simple structure, high integration level and relatively low power consumption, and is a clock generation circuit which is most widely applied. Generally, an RC oscillator generates an oscillation clock by delaying charging and discharging of a capacitor, but as a power supply voltage fluctuates and a working environment temperature changes, a charging and discharging current, a reference voltage, a comparator delay and a resistance value of the RC oscillator are affected, so that it is difficult to obtain a stable oscillation frequency.
Therefore, it is necessary to enhance the adaptability of the output frequency of the RC oscillator to the supply voltage and temperature variation, so that the clock frequency is stable and reliable.
Disclosure of Invention
The invention aims to provide an RC oscillator with stable frequency, which is an RC oscillator with low temperature drift and high power supply rejection ratio and has the characteristics of simple structure, small influence by temperature and power supply voltage and stable frequency.
The invention is realized by the following technical scheme: a frequency stabilized RC oscillator comprises
The reference generating circuit is used for generating fixed bias current and bias voltage, and the bias voltage is generated by the bias current flowing through the bias resistor;
an oscillation generating circuit for generating a frequency signal, which is a periodic signal relating only to the resistance and the capacitance, using a reference of the reference generating circuit;
the feedback regulating circuit is used for regulating the comparison reference voltage of the comparator according to the delay change of the comparator in the oscillation generating circuit and eliminating the delay influence of the comparator;
the logic circuit is used for receiving the output signal of the oscillation generating circuit, controlling a switch in the oscillation generating circuit and generating a periodic clock signal through switching of the switch;
the reference generating circuit is connected with the oscillation generating circuit, the oscillation generating circuit is connected with the logic circuit, and the feedback adjusting circuit is connected with the oscillation generating circuit.
In order to further realize the invention, the following arrangement mode is adopted: the reference generating circuit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first resistor, a second resistor, a third resistor and a power supply; the first resistor and the second resistor are connected in series and are connected between the grid electrode and the source electrode of the first NMOS tube, namely, one end of the first resistor is grounded, one end of the second resistor is connected with the other end of the first resistor, the other end of the second resistor is connected with the grid electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded; the grid electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the grid electrode of the second NOMS tube is connected with the drain electrode of the first NMOS tube, the third resistor is connected between the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube, namely, one end of the third resistor is connected with the drain electrode of the second NOMS tube, the other end of the third resistor is connected with the drain electrode of the third PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are connected with each other and are connected with the drain electrode of the second NMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are connected with each other and are connected with the drain electrode of the third PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the fourth PMOS tube, and the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected with a power supply; the common node of the third PMOS tube and the fourth PMOS tube and the common node of the fifth PMOS tube and the sixth PMOS tube are connected to the oscillation generating circuit, namely the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are both connected with the grid electrode of the seventh PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are both connected with the grid electrode of the eighth PMOS tube, and the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected with the source electrode of the eighth PMOS tube and are both powered.
In order to further realize the invention, the following arrangement mode is adopted: the first and second resistors have opposite temperature coefficients.
In order to further realize the invention, the following arrangement mode is adopted: the oscillation generating circuit comprises a seventh PMOS tube, an eighth PMOS tube, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a first comparator and a second comparator; the source electrode and the grid electrode of the eighth PMOS tube are both connected with a reference generating circuit (namely the source electrode of the eighth PMOS tube is connected with a power supply, and the grid electrode of the eighth PMOS tube is connected with the grid electrode of the fifth PMOS tube), the source electrode of the seventh PMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the seventh PMOS tube is connected with the reference generating circuit (the grid electrode of the third PMOS tube), one end of the first switch and one end of the second switch are connected with each other and are connected with the drain electrode of the seventh PMOS tube, the other end of the first switch is connected with one end of the first capacitor, the control end of the first switch is connected with a logic circuit (a QB end), and the other end of the first capacitor is grounded; the other end of the second switch is connected with one end of a second capacitor, the control end of the second switch is connected with a logic circuit (Q end), and the other end of the second capacitor is grounded; one end of the third switch is connected with one end of the first capacitor, the other end of the third switch is grounded, and the control end of the third switch is connected with the logic circuit (Q end); the fourth switch is connected in parallel on the second capacitor, the control termination logic circuit (QB end) of the fourth switch, the positive end of the first comparator and the positive end of the second comparator are connected with each other and connected on the feedback regulation circuit (the output end of the third comparator), the negative end of the first comparator is connected with one end of the first capacitor, the negative end of the second comparator is connected with one end of the second capacitor, and the output ends of the first comparator and the second comparator are connected with the logic circuit.
In order to further realize the invention, the following arrangement mode is adopted: the feedback adjusting circuit comprises a fourth resistor, a third capacitor and a third comparator; the fourth resistor is connected with the oscillation generating circuit and the negative input end of the third comparator, the third capacitor is connected between the negative input end and the output end of the third comparator, and the positive input end of the third comparator is connected with the reference generating circuit; one end of the fourth resistor is connected with the drain electrode of the seventh PMOS tube of the oscillation generating circuit, the other end of the fourth resistor and one end of the third capacitor are connected with each other and are connected with the negative input end of the third comparator, the other end of the third capacitor is connected with the output end of the third comparator, and the positive input end of the third comparator is connected with the grid electrode of the first NMOS tube of the reference generating circuit.
In order to further realize the invention, the following arrangement mode is adopted: the logic circuit comprises a first Schmitt trigger, a second Schmitt trigger and an RS trigger; the input ends of the first Schmitt trigger and the second Schmitt trigger are connected to the oscillation generating circuit, the output end of the first Schmitt trigger is connected with the S end of the RS trigger, the output end of the second Schmitt trigger is connected with the R end of the RS trigger, and the RS trigger outputs a logic control signal to control the oscillation generating circuit; namely, the input end of the first schmitt trigger is connected with the output end of the first comparator of the oscillation generating circuit, the output end of the first schmitt trigger is connected with the S end of the RS trigger, the input end of the second schmitt trigger is connected with the output end of the second comparator of the oscillation generating circuit, the output end of the second schmitt trigger is connected with the R end of the RS trigger, the forward output end of the RS trigger forms the Q end of the logic circuit, and the reverse output end of the RS trigger forms the QB end of the logic circuit.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the self-biased cascode current mirror is adopted, so that the current copying precision is improved, the output frequency of the oscillator is only related to the first resistor, the second resistor, the first capacitor and the second capacitor, the influence of temperature and voltage is obviously reduced, and the output frequency of the oscillator is stable; the feedback regulating circuit is arranged, the overturning voltage of the comparator is regulated according to the delay change of the comparator, and the influence of the delay of the comparator on the frequency of the oscillator is reduced; the reference voltage and the bias current are integrated, the structure is simple, and the cost and the circuit area are reduced.
Drawings
FIG. 1 is a block diagram of the present invention.
Fig. 2 is a schematic circuit diagram of the present invention.
FIG. 3 is a timing diagram of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the equipment or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
It is worth noting that: in the present application, when it is necessary to apply the known technology or the conventional technology in the field, the applicant may have the case that the known technology or/and the conventional technology is not specifically described in the text, but the technical means is not specifically disclosed in the text, and the present application is considered to be not in compliance with the twenty-sixth clause of the patent law.
Example 1:
the invention designs an RC oscillator with stable frequency, which is an RC oscillator with low temperature drift and high power supply rejection ratio, has the characteristics of simple structure, small influence by temperature and power supply voltage and stable frequency, and particularly adopts the following arrangement structure as shown in figures 1 and 2: comprises that
The reference generating circuit is used for generating fixed bias current and bias voltage, and the bias voltage is generated by the bias current flowing through the bias resistor;
an oscillation generating circuit for generating a frequency signal, which is a periodic signal relating only to the resistance and the capacitance, using a reference of the reference generating circuit;
the feedback regulating circuit is used for regulating the comparison reference voltage of the comparator according to the delay change of the comparator in the oscillation generating circuit and eliminating the delay influence of the comparator;
the logic circuit is used for receiving the output signal of the oscillation generating circuit, controlling a switch in the oscillation generating circuit and generating a periodic clock signal through switching of the switch;
the reference generating circuit is connected with the oscillation generating circuit, the oscillation generating circuit is connected with the logic circuit, and the feedback adjusting circuit is connected with the oscillation generating circuit.
Example 2:
the present embodiment is further optimized based on the above embodiment, and the same parts as those in the foregoing technical solution will not be described herein again, as shown in fig. 1 to fig. 2, in order to further better implement the present invention, the following setting manner is particularly adopted: the reference generating circuit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first resistor, a second resistor, a third resistor and a power supply; the first resistor and the second resistor are connected in series and are connected between the grid electrode and the source electrode of the first NMOS tube, namely, one end of the first resistor is grounded, one end of the second resistor is connected with the other end of the first resistor, the other end of the second resistor is connected with the grid electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded; the grid electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the grid electrode of the second NOMS tube is connected with the drain electrode of the first NMOS tube, the third resistor is connected between the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube, namely, one end of the third resistor is connected with the drain electrode of the second NOMS tube, the other end of the third resistor is connected with the drain electrode of the third PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are connected with each other and are connected with the drain electrode of the second NMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are connected with each other and are connected with the drain electrode of the third PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the fourth PMOS tube, and the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected with a power supply; the common node of the third PMOS tube and the fourth PMOS tube and the common node of the fifth PMOS tube and the sixth PMOS tube are connected to the oscillation generating circuit, namely the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are both connected with the grid electrode of the seventh PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are both connected with the grid electrode of the eighth PMOS tube, and the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected with the source electrode of the eighth PMOS tube and are both powered.
Example 3:
the present embodiment is further optimized based on any of the above embodiments, and parts that are the same as the above technical solutions will not be described herein again, as shown in fig. 1 to fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the first and second resistors have opposite temperature coefficients.
Example 4:
the present embodiment is further optimized based on any of the above embodiments, and parts that are the same as the above technical solutions will not be described herein again, as shown in fig. 1 to fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the oscillation generating circuit comprises a seventh PMOS tube, an eighth PMOS tube, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a first comparator and a second comparator; the source electrode and the grid electrode of the eighth PMOS tube are both connected with a reference generating circuit (namely the source electrode of the eighth PMOS tube is connected with a power supply, and the grid electrode of the eighth PMOS tube is connected with the grid electrode of the fifth PMOS tube), the source electrode of the seventh PMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the seventh PMOS tube is connected with the reference generating circuit (the grid electrode of the third PMOS tube), one end of the first switch and one end of the second switch are connected with each other and are connected with the drain electrode of the seventh PMOS tube, the other end of the first switch is connected with one end of the first capacitor, the control end of the first switch is connected with a logic circuit (a QB end), and the other end of the first capacitor is grounded; the other end of the second switch is connected with one end of a second capacitor, the control end of the second switch is connected with a logic circuit (Q end), and the other end of the second capacitor is grounded; one end of the third switch is connected with one end of the first capacitor, the other end of the third switch is grounded, and the control end of the third switch is connected with the logic circuit (Q end); the fourth switch is connected in parallel on the second capacitor, the control termination logic circuit (QB end) of the fourth switch, the positive end of the first comparator and the positive end of the second comparator are connected with each other and connected on the feedback regulation circuit (the output end of the third comparator), the negative end of the first comparator is connected with one end of the first capacitor, the negative end of the second comparator is connected with one end of the second capacitor, and the output ends of the first comparator and the second comparator are connected with the logic circuit.
Example 5:
the present embodiment is further optimized based on any of the above embodiments, and parts that are the same as the above technical solutions will not be described herein again, as shown in fig. 1 to fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the feedback adjusting circuit comprises a fourth resistor, a third capacitor and a third comparator; the fourth resistor is connected with the oscillation generating circuit and the negative input end of the third comparator, the third capacitor is connected between the negative input end and the output end of the third comparator, and the positive input end of the third comparator is connected with the reference generating circuit; one end of the fourth resistor is connected with the drain electrode of the seventh PMOS tube of the oscillation generating circuit, the other end of the fourth resistor and one end of the third capacitor are connected with each other and are connected with the negative input end of the third comparator, the other end of the third capacitor is connected with the output end of the third comparator, and the positive input end of the third comparator is connected with the grid electrode of the first NMOS tube of the reference generating circuit.
Example 6:
the present embodiment is further optimized based on any of the above embodiments, and parts that are the same as the above technical solutions will not be described herein again, as shown in fig. 1 to fig. 2, in order to further better implement the present invention, the following setting modes are particularly adopted: the logic circuit comprises a first Schmitt trigger, a second Schmitt trigger and an RS trigger; the input ends of the first Schmitt trigger and the second Schmitt trigger are connected to the oscillation generating circuit, the output end of the first Schmitt trigger is connected with the S end of the RS trigger, the output end of the second Schmitt trigger is connected with the R end of the RS trigger, and the RS trigger outputs a logic control signal to control the oscillation generating circuit; namely, the input end of the first schmitt trigger is connected with the output end of the first comparator of the oscillation generating circuit, the output end of the first schmitt trigger is connected with the S end of the RS trigger, the input end of the second schmitt trigger is connected with the output end of the second comparator of the oscillation generating circuit, the output end of the second schmitt trigger is connected with the R end of the RS trigger, the forward output end of the RS trigger forms the Q end of the logic circuit, and the reverse output end of the RS trigger forms the QB end of the logic circuit.
Example 7:
referring to fig. 1, fig. 1 is a block diagram of an RC oscillator of the present invention, which specifically includes a reference generating circuit 110, an oscillation generating circuit 120, a feedback adjusting circuit 130, and a logic circuit 140.
A reference generation circuit 110 connected to the oscillation generation circuit, for generating a fixed bias current and a bias voltage, and the bias voltage is generated by the bias current flowing through a bias resistor;
an oscillation generating circuit 120, connected to the feedback adjusting circuit and the logic circuit, respectively, for generating a frequency signal with the reference of the reference generating circuit, wherein the frequency signal is only a periodic signal related to the resistor and the capacitor;
the feedback adjusting circuit 130 is connected with the oscillation generating circuit and used for receiving the signal of the oscillation generating circuit and adjusting the comparison reference voltage of the comparator according to the delay variation of the comparator in the oscillation generating circuit so as to eliminate the influence of the delay of the comparator;
and a logic circuit 140 for receiving the output signal of the oscillation generating circuit, generating a periodic clock signal, and controlling the switching of the switches in the oscillation generating circuit to alternately charge and discharge the oscillation generating circuit.
Specifically, referring to fig. 2 in conjunction with fig. 2, fig. 2 is a schematic circuit diagram of the RC oscillator of the present invention. As shown in fig. 2, the reference generating circuit may specifically include: the transistor comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a third PMOS transistor MP1, a fourth PMOS transistor MP2, a fifth PMOS transistor MP3, a sixth PMOS transistor MP4, a first resistor R1, a second resistor R2, a third resistor R3 and a power supply; wherein, one end of the first resistor R1 is grounded, one end of the second resistor R2 is connected to the other end of the first resistor R1, the other end of the second resistor R2 is connected to the gate of the first NMOS MN1, the source of the first NMOS MN1 is grounded, the gate of the first NMOS MN1 is connected to the source of the second NMOS MN2, the gate of the second NMOS MN2 is connected to the drain of the first NMOS MN1, one end of the third resistor R3 is connected to the drain of the second NMOS MN2, the other end of the third resistor R3 is connected to the drain of the third PMOS MP1, the gate of the third PMOS MP1 and the gate of the fourth PMOS MP2 are connected to each other and to the drain of the second NMOS 2, the drain of the fourth PMOS MP2 is connected to the drain of the first NMOS 1, the drain of the fifth PMOS MP3 is connected to the source of the third PMOS MP1, the gate of the fifth PMOS MP3 and the sixth PMOS MP3 are connected to the drain of the fourth PMOS 363672, the source electrode of the fifth PMOS transistor MP3 and the source electrode of the sixth PMOS transistor MP4 are connected with the power supply; the first resistor R1 and the second resistor R2 have opposite temperature coefficients, and the proportion of the first resistor R1 and the second resistor R2 can be adjusted appropriately to generate the temperature-independent resistor R1+ R2.
The oscillation generating circuit may specifically include: a seventh PMOS transistor MP5, an eighth PMOS transistor MP6, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, a second capacitor C2, a first comparator COMP1, and a second comparator COMP 2; the source of the eighth PMOS transistor MP6 is connected to the power supply, the gate of the eighth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP3, the source of the seventh PMOS transistor MP5 is connected to the drain of the eighth PMOS transistor MP6, the gate of the seventh PMOS transistor MP5 is connected to the gate of the third PMOS transistor MP1, one end of the first switch S1 and one end of the second switch S2 are connected to each other and to the drain of the seventh PMOS transistor MP5, the other end of the first switch S1 is connected to one end of the first capacitor C1, the control end of the first switch S1 is connected to the QB terminal of the logic circuit, the other end of the first capacitor C1 is connected to ground, the other end of the second switch S2 is connected to one end of the second capacitor C2, the control end of the second switch S2 is connected to the Q terminal of the logic circuit, the other end of the second capacitor C2 is connected to ground, one end of the third switch S3 is connected to one end of the first capacitor C1, the control end of the third switch S1 is connected to the logic circuit C3, one end of a fourth switch S4 is connected to one end of the second capacitor C2, the other end of the fourth switch S4 is connected to the other end of the second capacitor C2, a control end of the fourth switch S4 is connected to the QB terminal of the logic circuit, a positive terminal of the first comparator COMP1 and a positive terminal of the second comparator COMP2 are connected to each other and to an output terminal of a third comparator COMP3 of the feedback regulation circuit, a negative terminal of the first comparator COMP1 is connected to one end of the first capacitor C1, and a negative terminal of the second comparator COMP2 is connected to one end of the second capacitor C2.
The feedback adjusting circuit may specifically include: a fourth resistor R4, a third capacitor C3 and a third comparator COMP 3; one end of the fourth resistor R4 is connected to the drain of the seventh PMOS transistor MP5 of the oscillation generating circuit, the other end of the fourth resistor R4 and one end of the third capacitor C3 are connected to each other and to the negative input terminal of the third comparator COMP3, the other end of the third capacitor C3 is connected to the output terminal of the third comparator COMP3, and the positive input terminal of the third comparator COMP3 is connected to the gate node Vref of the first NMOS transistor MN1 of the reference generating circuit.
The logic circuit may specifically include a first schmitt trigger M1, a second schmitt trigger M2, and an RS trigger; the input end of the first schmitt trigger M1 is connected to the output end of the first comparator COMP1 of the oscillation generating circuit, the output end of the first schmitt trigger M1 is connected to the S end of the RS trigger, the input end of the second schmitt trigger M2 is connected to the output end of the second comparator COMP2 of the oscillation generating circuit, the output end of the second schmitt trigger M2 is connected to the R end of the RS trigger, the forward output end of the RS trigger is the Q end, and the reverse output end of the RS trigger is the QB end.
Referring to fig. 2 again, the working principle of the RC oscillator of the present invention is:
when the reference generating circuit works normally, the currents flowing through the third PMOS transistor MP1 and the fourth PMOS transistor MP2 are equal, and the first NMOS transistor MN1 works in a saturation region, so that the reference generating circuit can obtain
Figure BDA0003253761270000131
Figure BDA0003253761270000132
Wherein, munIs the mobility of NMOS transistor, CoxIs a gate-oxide capacitor (GOP) with a high capacitance,
Figure BDA0003253761270000133
is the width-to-length ratio, V, of the first NMOS transistor MN1GSIs the gate-source voltage, V, of the first NMOS transistor MN1thIs the threshold voltage, R, of the first NMOS transistor MN11Is the resistance value of the first resistor, R2Is the resistance value of the second resistor;
the bias current value generated by the reference generation circuit can be determined by the equations (1) and (2), and it can be seen that the influence of the temperature on the threshold voltage of the first NMOS transistor MN1 directly influences the bias current value.
The bias current I is copied to an oscillation generating circuit through a current mirror formed by a third PMOS tube MP1, a fifth PMOS tube MP3, a seventh PMOS tube MP5, an eighth PMOS tube MP6 and a third resistor R3 to generate a charging current KI, wherein K is the ratio of the width to length of the eighth PMOS tube MP6 to the width to length of the fifth PMOS tube MP3, and the current copying precision is high due to the adoption of a self-biased cascode current mirror structure, so that errors generated in the current copying process can be ignored.
Referring to fig. 3 for analysis, fig. 3 is a timing diagram of the RC oscillator of the present invention. As shown, at T1At the moment, the timing sequence of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 shows that the charging current charges the first capacitor C1, the charging loop of the second capacitor C2 is opened, the discharging loop is closed, the second capacitor C2 discharges rapidly, the output of the second comparator COMP2 is constantly high, the initial output of the first comparator COMP1 is low, and when the first capacitor C1 charges to the upper plate voltage and the upper plate voltage exceeds V, the upper plate voltage exceeds VFBTime-delayed T by comparatordTo T2At the moment, the output of the first comparator COMP1 flips to low level, passing through the RS flip-flop in the logic circuitThe voltages output by the Q end and the QB end are inverted, so that the charging current is used for charging the second capacitor C2, and the first capacitor C1 discharges rapidly; in a similar manner, at T2At the moment, the charging current charges the second capacitor C2, the charging loop of the first capacitor C1 is disconnected, the discharging loop is closed, the first capacitor C1 is rapidly discharged, the output of the first comparator COMP1 is constantly at a high level, the output of the second comparator COMP2 is initially at a low level, and when the second capacitor C2 is charged until the voltage of the upper electrode plate exceeds V and the voltage of the upper electrode plate exceeds VFBTime-delayed T by comparatordTo T3At the moment, the output of the second comparator COMP2 is inverted to be low level, the voltages output by the Q end and the QB end are inverted through an RS trigger in the logic circuit, so that the charging current charges the first capacitor C1, and the second capacitor C2 discharges rapidly; the oscillation generating circuit and the logic circuit are sequentially reciprocated to form continuous clock square wave signals, and meanwhile stray noise influence can be eliminated by the first Schmitt trigger M1 and the second Schmitt trigger M2, so that false triggering of the triggers is prevented, and output stability is improved.
In the invention, the node voltage of the common end point of the first switch S1 and the second switch S2 is Vx, as can be seen by referring to the timing diagram of fig. 3, Vx is the superposition of the upper plate voltages of the first capacitor C1 and the second capacitor C2 in the charging stage, which are presented in the form of sawtooth wave periodic signals, and a smooth direct current signal with an average value Vm/2 is obtained after passing through a low-pass filter composed of the fourth resistor R4 and the third capacitor C3; when the time delay of a first comparator COMP1 and a second comparator COMP2 in the oscillation generating circuit is increased due to the change of temperature or power supply voltage, the peak value Vm of the Vx sawtooth wave is increased, the difference value between the Vref and the Vref is reduced, and after the Vx sawtooth wave is amplified by a third comparator COMP3, the output voltage V is outputFBDecreasing, causing the first comparator COMP1 and the second comparator COMP2 to flip ahead; when the time delay of the first comparator COMP1 and the second comparator COMP2 is reduced, the same can be obtained, and the output voltage V is obtainedFBIncreasing, delaying the first comparator COMP1 and the second comparator COMP2 to flip; through the negative feedback regulation of the feedback regulation circuit, the influence of temperature and voltage on the time delay of the comparator is eliminated, and the frequency stability of the RC oscillating circuit is improved.
To further illustrate the RC oscillator principle of the present invention, please refer to fig. 2 and fig. 3 to perform a quantitative analysis on the circuit principle.
Due to the gate-source voltage V of the first NMOS transistor MN1GSVref, obtained from formula (1)
Vref＝I*(R1+R2) (3)
Peak value of sawtooth wave Vx
Vm＝VFB+Vdelay (4)
Wherein, VdelayFor the comparator delaying time TdVoltage, V, produced by internal VxFBIs the voltage at the output terminal of the third comparator COMP 3;
assuming that the capacitance values of the first capacitor C1 and the second capacitor C2 are equal, the oscillation period of the RC oscillation circuit
Figure BDA0003253761270000151
Wherein C is a capacitance value of the first capacitor C1 and the second capacitor C2, K is a ratio of a width to a length of the eighth PMOS transistor MP6 to a width to a length of the fifth PMOS transistor MP3, and I is a current flowing through the third PMOS transistor MP1 or the fourth PMOS transistor MP 2;
fourier series expansion of the sawtooth wave signal Vx as
Figure BDA0003253761270000152
Wherein
Figure BDA0003253761270000153
The angular frequency of the sawtooth wave signal Vx;
after passing through a low pass filter composed of a fourth resistor R4 and a third capacitor C3, the DC component of the signal generated by the equation (6) is
Figure BDA0003253761270000154
The output of the third comparator COMP3
Figure BDA0003253761270000155
Where a is the gain of the third comparator COMP 3;
is obtainable from the formula (7)
Figure BDA0003253761270000156
Since the ratio of A > 2 is high,
VFB≈2*Vref-Vdelay (9)
from the expressions (3), (5) and (9), the oscillation period of the RC oscillation circuit can be obtained
Figure BDA0003253761270000157
The oscillation frequency of the RC oscillation circuit is
Figure BDA0003253761270000161
In summary, the oscillation frequency of the RC oscillator of the invention is only equal to the ratio K of the width to length ratios of the eighth PMOS transistor MP6 and the fifth PMOS transistor MP3, the capacitance C of the first capacitor C1 and the second capacitor C2, and the resistance R of the first resistor R1 and the second resistor R21+R2In which R is1+R2K is irrelevant to temperature, and the temperature coefficient of the capacitor is very small in the modern process, so that through the optimized design of the circuit structure, the RC oscillator offsets the influence of bias current and bias voltage on oscillation frequency, and simultaneously eliminates the influence of comparator delay on oscillation frequency, thereby obtaining stable output frequency.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.

Claims (6)

1. A frequency-stabilized RC oscillator, characterized by: comprises that
The reference generating circuit is used for generating fixed bias current and bias voltage, and the bias voltage is generated by the bias current flowing through the bias resistor;
an oscillation generating circuit for generating a frequency signal, which is a periodic signal relating only to the resistance and the capacitance, using a reference of the reference generating circuit;
the feedback regulating circuit is used for regulating the comparison reference voltage of the comparator according to the delay change of the comparator in the oscillation generating circuit and eliminating the delay influence of the comparator;
the logic circuit is used for receiving the output signal of the oscillation generating circuit, controlling a switch in the oscillation generating circuit and generating a periodic clock signal through switching of the switch;
the reference generating circuit is connected with the oscillation generating circuit, the oscillation generating circuit is connected with the logic circuit, and the feedback adjusting circuit is connected with the oscillation generating circuit.
2. A frequency-stabilized RC oscillator as claimed in claim 1, wherein: the reference generating circuit comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first resistor, a second resistor, a third resistor and a power supply; the first resistor and the second resistor are connected in series and are connected between the grid electrode and the source electrode of the first NMOS tube; the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the grid electrode of the second NOMS tube is connected with the drain electrode of the first NMOS tube, the third resistor is connected between the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are connected with each other and are connected to the drain electrode of the second NMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are connected with each other and are connected to the drain electrode of the third PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected with a power supply, and the common nodes of the third PMOS tube and the fourth PMOS tube, and the common nodes of the fifth PMOS tube are both connected to a generation circuit.
3. A frequency-stabilized RC oscillator as claimed in claim 2, wherein: the first and second resistors have opposite temperature coefficients.
4. A frequency-stabilized RC oscillator as claimed in claim 1, wherein: the oscillation generating circuit comprises a seventh PMOS tube, an eighth PMOS tube, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, a first comparator and a second comparator; the source electrode and the grid electrode of the eighth PMOS tube are both connected with the reference generating circuit, the source electrode of the seventh PMOS tube is connected with the drain electrode of the eighth PMOS tube, the grid electrode of the seventh PMOS tube is connected with the reference generating circuit, one end of the first switch and one end of the second switch are mutually connected and are connected with the drain electrode of the seventh PMOS tube, the other end of the first switch is connected with one end of the first capacitor, the control end of the first switch is connected with the logic circuit, and the other end of the first capacitor is grounded; the other end of the second switch is connected with one end of a second capacitor, the control end of the second switch is connected with the logic circuit, and the other end of the second capacitor is grounded; one end of the third switch is connected with one end of the first capacitor, the other end of the third switch is grounded, and the control end of the third switch is connected with the logic circuit; the fourth switch is connected in parallel to the second capacitor, the control end of the fourth switch is connected with the logic circuit, the positive end of the first comparator and the positive end of the second comparator are connected with each other and connected to the feedback adjusting circuit, the negative end of the first comparator is connected with one end of the first capacitor, the negative end of the second comparator is connected with one end of the second capacitor, and the output ends of the first comparator and the second comparator are connected with the logic circuit.
5. A frequency-stabilized RC oscillator as claimed in claim 1, wherein: the feedback adjusting circuit comprises a fourth resistor, a third capacitor and a third comparator; the fourth resistor is connected to the oscillation generating circuit and the negative input end of the third comparator, the third capacitor is connected between the negative input end and the output end of the third comparator, and the positive input end of the third comparator is connected to the reference generating circuit.
6. A frequency-stabilized RC oscillator as claimed in claim 1, wherein: the logic circuit comprises a first Schmitt trigger, a second Schmitt trigger and an RS trigger; the input ends of the first Schmitt trigger and the second Schmitt trigger are connected to the oscillation generating circuit, the output end of the first Schmitt trigger is connected with the S end of the RS trigger, the output end of the second Schmitt trigger is connected with the R end of the RS trigger, and the RS trigger outputs a logic control signal to control the oscillation generating circuit.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114726315A (en) * 2022-06-01 2022-07-08 苏州聚元微电子股份有限公司 RC relaxation oscillation circuit and RC relaxation oscillator
WO2023168820A1 (en) * 2022-03-11 2023-09-14 长鑫存储技术有限公司 Bias signal generation circuit and clock input circuit
CN117879495A (en) * 2024-01-09 2024-04-12 武汉芯必达微电子有限公司 Oscillator circuit and method for eliminating clock frequency overshoot
WO2024120173A1 (en) * 2022-12-07 2024-06-13 深圳飞骧科技股份有限公司 Rc oscillator circuit

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090160557A1 (en) * 2007-12-20 2009-06-25 Infineon Technologies Ag Self-biased cascode current mirror
CN102045041A (en) * 2011-01-17 2011-05-04 上海宏力半导体制造有限公司 Resistance-capacitance (RC) oscillator and realization method thereof
JP2012095510A (en) * 2010-10-29 2012-05-17 Honda Motor Co Ltd Power supply unit
CN103546123A (en) * 2013-11-01 2014-01-29 东南大学 High-linearity relaxation oscillator
CN108494385A (en) * 2018-03-05 2018-09-04 上海华虹宏力半导体制造有限公司 Low-frequency oscillatory network and bias voltage and current generating circuit
CN112104361A (en) * 2020-09-14 2020-12-18 中国科学院微电子研究所 Relaxation oscillator-based clock generation circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090160557A1 (en) * 2007-12-20 2009-06-25 Infineon Technologies Ag Self-biased cascode current mirror
JP2012095510A (en) * 2010-10-29 2012-05-17 Honda Motor Co Ltd Power supply unit
CN102045041A (en) * 2011-01-17 2011-05-04 上海宏力半导体制造有限公司 Resistance-capacitance (RC) oscillator and realization method thereof
CN103546123A (en) * 2013-11-01 2014-01-29 东南大学 High-linearity relaxation oscillator
CN108494385A (en) * 2018-03-05 2018-09-04 上海华虹宏力半导体制造有限公司 Low-frequency oscillatory network and bias voltage and current generating circuit
CN112104361A (en) * 2020-09-14 2020-12-18 中国科学院微电子研究所 Relaxation oscillator-based clock generation circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023168820A1 (en) * 2022-03-11 2023-09-14 长鑫存储技术有限公司 Bias signal generation circuit and clock input circuit
CN114726315A (en) * 2022-06-01 2022-07-08 苏州聚元微电子股份有限公司 RC relaxation oscillation circuit and RC relaxation oscillator
WO2024120173A1 (en) * 2022-12-07 2024-06-13 深圳飞骧科技股份有限公司 Rc oscillator circuit
CN117879495A (en) * 2024-01-09 2024-04-12 武汉芯必达微电子有限公司 Oscillator circuit and method for eliminating clock frequency overshoot

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