CN113948379A - Preparation method of nano gate, nano gate and application - Google Patents
Preparation method of nano gate, nano gate and application Download PDFInfo
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- CN113948379A CN113948379A CN202010691398.3A CN202010691398A CN113948379A CN 113948379 A CN113948379 A CN 113948379A CN 202010691398 A CN202010691398 A CN 202010691398A CN 113948379 A CN113948379 A CN 113948379A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a preparation method of a nano gate, and also provides the nano gate prepared by the method and application. The method can simplify the preparation of the nano-scale gate, accurately control the long dimension of the gate, realize the preparation of a nano-gate device and further improve the performance of an electronic device.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a preparation method of a nano gate, the nano gate and application.
Background
In the field of integrated circuits, there is a constant trend toward higher integration levels, and new processes and techniques are continually developed to achieve smaller line width chips, and are approaching their physical limits.
The gate is the control terminal of the transistor and the gate size has a significant impact on the performance of the electronic device. At present, the processing of nanoscale gate length dimensions for devices becomes increasingly difficult. When an electronic device is prepared by using the existing photoetching technology, the gate length of the electronic device not only depends on the resolution of photoetching equipment, but also depends on various influence factors such as photoresist types, baking temperature, exposure dose, developing temperature and time in the photoetching process. This results in devices with gate length dimensions that are not easily controlled precisely, especially with gates of nanometer scale that are difficult to fabricate. At present, the nano gate is mainly prepared by combining an extreme ultraviolet lithography machine with a FIN-FET process, the cost is high, the requirement on equipment is high, and the production is not easy.
In addition to the preparation of fine patterns having a size of 100nm or less using an extreme ultraviolet lithography machine, the preparation can be carried out by Electron Beam Lithography (EBL), and a fine structure having a wavelength of 10nm or less can be prepared by making the electron beam have a very short de Broglie wavelength. However, EBL is inefficient, has a strong proximity effect, has a high requirement for the stability of the device, and has a great problem in the developing and etching processes for electron beam exposure.
In order to maintain the continuous development of the integrated circuit industry, a new preparation method needs to be developed, so that the preparation of a gate with a nanoscale can be simplified, the long dimension of the gate can be accurately controlled, the preparation of a nano-gate device can be realized, and the performance of an electronic device can be further improved.
Disclosure of Invention
The invention aims to provide a method for preparing a nano gate by combining a thin film deposition technology aiming at the defects of the existing means and the preparation and acquisition of the nano gate, so that the preparation process of a device is improved, and the preparation cost of the device is reduced.
Before setting forth the context of the present invention, the terms used herein are defined as follows:
the term "ALD" refers to: atom layer Deposition.
The term "CMP" refers to: chemical Mechanical Polishing.
The term "RIE" refers to: reaction ion etching.
The term "PECVD" refers to: plasma Enhanced Chemical Vapor Deposition, Plasma Enhanced Chemical Vapor Deposition.
The term "ICP-CVD" means: inductively Coupled Plasma Chemical Vapor Deposition.
The term "DUV lithography" refers to: deep ultraviolet lithography.
The term "EUV lithography" refers to: and (4) performing extreme ultraviolet lithography.
The term "CMOS" refers to: a complementary metal oxide semiconductor.
The term "NAND" refers to: not AND, computer flash memory device.
The term "PSG" refers to: phosphosilicate glass.
The term "ICP" refers to: inductively coupled plasma.
The term "MESFET" refers to: Metal-Semiconductor Field Effect Transistor (MOSFET).
The term "MOSFET" refers to: Metal-Oxide-Semiconductor Field-Effect Transistor.
In order to achieve the above object, a first aspect of the present invention provides a method for manufacturing a nanogate, the method comprising the steps of:
(1) providing a wafer required by process preparation;
(2) coating a photoresist material on the wafer;
(3) preparing the photoresist material in the step (2) into a formed structure by utilizing a photoetching technology;
(4) depositing a first isolation layer material to coat the graph structure;
(5) depositing a second isolation layer material, filling the groove and covering the surface;
(6) flattening the surface of the material obtained in the step (5) to obtain a flat surface and expose a composite structure of the photoresist material and the first and second isolation layers which are arranged alternately;
(7) removing the photoresist material to form a new pattern structure on the surface of the wafer;
(8) depositing a third isolation layer material, filling the groove of the new pattern structure and covering the surface;
(9) flattening the surface of the material obtained in the step (8) to enable the height of the pattern on the surface of the wafer after flattening to be the height of the composite structure prepared in the step (6), and forming a structure with the first, second and third isolating layers arranged alternately on the surface;
(10) etching to remove the first isolation layer material between the adjacent second isolation layer and the third isolation layer to the surface of the wafer;
(11) depositing a grid material, filling the grid groove and covering the surface;
(12) carrying out process treatment on the material obtained in the step (11), removing the grid electrode material on the surface to the surfaces of the second isolation layer and the third isolation layer, and obtaining a structure in which the third isolation layer, the nano-grid, the second isolation layer and the composite isolation layer formed by the first isolation layer are arranged alternately on the surface;
wherein, the second isolation layer and the third isolation layer are made of the same material.
The method according to the first aspect of the present invention, wherein the wafer in step (1) has a planarized surface;
preferably, the wafer material is selected from one or more of: a semiconductor substrate of silicon, gallium arsenic, silicon carbide, gallium nitrogen, indium phosphorus, or the like;
more preferably, the wafer is a wafer with a functional layer.
The method according to the first aspect of the present invention, wherein the photoresist-based material in the step (2) comprises a photoresist and/or a photosensitive polyimide.
The method according to the first aspect of the invention, wherein the material of the barrier layer is selected from one or more of: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, alpha silicon, or the like;
preferably, the etching selection ratio of the materials of the first isolation layer and the second isolation layer is greater than 2: 1.
The method according to the first aspect of the present invention, wherein the deposition method in steps (4), (5), (8) is a thin film deposition technique, preferably the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering;
the thickness of the first isolation layer material in the step (4) is the line width of the nano gate;
preferably, the line width of the nano gate is 100nm or less, preferably 28nm or less, more preferably 14nm or less, still more preferably 7nm or less, further preferably 5nm or less, and most preferably 3nm or less; and/or
The processing method in the step (12) is selected from CMP and/or etching technology;
preferably, the etching technique is selected from one or more of: argon ion etching, RIE technique, ICP technique.
The method according to the first aspect of the present invention, wherein the pattern preparation technique in step (3) is selected from one or more of: lithography, electron beam exposure, laser direct writing;
preferably, the lithographic technique is selected from one or more of: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.
The method according to the first aspect of the present invention is characterized in that the pattern structure described in the step (3) has a pitch between patterns twice as large as a thickness of the first spacer.
The method according to the first aspect of the present invention is characterized in that the method for depositing the gate material in step (11) is a thin film preparation technique, preferably, the thin film preparation technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, electron beam evaporation, and the like;
the material of the nano gate is selected from one or more of the following materials: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polysilicon, and the like.
The method according to the first aspect of the present invention, wherein the planarization method in steps (6), (9) is selected from one or more of the following: CMP technique, PSG technique, ion selective bombardment;
CMP techniques are preferred.
The method according to the first aspect of the invention, further comprising the steps of:
(13) processing the non-nano gate reserved area by adopting a conventional process to obtain a required mesa structure;
preferably, the conventional process is selected from one or more of the following: photolithography, wet etching, dry etching, and the like.
A second aspect of the invention provides a nanograting prepared according to the method of the first aspect;
preferably, the line width of the nano gate is 100nm or less, preferably 28nm or less, more preferably 14nm or less, still more preferably 7nm or less, further preferably 5nm or less, most preferably 3nm or less, and 1nm or more; and/or
The material of the nano gate is selected from one or more of the following materials: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polysilicon, and the like.
A third aspect of the present invention provides a semiconductor device comprising a nanogate produced by the production method according to the first aspect and/or the nanogate according to the second aspect;
preferably, the semiconductor device is selected from one or more of: integrated circuit, CMOS, MESFET, MOSFET, NAND Flash, NOR Flash, DRAM.
The present invention relates to the field of semiconductor device fabrication, not only discrete devices, but also integrated circuit fabrication, and more particularly, to a method for fabricating a nanogate by thin film deposition.
The invention aims to provide a method for preparing a nano gate by combining a thin film deposition technology aiming at the defects of the existing means and the preparation and acquisition of the nano gate, so that the preparation process of a device is improved, and the preparation cost of the device is reduced.
The invention provides a structure for preparing a nano gate by combining a thin film deposition technology, which comprises the following components in sequence from bottom to top:
wafers required by the process;
the composite isolation layer is formed by the third isolation layer, the nano gate, the first isolation layer and the second isolation layer;
a planarized material surface;
preferably, the wafer includes but is not limited to a silicon substrate, a gallium arsenic substrate, and the like;
preferably, the wafer refers to a wafer with a functional layer;
preferably, the materials of the first, second and third isolation layers include, but are not limited to, silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, etc.;
preferably, the second isolation layer and the third isolation layer are made of the same material;
preferably, the etching selection ratio between the first isolation layer and the second isolation layer is not less than 2; 1;
preferably, the first, second and third isolation layers are prepared by methods including, but not limited to, ALD, PECVD, ICP-CVD, LPCVD, etc.;
preferably, the material of the nano-gate includes, but is not limited to, gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polysilicon, and the like.
Preferably, the nano-grid is prepared by means of electron beam evaporation, sputtering, chemical deposition, and the like.
The invention provides a method for preparing a nano gate by using a thin film deposition technology, which comprises the following steps:
providing a wafer required by process preparation;
coating a photoresist material on the wafer;
preparing a graph structure on the surface of the wafer by utilizing a photoetching technology;
depositing a first isolation layer material to coat the graph structure;
depositing a second isolation layer material, filling the groove and covering the surface;
flattening the surface of the obtained material to obtain a flat surface and expose the photoresist material and a structure in which the first isolation layer and the second isolation layer are arranged alternately;
removing the photoresist material, and forming a new pattern structure on the surface of the wafer;
depositing a third isolation layer material, filling the groove and covering the surface of the new pattern structure;
flattening the surface of the obtained material to enable the height of the wafer surface graph after flattening to be the height of the structure corresponding to the last flattening process;
etching to remove the first isolation layer material between the adjacent second and third isolation layers to the surface of the wafer;
depositing a grid material, filling the grid groove and covering the surface;
and carrying out process treatment on the obtained material, removing the grid material on the surface to the surfaces of the second isolation layer and the third isolation layer, and obtaining a structure with the third isolation layer, the nano-grid and the second isolation layer arranged alternately on the surface, wherein the process treatment method comprises CMP, large-area etching and the like.
And carrying out subsequent processes of the required preparation structure.
The wafer has a flattened surface, and not only comprises common substrate materials, such as substrates of silicon, gallium arsenic, silicon carbide and the like, but also comprises a wafer with a functional layer;
the photoresist materials include but are not limited to photoresist and photosensitive polyimide;
preparing a pattern structure on the surface of the wafer by utilizing a photoetching technology, wherein the distance between patterns is not less than two times of the thickness of the first isolation layer;
the first, second and third isolation layer materials are deposited by using a thin film deposition technology, wherein the thin film deposition technology comprises but is not limited to ALD, PECVD, ICP-CVD, LPCVD, reactive ion magnetron sputtering and other technologies;
the first, second and third isolation layer materials are deposited by using a thin film deposition technique, and the isolation layer materials include, but are not limited to, silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, alpha silicon and other materials;
preparing a related graph structure on the photoresist material by utilizing a photoetching technology or other graph preparation technologies, wherein the photoetching technology comprises common controllable photoetching technologies such as ultraviolet photoetching, DUV photoetching, EUV photoetching, immersion photoetching and the like;
preparing a related graph structure on the photoresist material by utilizing a photoetching technology or other graph preparation technologies, wherein the other graph preparation technologies comprise but are not limited to an electron beam exposure technology, a laser direct writing technology and other controllable graph preparation technologies;
the related graphic structure prepared on the photoresist material is not limited in structural shape, including but not limited to strip, circle and the like.
The second isolation layer and the third isolation layer are made of the same material;
the first isolation layer material and the second isolation layer material are grown by using a thin film deposition technology, and the etching selection ratio of the two materials is not less than 2: 1;
the gate material is deposited, the gate groove is filled and the surface is covered by utilizing a thin film deposition technology, wherein the thin film deposition technology comprises but is not limited to electron beam evaporation, sputtering, chemical deposition and the like;
the method comprises the steps of depositing a grid material by using a thin film deposition technology, filling a grid groove and covering the surface, wherein the metal material comprises but is not limited to gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polysilicon and other materials;
in the process, the non-nano gate reserved area can be processed by a conventional process to obtain the required mesa structure.
The length of the nano gate is the thickness of the first isolation layer, the thickness is not specifically specified, preferably less than 100nm, the current 14nm and 7nm process can be covered, even the process can be widened to 5nm and 3nm, and the line width is more than 1 nm.
The process result is a nano-gate structure, and the subsequent process application of the nano-gate comprises but is not limited to CMOS, NAND and other semiconductor devices.
The method of the present invention may have, but is not limited to, the following beneficial effects:
the method can simplify the preparation of the gate with the nanoscale, accurately control the long dimension of the gate, realize the preparation of the nano gate device and further improve the performance of the electronic device.
Drawings
Embodiments of the invention are described in detail below with reference to the attached drawing figures, wherein:
FIG. 1 shows a flow chart of an embodiment of the present invention.
FIG. 2 shows a schematic diagram of the preparation of a photoresist film according to an embodiment of the present invention.
FIG. 3 shows a schematic diagram of the fabrication of a patterned structure on a photoresist film in accordance with an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a patterned structure coated with a first isolation layer according to an embodiment of the invention.
Fig. 5 shows a schematic view of filling a trench with a second isolation layer according to an embodiment of the present invention.
FIG. 6 shows a schematic representation of an embodiment of the present invention after surface planarization by CMP.
FIG. 7 shows a schematic diagram of photoresist removal according to an embodiment of the present invention.
Fig. 8 shows a schematic view of filling a trench with a third isolation layer according to an embodiment of the present invention.
FIG. 9 shows a schematic representation of an embodiment of the present invention after surface planarization by CMP.
FIG. 10 is a schematic diagram illustrating an embodiment of the present invention using an etching technique to remove material from the first isolation layer between the second and third isolation layers to the surface of the wafer.
Fig. 11 is a schematic diagram illustrating the fabrication of a gate electrode using a thin film deposition technique according to an embodiment of the present invention.
Fig. 12 is a schematic diagram illustrating the removal of the gate material on the surfaces of the second and third isolation layers by using a CMP technique according to an embodiment of the present invention.
Description of reference numerals:
1. a wafer; 2. photoresist; 3A, 3B, 3C, a first isolation layer; 4. a second isolation layer; 5. a third isolation layer; 6. and a gate.
Detailed Description
The invention is further illustrated by the following specific examples, which, however, are to be construed as merely illustrative, and not limitative of the remainder of the disclosure in any way whatsoever.
This section generally describes the materials used in the testing of the present invention, as well as the testing methods. Although many materials and methods of operation are known in the art for the purpose of carrying out the invention, the invention is nevertheless described herein in as detail as possible. It will be apparent to those skilled in the art that the materials and methods of operation used in the present invention are well within the skill of the art, provided that they are not specifically illustrated.
Example 1
This example illustrates the method of fabricating a nanogate using thin film deposition techniques according to the invention.
The specific process is shown in fig. 1, and comprises the following steps:
s100: providing a wafer 1 required by process preparation;
s200: coating a uniform photoresist 2 film;
s300: preparing a strip-shaped graph structure on the photoresist 2;
s400: depositing first isolation layer materials 3A, 3B and 3C;
s500: depositing a second isolating layer material 4 to fill the groove;
s600: the material surface is planarized to remove the first isolation layer 3A.
S700: removing the photoresist;
s800: depositing a third isolation layer material 5;
s900: flattening the surface of the material;
s1000: removing the first isolation layer 3B;
s1100: depositing a gate metal 6;
s1200: and flattening the surface of the material, and removing the metal on the surface.
In this embodiment, the material of the wafer 1 in S100 may be selected from one or more of the following: silicon, gallium arsenic, silicon carbide, wafers with functional layers.
In a preferred embodiment, the material of the wafer 1 is a silicon substrate of (001) crystal orientation.
In a preferred embodiment, a photoresist film is prepared by using a spin coater, and the thickness of the photoresist is 150 nm;
the pattern preparation technique in S300 is selected from one or more of: lithography, electron beam exposure, laser direct writing; the lithographic technique is selected from one or more of: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.
In a preferred embodiment, a stripe-shaped photoresist structure with a pattern width of 50nm, a pattern pitch of 90nm and a period of 140nm is prepared by combining with a corresponding photolithography technique, as shown in FIG. 3.
The deposition method in S400 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating.
In S400, the thickness of the first isolation layer material 3 is 1nm or more.
The material of the barrier layer in this embodiment is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, alpha silicon, or the like;
the etching selection ratio of the materials of the first isolation layer and the second isolation layer is at least 2: 1.
in a preferred embodiment, the first spacer material 3 silicon oxide material is deposited at 20nm using ALD technique at a deposition temperature of 100 c using aminosilane and water vapor as precursor materials for a deposition time of 2.5h, as shown in fig. 4.
The deposition method in S500 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
The thickness of the second isolation layer material 4 in S500 should be greater than the thickness of the photoresist.
In a preferred embodiment, the 200nm second spacer material 4 alumina material is deposited by CVD technique to fill the patterned trenches at a deposition temperature of 100 c using trimethylaluminum and nitric oxide as precursor materials for a deposition time of 5min, as shown in fig. 5.
The planarization method in S600 is selected from one or more of the following: CMP techniques, PSG techniques, ion selective bombardment.
In a preferred embodiment, the surface planarization by the CMP technique is performed by polishing with a polisher in combination with an alumina polishing solution at a polishing rate of 10nm/min to leave a spacer layer having a height equal to the initial photoresist height, so that the surface is exposed to a pattern in which the photoresist, alumina, and silica are alternately arranged, as shown in fig. 6.
Removing the photoresist by using an organic solvent in S700; the organic solvent is selected from one or more of the following: acetone, isopropanol, trichloroethylene, and the like.
In a preferred embodiment, the wafer is cleaned with acetone and the photoresist is removed, preferably by sonication, as shown in FIG. 7.
The deposition method in S800 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
In a preferred embodiment, the third isolation layer, alumina material, was deposited by CVD technique at 380 c using trimethylaluminum and nitric oxide as precursor materials for 4min, as shown in fig. 8;
the planarization method in S900 is selected from one or more of the following: CMP techniques, PSG techniques, ion selective bombardment.
In a preferred embodiment, the surface is planarized by CMP and polished by a polisher in combination with an alumina polishing solution at a polishing rate of 10nm/min, so that the surface is exposed to a pattern of alumina, silica, and alumina arranged alternately, as shown in fig. 9.
The etching method in S1000 is selected from one or more of the following methods: RIE, ICP.
In a preferred embodiment, the exposed silicon oxide is etched away using RIE etching techniques: with CHF3And O2As etching gas, the power was set to 150w and the flow rates were CHF, respectively3:25sccm/O225sccm, carvingThe etching time was 2min, as shown in FIG. 10.
The deposition method in S1100 is selected from one or more of: electron beam evaporation technique, sputtering.
The metal in S1100 is selected from one or more of the following: gold, cobalt, aluminum, nickel, titanium, platinum, palladium and the like.
In a preferred embodiment, aluminum metal is deposited by electron beam evaporation at a rate of 1A/s, the trenches formed by etching are filled, and full surface coverage is achieved, as shown in fig. 11;
the planarization method in S1200 is selected from one or more of the following: CMP technique, PSG technique, ion selective bombardment, and large-area etching.
In a preferred embodiment, the surface is planarized using CMP techniques: and (4) polishing by using a polishing machine and combining with the metal aluminum polishing solution, wherein the polishing rate is 10nm/min, and removing the metal aluminum on the surface. Finally, a device structure with aluminum metal as a gate is obtained, as shown in fig. 12.
FIG. 2 corresponds to a schematic view of a photoresist film prepared on a silicon surface in the present example; FIG. 3 corresponds to a schematic diagram of the patterned structure on the photoresist in this example; FIG. 4 corresponds to a schematic view of a structure of a blanket pattern of grown silicon oxide in the present invention; FIG. 5 corresponds to a schematic view after depositing an alumina material full coverage trench in accordance with the present invention; FIG. 6 corresponds to a schematic representation of the present invention after surface planarization by CMP; FIG. 7 corresponds to a schematic after removal of the photoresist with acetone; FIG. 8 corresponds to a schematic view of growing alumina filled trenches in accordance with the present invention; FIG. 9 corresponds to a schematic representation after surface planarization by CMP; FIG. 10 corresponds to a schematic diagram of a wafer surface with an etching technique to remove the first isolation layer material between the second and third isolation layers; FIG. 11 corresponds to a schematic diagram after depositing aluminum metal using electron beam; fig. 12 corresponds to a schematic diagram of the present invention for removing aluminum metal on the surface by using CMP to planarize the surface.
Example 2
This example illustrates the method of fabricating a nanogate using thin film deposition techniques according to the invention.
The specific process is shown in fig. 1, and comprises the following steps:
s100: providing a wafer 1 required by process preparation;
s200: coating a uniform photoresist 2 film;
s300: preparing a strip-shaped graph structure on the photoresist 2;
s400: depositing first isolation layer materials 3A, 3B and 3C;
s500: depositing a second isolating layer material 4 to fill the groove;
s600: the material surface is planarized to remove the first isolation layer 3A.
S700: removing the photoresist;
s800: depositing a third isolation layer material 5 and filling the groove;
s900: flattening the surface of the material;
s1000: removing the first isolation layer 3B;
s1100: depositing a gate metal 6;
s1200: and flattening the surface of the material, and removing the metal on the surface.
In this embodiment, the material of the wafer 1 is a silicon substrate with a (001) crystal orientation.
In this embodiment, a photoresist film is prepared by a spin coater, and the thickness of the photoresist is 50 nm;
in this embodiment, a stripe photoresist structure with a pattern width of 7nm, a pattern pitch of 14nm, and a period of 20nm is prepared by combining with a corresponding photolithography technique, as shown in fig. 3.
In this embodiment, an ALD technique is used to deposit a 3nm first isolation layer material, i.e., a 3nm silicon oxide material, at a deposition temperature of 100 ℃, using aminosilane and water vapor as precursor materials, and depositing for 45min, as shown in fig. 4.
In this embodiment, an 80nm second isolation layer material 4 of alumina material is deposited by using a CVD technique to fill the patterned trench, the deposition temperature is 100 ℃, the precursor materials used are trimethylaluminum and nitric oxide, and the deposition time is 2min, as shown in fig. 5.
In this embodiment, surface planarization by CMP is performed by polishing with a polisher combined with an alumina polishing solution at a polishing rate of 10nm/min to leave a spacer layer with a height equal to that of the original photoresist, so that the photoresist, alumina, and silica are exposed on the surface of the substrate in an alternating pattern, as shown in fig. 6.
In this embodiment, the wafer is cleaned with acetone to remove the photoresist, which is preferably sonicated, as shown in FIG. 7.
In this embodiment, the fifth isolation layer, alumina material, was deposited by CVD technique at 380 deg.c, using trimethyl aluminum and nitric oxide as precursor materials, and the deposition time was 2min, as shown in fig. 8;
in this embodiment, the surface is planarized by CMP, and polished by a polisher in combination with an alumina polishing solution at a polishing rate of 10nm/min, so that the surface is exposed to a pattern of alumina, silica, and alumina arranged alternately, as shown in fig. 9.
In this example, the exposed silicon oxide was etched away using RIE etching: with CHF3And O2As etching gas, the power was set to 150w and the flow rates were CHF, respectively3:25sccm/O225sccm, as shown in FIG. 10.
In this embodiment, an electron beam evaporation technique is used to deposit aluminum metal at a rate of 1A/s, fill the trench generated by etching, and achieve full coverage of the surface layer, as shown in fig. 11;
in this embodiment, the surface is planarized using CMP techniques: and (4) polishing by using a polishing machine and combining with the metal aluminum polishing solution, wherein the polishing rate is 10nm/min, and removing the metal aluminum on the surface. Finally, a device structure with aluminum metal as a gate is obtained, as shown in fig. 12.
FIG. 2 corresponds to a schematic view of a photoresist film prepared on a silicon surface in the present example; FIG. 3 corresponds to a schematic diagram of the patterned structure on the photoresist in this example; FIG. 4 corresponds to a schematic view of a structure of a blanket pattern of grown silicon oxide in the present invention; FIG. 5 corresponds to a schematic view after depositing an alumina material full coverage trench in accordance with the present invention; FIG. 6 corresponds to a schematic representation of the present invention after surface planarization by CMP; FIG. 7 corresponds to a schematic after removal of the photoresist with acetone; FIG. 8 corresponds to a schematic view of growing alumina filled trenches in accordance with the present invention; FIG. 9 corresponds to a schematic representation after surface planarization by CMP; FIG. 10 corresponds to a schematic diagram of a wafer surface with an etching technique to remove the first isolation layer material between the second and third isolation layers; FIG. 11 corresponds to a schematic diagram after depositing aluminum metal using electron beam; fig. 12 corresponds to a schematic diagram of the present invention for removing aluminum metal on the surface by using CMP to planarize the surface.
Although the present invention has been described to a certain extent, it is apparent that appropriate changes in the respective conditions may be made without departing from the spirit and scope of the present invention. It is to be understood that the invention is not limited to the described embodiments, but is to be accorded the scope consistent with the claims, including equivalents of each element described.
Claims (10)
1. A method for preparing a nano-gate, the method comprising the steps of:
(1) providing a wafer required by process preparation;
(2) coating a photoresist material on the wafer;
(3) preparing the photoresist material in the step (2) into a formed structure by utilizing a photoetching technology;
(4) depositing a first isolation layer material to coat the graph structure;
(5) depositing a second isolation layer material, filling the groove and covering the surface;
(6) flattening the surface of the material obtained in the step (5) to obtain a flat surface and expose a composite structure of the photoresist material and the first and second isolation layers which are arranged alternately;
(7) removing the photoresist material to form a new pattern structure on the surface of the wafer;
(8) depositing a third isolation layer material, filling the groove of the new pattern structure and covering the surface;
(9) flattening the surface of the material obtained in the step (8) to enable the height of the pattern on the surface of the wafer after flattening to be the height of the composite structure prepared in the step (6), and forming a structure with the first, second and third isolating layers arranged alternately on the surface;
(10) etching to remove the first isolation layer material between the adjacent second isolation layer and the third isolation layer to the surface of the wafer;
(11) depositing a grid material, filling the grid groove and covering the surface;
(12) carrying out process treatment on the material obtained in the step (11), removing the grid electrode material on the surface to the surfaces of the second isolation layer and the third isolation layer, and obtaining a structure in which the third isolation layer, the nano-grid, the second isolation layer and the composite isolation layer formed by the first isolation layer are arranged alternately on the surface;
wherein the second isolation layer and the third isolation layer are made of the same material.
2. The method according to claim 1, wherein the photoresist material in step (2) is photoresist and/or photosensitive polyimide; and/or
The processing method in the step (12) is selected from CMP and/or etching technology;
preferably, the etching technique is selected from one or more of: argon ion etching, RIE technique, ICP technique.
3. The method according to claim 1 or 2, wherein the pattern structure in step (3) has a pitch between patterns not less than twice the thickness of the first spacer layer.
4. The method of any one of claims 1 to 3, wherein the wafer in step (1) is selected from one or more of: silicon, gallium arsenic, silicon carbide, gallium nitrogen and indium phosphorus;
more preferably, the wafer is a wafer with a functional layer.
5. The method according to any one of claims 1 to 4, wherein the material of the isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, alpha silicon;
preferably, the etching selection ratio of the materials of the first isolation layer and the second isolation layer is greater than 2: 1.
6. The method according to any one of claims 1 to 5, wherein the deposition method in steps (4), (5), (8) is a thin film deposition technique, preferably selected from one or more of the following: ALD, PECVD, ICP-CVD, LPCVD, reactive ion magnetron sputtering; and/or
The pattern preparation technique in step (3) is selected from one or more of the following: lithography, electron beam exposure, laser direct writing;
preferably, the lithographic technique is selected from one or more of: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.
7. The method according to any one of claims 1 to 6, wherein the planarization method in steps (6), (9) is selected from one or more of the following: CMP technique, PSG technique, ion selective bombardment; preferably a CMP technique; and/or
The method for depositing the gate material in the step (11) is a thin film preparation technology, and preferably, the thin film preparation technology is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering and electron beam evaporation;
the material of the nano gate is selected from one or more of the following materials: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polysilicon.
8. The method according to any one of claims 1 to 7, characterized in that it further comprises the steps of:
(13) processing the non-nano gate reserved area by adopting a conventional process to obtain a required mesa structure;
preferably, the conventional process is selected from one or more of the following: photoetching, wet etching and dry etching.
9. A nanogate fabricated according to the method of any one of claims 1 to 8, wherein the nanogate has a gate length of the thickness of the first isolation layer;
preferably, the line width of the nano gate is 100nm or less, preferably 28nm or less, more preferably 14nm or less, still more preferably 7nm or less, further preferably 5nm or less, most preferably 3nm or less, and 1nm or more.
10. A semiconductor device comprising the nanogate according to claim 9 and/or the nanogate produced by the production method according to any one of claims 1 to 8;
preferably, the semiconductor device is selected from one or more of: integrated circuit, CMOS, MESFET, MOSFET, NAND Flash, NOR Flash, DRAM.
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