CN113948043A

CN113948043A - Pixel driving circuit, driving method thereof, display panel and electronic equipment

Info

Publication number: CN113948043A
Application number: CN202010688078.2A
Authority: CN
Inventors: 迟世鹏; 安亚斌; 贺海明; 张帅
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-07-16
Filing date: 2020-07-16
Publication date: 2022-01-18
Anticipated expiration: 2040-07-16
Also published as: CN113948043B

Abstract

The embodiment of the application provides a pixel driving circuit, a driving method of the pixel driving circuit, a display panel and electronic equipment, relates to the technical field of display, and aims to improve the grid potential stability of a driving transistor and reduce the number of oxide transistors. The pixel driving circuit includes: a driving transistor having a gate, a first pole and a second pole connected to the first, second and third nodes; the initialization module writes a reset signal into a third node and the anode of the organic light-emitting diode, comprises a third switching transistor connected between the second switching transistor and a reset signal line and is a low-temperature polysilicon transistor; the data signal writing module writes a reset signal into a first node and writes a data signal into a driving transistor, and comprises a first switching transistor and a second switching transistor which are arranged in series and connected between the first node and a third node, wherein the first switching transistor is connected between the second switching transistor and the first node, the first switching transistor is a low-temperature polycrystalline silicon transistor, and the second switching transistor is an oxide transistor.

Description

Pixel driving circuit, driving method thereof, display panel and electronic equipment

Technical Field

The invention relates to the technical field of display, in particular to a pixel driving circuit, a driving method thereof, a display panel and electronic equipment.

Background

With the continuous development of display technology, an Active-matrix organic light emitting diode (AMOLED) display panel becomes a mainstream product in the current display industry, and is often applied to mobile phones, computers and wearable electronic products. The AMOLED display panel comprises a plurality of pixel driving circuits arranged in a matrix mode, wherein the pixel driving circuits are electrically connected with the organic light emitting diodes and used for providing driving current for the organic light emitting diodes to drive the organic light emitting diodes to emit light.

Fig. 1 is a schematic structural diagram of a pixel driving circuit in the prior art, and as shown in fig. 1, the pixel driving circuit includes a first transistor T1 'to a ninth transistor T9', and the first transistor T1 'to the ninth transistor T9' are all low temperature polysilicon transistors. Since the off-state leakage current of the low temperature polysilicon transistor is large, when the organic light emitting diode is driven to emit light, the charges of the gate of the second transistor T2 ', that is, the charges of the gate of the driving transistor, will be lost through the flow paths of the third transistor T3 ' and the fourth transistor T4 ' and the flow paths of the seventh transistor T7 ' and the eighth transistor T8 ', so that the gate potential of the driving transistor is unstable, and the driving current flowing into the organic light emitting diode D ' is affected, thereby causing the luminance of the organic light emitting diode D ' to deviate from the standard value. Particularly, in order to achieve the advantages of optimized dynamic image display and low power consumption, the pixel driving circuit is often driven by switching between low frequency and high frequency, and when the low frequency driving is performed, because the driving period of the pixel driving circuit is long, the off-state time of the third transistor T3 ', the fourth transistor T4', the seventh transistor T7 'and the eighth transistor T8' is also long, so that the off-state leakage current of the transistors has a more significant influence on the gate potential of the driving transistor, and further the implementation of the low frequency driving is limited, for example, the driving at a lower frequency, such as 1Hz, cannot be implemented.

To this end, fig. 2 is a schematic structural diagram of a pixel driving circuit in the prior art, as shown in fig. 2, in the prior art, a Hybrid thin film transistor (Hybrid TFT) technology is usually adopted, the third transistor T3 'and the fourth transistor T4' are replaced by one oxide transistor, such as the tenth transistor T10 'shown in fig. 2, and the seventh transistor T7' and the eighth transistor T8 'are replaced by one oxide transistor, such as the eleventh transistor T11' shown in fig. 2, since the off-state leakage current of the oxide transistor can be as low as 1fA, so that the influence of the leakage current on the gate potential of the driving transistor is improved. However, since the oxide transistor is large in size and the parasitic capacitance formed is also large, when the potential of the gate of the oxide transistor and the source or drain of the oxide transistor electrically connected to the driving transistor is changed, the gate potential of the driving transistor is fluctuated due to the influence of the parasitic capacitance, and the gate potential of the driving transistor is unstable.

Therefore, how to effectively improve the stability of the gate potential of the driving transistor becomes a technical problem to be solved for the moment.

Disclosure of Invention

In view of this, the present disclosure provides a pixel driving circuit, a driving method thereof, a display panel and an electronic device, which effectively improve the stability of the gate potential of the driving transistor to better implement low-frequency driving and reduce the number of oxide transistors required to be disposed in the pixel driving circuit.

In a first aspect, an embodiment of the present application provides a pixel driving circuit, including:

the grid electrode of the driving transistor is electrically connected with a first node, the first pole of the driving transistor is electrically connected with a second node, and the second pole of the driving transistor is electrically connected with a third node;

the initialization module is respectively electrically connected with the first scanning signal line, the third scanning signal line, the reset signal line, the third node and the anode of the organic light emitting diode and is used for writing a reset signal provided by the reset signal line into the third node and the anode;

the data signal writing module is respectively electrically connected with a second scanning signal line, a third scanning signal line, a data line, a second node, a third node and a first node, and is used for writing a reset signal written into the third node by the initialization module into the first node and writing a data signal provided by the data line into the driving transistor;

a light emission control module electrically connected to a light emission control signal line, a power signal line, the second node, the third node, and the anode of the organic light emitting diode, respectively, for supplying a driving current converted from the data signal and the power signal line to the anode of the organic light emitting diode;

the data signal writing module comprises a first switch transistor and a second switch transistor which are arranged in series, the first switch transistor and the second switch transistor are electrically connected between the first node and the third node, the first switch transistor is electrically connected between the second switch transistor and the first node, the grid electrode of the second switch transistor is electrically connected with the third scanning signal line, the first switch transistor is a low-temperature polysilicon transistor, and the second switch transistor is an oxide transistor;

the initialization module comprises a third switching transistor, the third switching transistor is electrically connected between the second switching transistor and the reset signal line, the grid electrode of the third switching transistor is electrically connected with the first scanning signal line, and the third switching transistor is a low-temperature polysilicon transistor.

In some embodiments, the first switching transistor is a P-type transistor, and a gate of the first switching transistor is electrically connected to a fourth scan signal line.

In some embodiments, the first switching transistor is an N-type transistor, and a gate of the first switching transistor is electrically connected to the third scan signal line.

In some embodiments, the first switch transistor comprises a first switch transistor and a first second switch transistor arranged in parallel, the first switch transistor and the first second switch transistor are respectively P-type transistors;

the grid electrode of the first switch transistor A is electrically connected with the first scanning signal line, and the grid electrode of the first switch transistor B is electrically connected with the second scanning signal line.

In some embodiments, the data signal writing module further includes a fourth switching transistor electrically connected between the data line and the second node, and a gate of the fourth switching transistor is electrically connected to the second scan signal line.

In some embodiments, the initialization module further includes a fifth switching transistor electrically connected between the reset signal line and the anode of the organic light emitting diode.

Further, the fifth switching transistor is a P-type transistor, and a gate of the fifth switching transistor is electrically connected to the second scanning signal line.

Further, the fifth switching transistor is an oxide transistor, and a gate of the fifth switching transistor is electrically connected to the third scanning signal line.

In some embodiments, the light emission control module includes a sixth switching transistor and a seventh switching transistor, wherein the sixth switching transistor is electrically connected between the power signal line and the second node, the seventh switching transistor is electrically connected between the third node and the anode of the organic light emitting diode, and gates of the sixth switching transistor and the seventh switching transistor are electrically connected to the light emission control signal line, respectively.

In some embodiments, the oxide transistor comprises an indium gallium zinc oxide transistor or an indium aluminum zinc oxide transistor.

Based on the same inventive concept, the embodiment of the present application further provides a driving method of a pixel driving circuit, for driving the pixel driving circuit;

the driving cycle of the pixel driving circuit includes a first period, a second period, and a third period, and the driving method includes:

in the first period, a third switching transistor in the initialization module responds to a first scanning signal provided by a first scanning signal line and writes a reset signal provided by a reset signal line into a third node, and a first switching transistor and a second switching transistor in the data signal writing module write the reset signal written into the third node by the initialization module into a first node and reset the first node;

in the second time interval, the initialization module writes the reset signal into the anode of the organic light emitting diode and resets the anode; the data signal writing module responds to a second scanning signal provided by a second scanning signal line and writes a data signal provided by a data line into the driving transistor;

in the third period, the light emission control module supplies the driving current converted by the data signal and the power signal line to the anode of the organic light emitting diode in response to the light emission control signal supplied from the light emission control signal line, and drives the organic light emitting diode to emit light.

In some embodiments, the first switching transistor is a P-type transistor, and a gate of the first switching transistor is electrically connected to a fourth scan signal line;

the process of writing the reset signal, which is written by the initialization module into the third node, into the first node by the first switching transistor and the second switching transistor during the first period includes: in the first period, the first switching transistor is turned on by a third scanning signal provided by the third scanning signal line, the second switching transistor is turned on by a fourth scanning signal provided by the fourth scanning signal line, and the reset signal written into the third node by the initialization module is written into the first node via the turned-on second switching transistor and the first switching transistor.

In some embodiments, the first switching transistor is an N-type transistor, and a gate of the first switching transistor is electrically connected to the third scanning signal line;

the process of writing the reset signal, which is written by the initialization module into the third node, into the first node by the first switching transistor and the second switching transistor during the first period includes: in the first period, the first switch transistor and the second switch transistor are turned on under the action of a third scan signal provided by the third scan signal line, and the reset signal written into the third node by the initialization module is written into the first node through the turned-on second switch transistor and the turned-on first switch transistor.

In some embodiments, the first switch transistor includes a first switch transistor and a first second switch transistor arranged in parallel, the first switch transistor and the first second switch transistor are P-type transistors respectively, a gate of the first switch transistor is electrically connected to the first scanning signal line, and a gate of the first second switch transistor is electrically connected to the second scanning signal line;

the process of writing the reset signal, which is written by the initialization module into the third node, into the first node by the first switching transistor and the second switching transistor during the first period includes: in the first period, the second switch transistor is turned on by a third scan signal provided by the third scan signal line, the first switch transistor is turned on by a first scan signal provided by the first scan signal line, and the reset signal written into the third node by the initialization module is written into the first node via the turned-on second switch transistor and the first switch transistor.

In some embodiments, the initialization module further includes a fifth switching transistor electrically connected between the reset signal line and the anode of the organic light emitting diode, the fifth switching transistor being an oxide transistor, a gate of the fifth switching transistor being electrically connected to a third scan signal line;

in the first period, the driving method further includes: the fifth switching transistor is conducted under the action of a third scanning signal provided by the third scanning signal line, and the reset signal is written into the anode of the organic light-emitting diode;

in the second period, the process of writing the reset signal into the anode of the organic light emitting diode by the initialization module includes: in the second period, the fifth switching transistor is turned on by a third scan signal supplied from the third scan signal line to write the reset signal into the anode of the organic light emitting diode.

Based on the same inventive concept, the embodiment of the present application further provides a display panel, which includes the pixel driving circuit.

Based on the same inventive concept, the embodiment of the application also provides an electronic device, which comprises the display panel.

The pixel driving circuit, the driving method thereof, the display panel and the electronic device have the following beneficial effects:

on one hand, on the premise of reducing the influence of leakage current on the potential of a first node by using a second switching transistor with lower off-state leakage current, by additionally arranging a first switching transistor between the second switching transistor and the first node and setting the first switching transistor as a low-temperature polysilicon transistor, when a third scanning signal received by the second switching transistor jumps in high and low levels and the potential of the third node changes in a second period of time, the potential fluctuation caused by the jump of the third scanning signal and the potential change of the third node is firstly fed back to a second pole of the first switching transistor and then fed back to the first node through the first switching transistor, because the size of the low-temperature polysilicon transistor is smaller, the generated parasitic capacitance is smaller, and therefore, under the influence of the smaller parasitic capacitance, the potential fluctuation of a second pole of the first switching transistor is further fed back to the first node, the potential fluctuation of the first node is attenuated so much that the fluctuation of the potential of the first node caused by the third scanning signal and the potential variation of the third node is reduced.

On the other hand, by arranging the first switch transistor and the second switch transistor in series between the third switch transistor and the first node, two current paths in the prior art are combined into one current path, and the second switch transistor is an oxide transistor with low leakage current, so that the leakage current of the current path is determined by the leakage current of the second switch transistor with the lowest leakage current, and then the third switch transistor does not need to be arranged as an oxide transistor, thereby reducing the number of oxide transistors required to be arranged in the pixel driving circuit.

To sum up, by adopting the technical scheme provided by the embodiment of the present application, while the second switching transistor is utilized to reduce the influence of the leakage current on the potential of the first node, the first switching transistor can also be utilized to weaken the third scan signal received by the second switching transistor and the influence of the potential change of the third node on the potential of the first node, thereby improving the stability of the potential of the first node to a greater extent, not only effectively improving the accuracy of the luminance of the organic light emitting diode, but also realizing the drive of lower frequency, thereby being better suitable for the drive mode of low-frequency and high-frequency switching, for example, being capable of realizing the drive within the range of 1Hz to 120 Hz. In addition, the arrangement positions of the first switch transistor and the second switch transistor are improved, and the number of oxide transistors required to be arranged in the pixel driving circuit is reduced, so that the space occupied by a single pixel driving circuit is reduced to a certain extent, the number of pixel driving circuits arranged in the display panel is correspondingly increased, and the resolution of the display panel is effectively improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.

FIG. 1 is a schematic diagram of a prior art pixel driving circuit;

FIG. 2 is a schematic diagram of a prior art pixel driving circuit;

FIG. 3 is a simulation diagram of the first node potential condition in the circuit structure shown in FIG. 2;

fig. 4 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram corresponding to the circuit configuration shown in FIG. 4;

FIG. 6 is a simulation diagram of the first node potential condition in the circuit structure shown in FIG. 4;

fig. 7 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 8 is a timing diagram corresponding to the circuit configuration shown in FIG. 7;

FIG. 9 is a simulation of the first node potential in the circuit configuration shown in FIG. 7;

fig. 10 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 11 is a simulation of the first node potential in the circuit configuration of FIG. 10;

fig. 12 is a schematic diagram of another structure of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 13 is another schematic structural diagram provided in accordance with an embodiment of the present application;

FIG. 14 is a schematic diagram of another structure of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 15 is a flowchart of a driving method provided in an embodiment of the present application;

fig. 16 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 17 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Before explaining the technical scheme of the present invention, the present invention first specifically explains the problems existing in the prior art based on fig. 2:

in the prior art, referring to fig. 2 again, after the transistors on the gate charge flow path of the driving transistor T2 'are replaced by oxide transistors, taking the tenth transistor T10' as an example, since the size of the oxide transistor is twice or more than that of the low temperature polysilicon transistor, a larger parasitic capacitor C1 'is formed between the film on which the tenth transistor T10' is located and the film on which the first node N1 'is located, and a larger parasitic capacitor C2' is formed between the film on which the tenth transistor T10 'is located and the film on which the third node N3' is located. When the data signal is charged, the scan signal provided by the scan signal line Sn 'electrically connected to the gate of the tenth transistor T10' will transition from high level to low level, and the transition of the scan signal will further cause the transition of the potential of the first node N1 ', under the influence of the parasitic capacitor C1'; in addition, when the light emitting period is entered, the potential of the third node N3 ' changes with the turn-off of the first transistor T1 ' and the turn-on of the fifth transistor T5 ', and is affected by the parasitic capacitors C1 ' and C2 ', and the potential change of the third node N3 ' also fluctuates the potential of the first node N1 ', so that a kick-back (kick-back) phenomenon occurs.

Therefore, the inventor performs simulation tests on the potential variation of the first node N1 ' in the prior art, fig. 3 is a simulation diagram of the potential variation of the first node in the circuit structure shown in fig. 2, fig. 3 illustrates a plurality of simulation curves, the plurality of simulation curves correspond to the potential variation of the first node N1 ' when different data signals are charged, as shown in fig. 3, after the data signals are charged, the potential of the first node N1 ' is obviously fluctuated in a falling manner under the influence of the high-low level jump of the scan signal, and when a light-emitting period is started, the potential of the first node N1 ' is obviously fluctuated in a rising manner, so that the potential of the first node N1 ' is unstable.

It can be seen that, based on the circuit structure adopted in the prior art, although the influence of the off-state leakage current on the potential of the first node N1 'is improved by using the oxide transistor, the jump of the scan signal and the potential change of the third node N3' still cause the instability of the potential of the first node N1 ', and further still affect the luminance of the light emitting diode D', so that the display effect is not uniform or flickers.

Based on this, an embodiment of the present application provides a pixel driving circuit, and fig. 4 is a schematic structural diagram of the pixel driving circuit provided in the embodiment of the present application, as shown in fig. 4, the pixel driving circuit includes a driving transistor DT, an initialization module 1, a data signal writing module 2, and a light emitting control module 3; the gate of the driving transistor DT is electrically connected to the first node N1, the first pole of the driving transistor DT is electrically connected to the second node N2, and the second pole of the driving transistor DT is electrically connected to the third node N3; the initialization module 1 is electrically connected to the first scan signal line Sp-1, the reset signal line Int, the third node N3, and the anode of the organic light emitting diode D, respectively, and is configured to write a reset signal provided by the reset signal line Int into the third node N3 and the anode; the Data signal writing module 2 is electrically connected to the second scan signal line Sp, the third scan signal line Sn, the Data line Data, the second node N2, the third node N3, and the first node N1, respectively, and is configured to write a reset signal, which is written to the third node N3 by the initialization module 1, into the first node N1 and write a Data signal, which is provided by the Data line Data, into the driving transistor DT; the light emission control module 3 is electrically connected to the light emission control signal line Emit, the power signal line ELVDD, the second node N2, the third node N3, and the anode of the organic light emitting diode D, respectively, and supplies a driving current converted from the power signal supplied via the data signal and the power signal line ELVDD to the anode of the organic light emitting diode D.

The data signal writing module 2 includes a first switching transistor T1 and a second switching transistor T2 connected in series, the first switching transistor T1 and the second switching transistor T2 are electrically connected between a first node N1 and a third node N3, and the first switching transistor T1 is electrically connected between a second switching transistor T2 and the first node N1, specifically, a gate of the second switching transistor T2 is electrically connected to a third scan signal line Sn, a first pole of the second switching transistor T2 is electrically connected to a third node N3, a second pole of the second switching transistor T2 is electrically connected to a first pole of the first switching transistor T1, a second pole of the first switching transistor T1 is electrically connected to the first node N1, the first switching transistor T1 is a low temperature polysilicon transistor, and the second switching transistor T2 is an oxide transistor.

The initialization module 1 includes a third switching transistor T3, the third switching transistor T3 is electrically connected between the second switching transistor T2 and the reset signal line Int, and specifically, the gate of the third switching transistor T3 is electrically connected to the first scan signal line Sp-1, the first pole of the third switching transistor T3 is electrically connected to the reset signal line Int, the second pole of the third switching transistor T3 is electrically connected to a third node N3, and the third switching transistor T3 is a low temperature polysilicon transistor.

The first and second poles of the transistor respectively represent a source and a drain of the transistor, and the second pole is a drain when the first pole is the source, or a source when the first pole is the drain. In addition, the oxide transistors in the embodiments of the present application are all N-type transistors.

Specifically, fig. 5 is a timing diagram corresponding to the circuit structure shown in fig. 4, and in conjunction with fig. 4 and 5, the driving cycle of the pixel driving circuit includes a first period t1, a second period t2, and a third period t 3:

in the first period T1, the first scan signal supplied from the first scan signal line Sp-1 is at a low level, the second scan signal supplied from the second scan signal line Sp is at a high level, the third scan signal supplied from the third scan signal line Sn is at a high level, the emission control signal supplied from the emission control signal line Emit is at a high level (for the sake of understanding, the first scan signal is represented by Sp-1, the second scan signal is represented by Sp, the emission control signal is represented by Emit, and the Data signal is represented by Data in fig. 5), the third switching transistor T3 in the initialization module 1 is turned on by the high level supplied from the first scan signal line Sp-1, the reset signal supplied from the reset signal line Int is written into the third node N3, and at the same time, the first switching transistor T1 in the Data signal writing module 2 is turned on, and the second switching transistor T2 is turned on by the high level supplied from the third scan signal line Sn, the reset signal of the third node N3 is written into the first node N1 via the turned-on second and first switching transistors T2 and T1, and resets the first node N1.

In the second period t2, the first scan signal provided by the first scan signal line Sp-1 is at a high level, the second scan signal provided by the second scan signal line Sp is at a low level, the third scan signal provided by the third scan signal line Sn is at a high level, the emission control signal provided by the emission control signal line Emit is at a high level, the initialization module 1 writes the reset signal into the anode of the organic light emitting diode D to reset the anode, and at the same time, the Data signal writing module 2 writes the Data signal provided by the Data line Data into the driving transistor DT in response to the low level provided by the second scan signal line Sp and the high level provided by the third scan signal, and at this time, V is V_N3＝V_Data-|Vth|。

In the third period t3, the first scan signal provided from the first scan signal line Sp-1 is at a high level, the second scan signal provided from the second scan signal line Sp is at a high level, the third scan signal provided from the third scan signal line Sn is at a low level, the emission control signal provided from the emission control signal line Emit is at a low level, and the emission control module 3 supplies the driving current converted by the data signal and the power signal provided from the power signal line ELVDD to the anode of the organic light emitting diode D in response to the low level provided from the emission control signal line Emit to drive the organic light emitting diode D to Emit light, and at this time, V is set to be high_N3＝V_ELVEE+V_OLEDWhich isIn, V_ELVEEThe voltage, V, of the negative supply signal received for the cathode of the organic light-emitting diode D_OLEDIs the voltage difference across the organic light emitting diode D.

It should be noted that, in the process of actually sending a signal, there may be a certain delay in the transmission of the signal, and the fact that the light emission control signal shown in fig. 5 jumps to the low level to enter the third time period t3 after the second time period t2 is ended and the high level is maintained for a certain period of time is to ensure that when the light emission control signal jumps low, both the second scan signal and the third scan signal have jumped to be ended, thereby avoiding the influence of the signal delay of the second scan signal and the third scan signal on the normal light emission of the organic light emitting diode D.

In combination with the above driving principle, in the pixel driving circuit provided in the embodiment of the invention, on the one hand, on the premise of reducing the influence of the leakage current on the potential of the first node N1 by using the second switching transistor T2 with lower off-state leakage current, by additionally providing the first switching transistor T1 between the second switching transistor T2 and the first node N1 and setting the first switching transistor T1 as a low-temperature polysilicon transistor, when the second period T2 enters the third period T3, when the third scanning signal received by the second switching transistor T2 makes a transition of high and low levels and the potential of the third node N3 changes, the potential fluctuation caused by the two signals is firstly fed back to the second pole of the first switching transistor T1 and then fed back to the first node N1 through the first switching transistor T1, and because the size of the low-temperature polysilicon transistor is smaller, the generated parasitic capacitance is also smaller, therefore, when the potential fluctuation of the second pole of the first switching transistor T1 is further fed back to the first node under the influence of the smaller parasitic capacitance, the potential fluctuation of the first node N1 is attenuated so much that the fluctuation of the potential of the third scanning signal and the third node N3 caused to the potential of the first node N1 is attenuated.

On the other hand, referring to the circuit structure in the prior art shown in fig. 1 again, in the third time period T3, the charge of the first node N1 'is lost through the two circulation paths where the seventh transistor T7', the eighth transistor T8 ', the third transistor T3' and the fourth transistor T4 'are located, and therefore, in order to improve the influence of the leakage current on the potential of the first node N1', it is necessary to replace the transistors on the two circulation paths with oxide transistors, for example, referring to the circuit structure in the prior art shown in fig. 2 again, the pixel driving circuit needs to at least provide two oxide transistors, namely, a tenth transistor T10 'and an eleventh transistor T11', but since the size of the oxide transistors is larger, the layout space occupation is also larger, and therefore, the space occupation of the pixel driving circuit is increased. In the embodiment of the present application, by disposing the first switching transistor T1 and the second switching transistor T2 in series between the third switching transistor T3 and the first node N1, two current paths in the prior art are combined into one current path, and since the second switching transistor T2 is an oxide transistor with low leakage current, the leakage current of the current path is determined by the leakage current of the second switching transistor T2 with the lowest leakage current, and then the third switching transistor T3 does not need to be disposed as an oxide transistor, thereby reducing the number of oxide transistors required to be disposed in the pixel driving circuit.

To sum up, with the pixel driving circuit provided in the embodiment of the present application, while the second switching transistor T2 is used to reduce the influence of the leakage current on the potential of the first node N1, the first switching transistor T1 can also be used to weaken the third scan signal received by the second switching transistor T2 and the influence of the potential change of the third node N3 on the potential of the first node N1, so as to greatly improve the stability of the potential of the first node N1, which not only effectively improves the accuracy of the luminance of the organic light emitting diode D, but also can realize the driving of lower frequencies, for example, the lower frequencies can be reduced to 1Hz, so that the driving method better applicable to the switching between low frequencies and high frequencies, for example, the switching between low frequencies and high frequencies can be realized within the range of 1Hz to 120 Hz. In addition, by improving the arrangement positions of the first switching transistor T1 and the second switching transistor T2, the number of oxide transistors required to be arranged in the pixel driving circuit is also reduced, so that the space required to be occupied by a single pixel driving circuit is reduced to a certain extent, the number of pixel driving circuits arranged in the display panel is correspondingly increased, and the resolution of the display panel is effectively improved.

In one embodiment, referring to fig. 4 and 5 again, the first switching transistor T1 is a P-type transistor, the gate of the first switching transistor T1 is electrically connected to the fourth scan signal line Spn, and the levels of the scan signals provided by the fourth scan signal line Spn and the third scan signal line Sn at the same time are opposite. At this time, the turn-on states of the first and second switching transistors T1 and T2 are the same in the same period, thereby ensuring that the reset signal of the third node N3 can be written into the first node N1 via the turned-on second and first switching transistors T2 and T1 in the first period T1, and the data signal can be written into the driving transistor DT via the turned-on second and first switching transistors T2 and T1 in the second period T2, to ensure the normal operation of the circuit.

Further, the inventor conducted simulation test on the potential variation of the first node N1 in the circuit structure shown in fig. 4, fig. 6 is a simulation diagram of the potential variation of the first node in the circuit structure shown in fig. 4, and it can be seen by comparing with fig. 3 corresponding to the prior art that V is used for charging with the same data signal_DataFor example, in the prior art, under the influence of the high-low level jump of the scanning signal, the potential of the first node is decreased from 0.969V to 0.307V, fluctuates by 0.662V, and under the influence of the potential change of the third node, the potential of the first node is subsequently increased from 0.307V to 0.478V, and fluctuates by 0.171V; in the embodiment of the present invention, under the influence of the high-low level jump of the third scan signal, the potential of the first node N1 decreases from 0.829V to 0.785V, fluctuates by 0.044V, and under the influence of the potential change of the third node N3, the potential of the first node N1 subsequently increases from 0.785V to 0.873V, and fluctuates by 0.088V. It can be seen that, with the circuit structure provided in the embodiment of the present application, the level of the potential fluctuation of the first node N1 caused by the high-low level jump of the third scan signal and the level of the potential fluctuation of the first node N1 caused by the potential change of the third node N3 are both significantly reduced, so that the stabilized potential of the first node N1 is closer to the potential before the drop, and the potential of the first node N1 is effectively increasedAnd (4) stability.

In an embodiment, fig. 7 is another structural schematic diagram of the pixel driving circuit provided in the embodiment of the present application, and as shown in fig. 7, the first switching transistor T1 is an N-type transistor, and a gate of the first switching transistor T1 is electrically connected to the third scan signal line Sn. Fig. 8 is a timing diagram corresponding to the circuit configuration shown in fig. 7, and as shown in fig. 8, in the first period T1 and the second period T2, the first switching transistor T1 and the second switching transistor T2 are both turned on by the high level provided by the third scan signal line Sn, so that in the first period T1, the reset signal of the third node N3 can be written into the first node N1 via the turned-on second switching transistor T2 and the turned-on first switching transistor T1, and in the second period T2, the data signal can be written into the driving transistor DT via the turned-on second switching transistor T2 and the turned-on first switching transistor T1, so as to ensure the normal operation of the circuit.

Based on this kind of circuit structure, first switch transistor T1 only need with second switch transistor T2 through the same third scanning signal line Sn only need drive can, need not to set up extra scanning signal line to first switch transistor T1 again, reduced the line quantity of walking among the pixel drive circuit to the space that pixel drive circuit occupy has further been reduced.

Further, the inventor conducted simulation test on the potential variation of the first node N1 in the circuit structure shown in fig. 7, fig. 9 is a simulation diagram of the potential variation of the first node in the circuit structure shown in fig. 7, and it can be seen by comparing with fig. 3 corresponding to the prior art that V is used for charging with the same data signal_DataFor example, in the prior art, under the influence of the high-low level jump of the scanning signal, the potential of the first node is decreased from 0.969V to 0.307V, fluctuates by 0.662V, and under the influence of the potential change of the third node, the potential of the first node is subsequently increased from 0.307V to 0.478V, and fluctuates by 0.171V; in the embodiment of the present invention, the voltage level of the first node N1 is decreased from 0.826V to 0.378V and fluctuates by 0.448V under the influence of the high-low level jump of the third scan signal, and the voltage level of the first node N1 is subsequently increased from 0.378V under the influence of the change of the voltage level of the third node N3To 0.497V, fluctuating by 0.119V. It can be seen that, with the circuit structure provided in the embodiment of the present application, the level of the potential fluctuation of the first node N1 caused by the high-low level jump of the third scan signal and the level of the potential fluctuation of the first node N1 caused by the potential change of the third node N3 are both significantly reduced, so that the potential of the first node N1 after being stabilized is closer to the potential before the drop, and the potential stability of the first node N1 is effectively improved.

In an embodiment, fig. 10 is a schematic structural diagram of a pixel driving circuit provided in the embodiment of the present application, and as shown in fig. 10, the first switching transistor T1 includes a first a switching transistor T11 and a first b switching transistor T12 that are arranged in parallel, and the first a switching transistor T11 and the first b switching transistor T12 are P-type transistors respectively; specifically, the gate of the first switching transistor T11 is electrically connected to the first scan signal line Sp-1, the gate of the first second switching transistor T12 is electrically connected to the second scan signal line Sp, the first poles of the first switching transistor T11 and the first second switching transistor T12 are electrically connected to the second pole of the second switching transistor T2, and the second poles of the first switching transistor T11 and the first second switching transistor T12 are electrically connected to the first node N1. Referring to fig. 8 again, since the first scan signal line Sp-1 and the second scan signal line Sp respectively provide a low level during the first period T1 and the second period T2, one of the first a switch transistor T11 and the first b switch transistor T12 can be turned on by the low level during the first period T1 and the second period T2; specifically, in the first period T1, the first switching transistor T11 is turned on by the low level provided by the first scan signal line Sp-1, so that the reset signal of the third node N3 can be written into the first node N1 via the turned-on second switching transistor T2 and first switching transistor T1, and in the second period T2, the first second switching transistor T12 is turned on by the low level provided by the second scan signal line Sp, so that the data signal can be written into the driving transistor DT via the turned-on second switching transistor T2 and first second switching transistor T12, to ensure the normal operation of the circuit.

At this time, the first switch transistor T11 and the first second switch transistor T12 only need to be connected with the original first scanning signal line Sp-1 and the original second scanning signal line Sp in the pixel driving circuit, so that the normal operation of the circuit can be ensured, no additional scanning signal line needs to be arranged for the first switch transistor T11 and the first second switch transistor T12, the number of wiring in the pixel driving circuit is reduced, and the space occupied by the pixel driving circuit is further reduced.

Further, the inventor conducted simulation test on the potential variation of the first node N1 in the circuit configuration shown in fig. 10, fig. 11 is a simulation diagram of the potential variation of the first node in the circuit configuration shown in fig. 10, and it can be seen by comparing with fig. 3 corresponding to the prior art that V is used for charging with the same data signal_DataFor example, in the prior art, under the influence of the high-low level jump of the scanning signal, the potential of the first node is decreased from 0.969V to 0.307V, fluctuates by 0.662V, and under the influence of the potential change of the third node, the potential of the first node is subsequently increased from 0.307V to 0.478V, and fluctuates by 0.171V; in the embodiment of the present invention, under the influence of the high-low level jump of the third scan signal, the potential of the first node N1 is decreased from 0.846V to 0.824V and fluctuates by 0.022V, and under the influence of the potential change of the third node N3, the potential of the first node N1 is subsequently increased from 0.824V to 0.906V and fluctuates by 0.082V. It can be seen that, with the circuit structure provided in the embodiment of the present application, the level of the potential fluctuation of the first node N1 caused by the high-low level jump of the third scan signal and the level of the potential fluctuation of the first node N1 caused by the potential change of the third node N3 are both significantly reduced, so that the potential of the first node N1 after being stabilized is closer to the potential before the drop, and the potential stability of the first node N1 is effectively improved.

In addition, the first scan signal, the second scan signal, the third scan signal and the fourth scan signal may be output by a same Gate driver On Array (GOA) circuit or a plurality of Gate driver circuits, for example, the first scan signal and the second scan signal are output by a same Gate driver circuit, and the third scan signal is output by another Gate driver circuit, or the first scan signal, the second scan signal and the third scan signal are output by a same Gate driver circuit, taking the timing sequence shown in fig. 8 as an example.

In one embodiment, referring to fig. 4, 7 and 10 again, the Data signal writing module 2 further includes a fourth switching transistor T4, the fourth switching transistor T4 is electrically connected between the Data line Data and the second node N2, specifically, the gate of the fourth switching transistor T4 is electrically connected to the second scan signal line Sp, the first electrode of the fourth switching transistor T4 is electrically connected to the Data line Data, the second electrode of the fourth switching transistor T4 is electrically connected to the second node N2, and the fourth switching transistor T4 may be a P-type low temperature polysilicon transistor. In conjunction with the timing shown in fig. 5 and 8, during the second period T2, the fourth switching transistor T4 is turned on by the low level supplied from the second scan signal line Sp, the first switching transistor T1 and the second switching transistor T2 are also turned on, and the Data signal supplied from the Data line Data is written into the first node N1, that is, the gate of the driving transistor DT, via the turned-on fourth switching transistor T4, the second switching transistor T2, and the third switching transistor T3, and captures the threshold voltage of the driving transistor DT.

In one embodiment, referring to fig. 4, 7 and 10 again, the initialization module 1 further includes a fifth switching transistor T5, the fifth switching transistor T5 is electrically connected between the reset signal line Int and the anode of the organic light emitting diode D, specifically, a first pole of the fifth switching transistor T5 is electrically connected to the reset signal line Int, and a second pole of the fifth switching transistor T5 is electrically connected to the anode of the organic light emitting diode D. The fifth switching transistor T5 is used to write a reset signal supplied from the reset signal line Int into the anode of the organic light emitting diode D to reset the anode of the organic light emitting diode D.

Further, referring to fig. 4, 7 and 10 again, the fifth switching transistor T5 is a P-type transistor, the gate of the fifth switching transistor T5 is electrically connected to the second scan signal line Sp, and the fifth switching transistor T5 may be a low temperature polysilicon transistor. In conjunction with the timing shown in fig. 5 and 8, during the second period T2, the fifth switching transistor T5 is turned on by the low level provided by the second scan signal line Sp, and the reset signal is transmitted to the anode of the organic light emitting diode D via the turned-on fifth switching transistor T5, thereby resetting the anode of the organic light emitting diode D.

Alternatively, fig. 12 is another schematic structural diagram of the pixel driving circuit provided in the embodiment of the present application, fig. 13 is another schematic structural diagram of the pixel driving circuit provided in the embodiment of the present application, and fig. 14 is another schematic structural diagram of the pixel driving circuit provided in the embodiment of the present application, as shown in fig. 12 to fig. 14, the fifth switching transistor T5 may also be an oxide transistor, in this case, the fifth switching transistor T5 is an N-type transistor, and the gate of the fifth switching transistor T5 is electrically connected to the third scan signal line Sn. In conjunction with the timing shown in fig. 5 and 8, the fifth switching transistor T5 is turned on by the high level provided by the third scan signal line Sn during the first period T1 and the second period T2, so that the anode of the organic light emitting diode D is reset during the first period T1 and the second period T2, and the reset time of the anode is increased, so that the anode is reset more fully. In addition, since the fifth switching transistor T5 is an oxide transistor, the off-state leakage current of the fifth switching transistor T5 is low, and when the fifth switching transistor T5 is turned off by the low level supplied from the third scan signal line Sn during the third period T3, the influence of the leakage current on the potential of the anode of the organic light emitting diode D can be reduced, and the reliability of light emission of the organic light emitting diode D can be further improved.

In one embodiment, referring again to fig. 4, 7 and 10, the light emitting control module 3 includes a sixth switching transistor T6 and a seventh switching transistor T7, wherein the sixth switching transistor T6 is electrically connected between the power signal line ELVDD and the second node N2, the seventh switching transistor T7 is electrically connected between the third node N3 and the anode of the organic light emitting diode D, and particularly, the gates of the sixth switching transistor T6 and the seventh switching transistor T7 are electrically connected to the emission control signal line Emit, respectively, the first pole of the sixth switching transistor T6 is electrically connected to the power signal line ELVDD, the second pole of the sixth switching transistor T6 is electrically connected to the second node N2, the first pole of the seventh switching transistor T7 is electrically connected to the third node N3, the second pole of the seventh switching transistor T7 is electrically connected to the anode of the organic light emitting diode D, and the sixth switching transistor T6 and the seventh switching transistor T7 may be P-type low temperature polysilicon transistors. In conjunction with the timing shown in fig. 5 and 8, in the third period T3, the sixth switching transistor T6 and the seventh switching transistor T7 are turned on by the low level supplied from the emission control signal line Emit, and the driving current converted by the data signal and the power signal is supplied to the anode of the organic light emitting diode D, driving the organic light emitting diode D to Emit light.

In addition, referring to fig. 4, 7 and 10 again, the pixel driving circuit may further include a storage capacitor C, a first plate of the storage capacitor C is electrically connected to the power signal line ELVDD, and a second plate of the storage capacitor C is electrically connected to the first node N1 for further stabilizing the potential of the first node N1.

Specifically, to increase the flexibility of the selection range of the oxide transistor, the oxide transistor used in the embodiment of the present invention includes an indium gallium zinc oxide transistor or an indium aluminum zinc oxide transistor, or other types of oxide transistors.

The driving principle of the pixel driving circuit provided by the embodiment of the present application is further described below with reference to fig. 4 and 5 based on the transistor structure of the pixel driving circuit:

in the first period t1, the first scan signal is at a low level, the second scan signal is at a high level, the third scan signal is at a high level, the fourth scan signal is at a low level, and the emission control signal is at a high level; the third switching transistor T3 is turned on by the first scan signal, the first switching transistor T1 is turned on by the fourth scan signal, the second switching transistor T2 is turned on by the third scan signal, and the reset signal provided by the reset signal line Int is transmitted to the third node N3 through the turned-on third switching transistor T3, and further transmitted to the first node N1 through the turned-on second switching transistor T2 and the turned-on first switching transistor T1, thereby resetting the first node N1.

In the second period t2, the first scan signal is at a high level, the second scan signal is at a low level, the third scan signal is at a high level, the fourth scan signal is at a low level, and the light emission control signal is at a high level; the fifth switching transistor T5 is turned on by the second scan signal, and the reset signal is transmitted to the anode of the organic light emitting diode D via the turned-on fifth switching transistor T5 to reset the anode; the fourth switching transistor T4 is turned on by the second scan signal, the first switching transistor T1 is turned on by the fourth scan signal, the second switching transistor T2 is turned on by the third scan signal, and the Data signal provided by the Data line Data is written to the gate of the driving transistor DT through the turned-on fourth switching transistor T4, the driving transistor DT, the second switching transistor T2, and the first switching transistor T1, and captures the threshold voltage of the driving transistor DT.

In the third period t3, the first scan signal is at a high level, the second scan signal is at a high level, the third scan signal is at a low level, the fourth scan signal is at a high level, and the light emission control signal is at a low level; the sixth switching transistor T6 and the seventh switching transistor T7 are turned on by the light emitting control signal, and the driving current converted by the data signal and the power signal supplied through the power signal line ELVDD flows into the anode of the organic light emitting diode D, driving the organic light emitting diode D to emit light.

Based on the same inventive concept, the present application further provides a driving method of a pixel driving circuit, for driving the pixel driving circuit, please refer to fig. 4 and fig. 5 again, a driving cycle of the pixel driving circuit includes a first time period t1, a second time period t2, and a third time period t3, fig. 15 is a flowchart of the driving method provided by the present application, and as shown in fig. 15, the driving method includes:

in the first period T1, the third switching transistor T3 in the initialization block 1 writes the reset signal supplied from the reset signal line Int to the third node N3 in response to the first scan signal supplied from the first scan signal line Sp-1, and the first switching transistor T1 and the second switching transistor T2 in the data signal writing block 2 write the reset signal written from the initialization block 1 to the third node N3 to the first node N1, resetting the first node N1.

In a second time period t2, the initialization module 1 writes a reset signal into the anode of the organic light emitting diode D to reset the anode; the Data signal writing module 2 writes the Data signal supplied from the Data line Data into the driving transistor DT in response to the second scan signal supplied from the second scan signal line Sp.

In the third period t3, the light emission control module 3 supplies the driving current converted by the power signal supplied via the data signal and the power signal line ELVDD to the anode of the organic light emitting diode D in response to the light emission control signal supplied from the light emission control signal line Emit, and drives the organic light emitting diode D to Emit light.

In combination with the analysis of the above embodiment, with the driving method, on the one hand, on the premise that the second switching transistor T2 with lower off-state leakage current is used to reduce the influence of the leakage current on the potential of the first node N1, by additionally providing the first switching transistor T1 between the second switching transistor T2 and the first node N1 and setting the first switching transistor T1 as a low-temperature polysilicon transistor, the fluctuation caused by the third scanning signal and the potential change of the third node N3 to the potential of the first node N1 can be weakened, so that the stability of the potential of the first node N1 is improved to a greater extent, and not only is the accuracy of the light emission luminance of the organic light emitting diode D effectively improved, but also the driving at a lower frequency can be realized. On the other hand, by disposing the first switching transistor T1 and the second switching transistor T2 in series between the third switching transistor T3 and the first node N1, the number of oxide transistors required to be disposed in the pixel driving circuit is reduced, thereby reducing the space required to be occupied by a single pixel driving circuit to some extent, and accordingly increasing the number of pixel driving circuits disposed in the display panel, which effectively improves the resolution of the display panel.

In one embodiment, referring to fig. 4 and 5 again, the first switching transistor T1 is a P-type transistor, the gate of the first switching transistor T1 is electrically connected to the fourth scan signal line Spn, and the levels of the scan signals provided by the fourth scan signal line Spn and the third scan signal line Sn at the same time are opposite. Based on this, in the first period T1, the process of the first and second switching transistors T1 and T2 writing the reset signal for initializing the module 1 to be written to the third node N3 to the first node N1 includes: in the first period T1, the first switching transistor T1 is turned on by the third scan signal provided by the third scan signal line Sn, the second switching transistor T2 is turned on by the fourth scan signal provided by the fourth scan signal line Spn, and the reset signal written to the third node N3 by the initialization module 1 is written to the first node N1 via the turned-on second switching transistor T2 and the first switching transistor T1. By driving in this way, the conduction states of the first switching transistor T1 and the second switching transistor T2 in the same time period can be guaranteed to be the same, so that the normal reset of the first node N1 is guaranteed, and the normal operation of the circuit is guaranteed.

In one embodiment, referring to fig. 7 and 8 again, the first switching transistor T1 is an N-type transistor, and the gate of the first switching transistor T1 is electrically connected to the third scan signal line Sn. Based on this, in the first period T1, the process of the first and second switching transistors T1 and T2 writing the reset signal for initializing the module 1 to be written to the third node N3 to the first node N1 includes: in the first period T1, the first and second switching transistors T1 and T2 are turned on by the third scan signal provided by the third scan signal line Sn, and the reset signal written to the third node N3 by the initialization module 1 is written to the first node N1 via the turned-on second and first switching transistors T2 and T1. By adopting the driving mode, the first switch transistor T1 and the second switch transistor T2 only need to be driven by the same third scanning signal line Sn, and no extra scanning signal line needs to be arranged for the first switch transistor T1, so that the wiring quantity in the pixel driving circuit is reduced, and the space occupied by the pixel driving circuit is further reduced.

In one embodiment, referring to fig. 10 and 8 again, the first switch transistor T1 includes a first switch transistor T11 and a first second switch transistor T12 that are arranged in parallel, the first switch transistor T11 and the first second switch transistor T12 are P-type transistors respectively, a gate of the first switch transistor T11 is electrically connected to the first scan signal line Sp-1, and a gate of the first second switch transistor T12 is electrically connected to the second scan signal line Sp. Based on this, since the first scan signal line Sp-1 and the second scan signal line Sp provide the low level in the first period T1 and the second period T2, respectively, in the first period T1 and the second period T2, one of the first switch transistor T11 and the first switch transistor T12 can be turned on by the low level, and specifically, in the first period T1, the process of writing the reset signal of the initialization module 1 written in the third node N3 into the first node N1 by the first switch transistor T1 and the second switch transistor T2 includes: in the first period T1, the second switching transistor T2 is turned on by the third scan signal provided by the third scan signal line Sn, the first switching transistor T11 is turned on by the first scan signal provided by the first scan signal line Sp-1, and the reset signal written to the third node N3 by the initialization module 1 is written to the first node N1 via the turned-on second switching transistor T2 and the first switching transistor T11. By adopting the driving mode, the first switch transistor T11 and the first switch transistor T12 only need to receive the scanning signals provided by the original first scanning signal line Sp-1 and the original second scanning signal line Sp in the pixel driving circuit, so that the normal work of the circuit can be ensured, no extra scanning signal line needs to be arranged for the first switch transistor T11 and the first switch transistor T12, the number of wiring in the pixel driving circuit is reduced, and the space occupied by the pixel driving circuit is further reduced.

In one embodiment, referring to fig. 4, fig. 7 and fig. 10 again in combination with the timing sequence shown in fig. 5 and fig. 8, the initialization module 1 further includes a fifth switching transistor T5, the fifth switching transistor T5 is electrically connected between the reset signal line Int and the anode of the organic light emitting diode D, the fifth switching transistor T5 is an oxide transistor, and the gate of the fifth switching transistor T5 is electrically connected to the third scan signal line Sn. Based on this, in the first period t1, the driving method further includes: the fifth switching transistor T5 is turned on by the third scan signal supplied from the third scan signal line Sn to write the reset signal into the anode of the organic light emitting diode D; also, in the second period t2, the process of the initialization module 1 writing the reset signal to the anode of the organic light emitting diode D includes: in the second period T2, the fifth switching transistor T5 is turned on by the third scan signal supplied from the third scan signal line Sn to write the reset signal into the anode of the organic light emitting diode D.

With this driving method, the fifth switching transistor T5 is turned on by the high level provided by the third scan signal line Sn during the first period T1 and the second period T2, so that the anode of the organic light emitting diode D is reset during the first period T1 and the second period T2, thereby increasing the reset time of the anode and making the reset more sufficient. In addition, since the fifth switching transistor T5 is an oxide transistor, the off-state leakage current of the fifth switching transistor T5 is low, and when the fifth switching transistor T5 is turned off by the low level supplied from the third scan signal line Sn during the third period T3, the influence of the leakage current on the potential of the anode of the organic light emitting diode D can be reduced, and the reliability of light emission of the organic light emitting diode D can be further improved.

In addition, it should be noted that the driving manners of other switching transistors in the pixel driving circuit, such as the sixth switching transistor T6 and the seventh switching transistor T7, have been described in detail in the embodiments corresponding to the pixel driving circuit, and are not described herein again.

Based on the same inventive concept, an embodiment of the present application further provides a display panel, fig. 16 is a schematic structural diagram of the display panel provided in the embodiment of the present application, and as shown in fig. 16, the display panel includes the pixel driving circuit 100, and the display panel may specifically be an Active-matrix organic light emitting diode (AMOLED) display panel, where specific structures and driving methods of the pixel driving circuit 100 have been described in detail in the embodiments, and are not repeated herein.

Based on the same inventive concept, an embodiment of the present application further provides an electronic device, and fig. 17 is a schematic structural diagram of a display panel provided in the embodiment of the present application, and as shown in fig. 17, the electronic device includes the display panel 200. Of course, the electronic device shown in fig. 17 is only a schematic illustration, and the electronic device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper book, or a television.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pixel driving circuit, comprising:

2. The pixel driving circuit according to claim 1,

the first switch transistor is a P-type transistor, and a grid electrode of the first switch transistor is electrically connected with the fourth scanning signal line.

3. The pixel driving circuit according to claim 1,

the first switch transistor is an N-type transistor, and the grid electrode of the first switch transistor is electrically connected with the third scanning signal line.

4. The pixel driving circuit according to claim 1,

the first switch transistor comprises a first switch transistor A and a first switch transistor B which are arranged in parallel, and the first switch transistor A and the first switch transistor B are respectively P-type transistors;

5. The pixel driving circuit according to claim 1,

the data signal writing module further includes a fourth switching transistor electrically connected between the data line and the second node, and a gate of the fourth switching transistor is electrically connected to the second scanning signal line.

6. The pixel driving circuit according to claim 1,

the initialization module further includes a fifth switching transistor electrically connected between the reset signal line and the anode of the organic light emitting diode.

7. The pixel driving circuit according to claim 6,

the fifth switching transistor is a P-type transistor, and a gate of the fifth switching transistor is electrically connected to the second scanning signal line.

8. The pixel driving circuit according to claim 6,

the fifth switching transistor is an oxide transistor, and a gate of the fifth switching transistor is electrically connected to the third scanning signal line.

9. The pixel driving circuit according to claim 1,

the light emission control module includes a sixth switching transistor electrically connected between the power signal line and the second node, and a seventh switching transistor electrically connected between the third node and the anode of the organic light emitting diode, and gates of the sixth switching transistor and the seventh switching transistor are electrically connected to the light emission control signal line, respectively.

10. The pixel driving circuit according to claim 1,

the oxide transistor includes an indium gallium zinc oxide transistor or an indium aluminum zinc oxide transistor.

11. A driving method of a pixel driving circuit for driving the pixel driving circuit according to claim 1;

12. The driving method according to claim 11,

the first switch transistor is a P-type transistor, and the grid electrode of the first switch transistor is electrically connected with the fourth scanning signal line;

13. The driving method according to claim 11,

the first switch transistor is an N-type transistor, and the grid electrode of the first switch transistor is electrically connected with the third scanning signal line;

14. The driving method according to claim 11,

the first switch transistor comprises a first switch transistor A and a first switch transistor B which are arranged in parallel, the first switch transistor A and the first switch transistor B are respectively P-type transistors, the grid electrode of the first switch transistor A is electrically connected with the first scanning signal line, and the grid electrode of the first switch transistor B is electrically connected with the second scanning signal line;

15. The driving method according to claim 11,

the initialization module further comprises a fifth switching transistor, the fifth switching transistor is electrically connected between the reset signal line and the anode of the organic light emitting diode, the fifth switching transistor is an oxide transistor, and the gate of the fifth switching transistor is electrically connected with a third scanning signal line;

16. A display panel comprising the pixel driving circuit according to any one of claims 1 to 10.

17. An electronic device characterized by comprising the display panel according to claim 16.