CN113946539A - DSP processor and processing method of loop jump instruction thereof - Google Patents
DSP processor and processing method of loop jump instruction thereof Download PDFInfo
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Abstract
The invention discloses a DSP processor and a processing method of a loop jump instruction thereof, wherein the method comprises the following steps: reading the loop jump instruction assembler at an instruction fetching stage of a pipeline cycle, wherein the loop jump instruction assembler comprises a register address for storing a loop jump instruction variable, a loop jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage, a decoding stage and an execution stage; decoding the read loop jump instruction to obtain decoded loop jump instruction information; and judging whether the jump is needed according to the value of the variable in the register and a loop jump threshold value, if the jump is needed, jumping to the jump target address, otherwise, performing loop processing on the value of the variable according to a loop processing mode in the loop jump instruction. The method improves the processing efficiency of the DSP processor.
Description
Technical Field
The invention relates to the technical field of instruction processing, in particular to a DSP processor and a processing method of a loop jump instruction thereof.
Background
In the prior art, 3 pipeline cycles are generally required to execute a loop jump instruction, taking a for loop of C language as an example, if an (i ═ 0; i ═ 0x 1F; i + +) loop is to be implemented, an assembler generally needs to write three instructions to implement, for example:
among the three instructions, the first instruction I1 is used to determine whether the value of the variable in the register R31 is equal to 0x1F and store the comparison result in the status register, the second instruction I2 performs the increment of the R31 register, and the third instruction I3 determines whether to perform branch jump according to the flag status register. It can be seen that in the prior art, 3 pipeline cycles are required to execute a for instruction. In order to implement the for instruction, a programmer needs to write 3 instructions, which occupy instruction space and reduce the functions that can be implemented by the processor under the condition of limited instruction space. In addition, since 3 pipeline cycles are required, the processing speed of the processor becomes slow, resulting in low processor efficiency.
Disclosure of Invention
The present invention provides a DSP processor and a loop jump instruction processing method thereof, so as to solve the problem of low processor efficiency caused by three pipeline cycles required for executing a loop jump instruction in the prior art.
In order to solve the above technical problem, an aspect of the present invention provides a method for processing a loop jump instruction of a DSP processor, including:
reading the loop jump instruction assembler at an instruction fetching stage of a pipeline cycle, wherein the loop jump instruction assembler comprises a register address for storing a loop jump instruction variable, a loop jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage, a decoding stage and an execution stage;
in the decoding stage, decoding the read loop jump instruction to obtain decoded loop jump instruction information;
in the execution stage, executing jump operation according to the decoded loop jump instruction information or executing corresponding operation on the current value of the variable according to the variable processing tag, if the corresponding operation is executed on the current value of the variable according to the variable tag, comparing the operated variable value with the jump threshold value, and judging whether the jump condition is met.
In a specific embodiment, the decoding the read loop jump instruction to obtain decoded loop jump instruction information specifically includes:
decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold, the jump target address and the variable processing tag;
the current value of the variable in the register is read.
In a specific embodiment, the executing a jump operation according to the decoded loop jump instruction information or executing a corresponding operation on the current value of the variable according to the variable processing tag, and if the corresponding operation is executed on the current value of the variable according to the variable processing tag, comparing the operated variable value with the jump threshold, and determining whether a jump condition is satisfied specifically includes:
comparing the current value of the variable with the jump threshold value, judging whether the jump condition is met, if the jump condition is met, jumping the instruction execution address to the jump target address, otherwise, determining the operation corresponding to the variable processing tag, if the operation is an adding operation, adding one to the current value of the variable, comparing the value after adding one with the jump threshold value, judging whether the jump condition is met, if the operation is a subtracting operation, subtracting one from the current value of the variable, comparing the value after subtracting one with the jump threshold value, and judging whether the jump condition is met.
In a specific embodiment, the method further comprises:
the instructions read in the instruction fetching stage of the pipeline cycle which is continuously set for one pipeline cycle behind the pipeline cycle are all NOP instructions.
A second aspect of the present invention provides a method for processing a loop jump instruction of a DSP processor, the method comprising:
reading the loop jump instruction assembler at an instruction fetching stage of a pipeline cycle, decoding the read loop jump instruction assembler to obtain decoded loop jump instruction information, reading a current value of the variable from the special register, and comparing the current value with the jump threshold, wherein the loop jump instruction assembler comprises a special register address for storing the loop jump instruction variable, a loop jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage and a decoding stage;
in the decoding stage, whether a jump condition is met or not is judged, if the jump condition is met, an instruction execution address is jumped to the jump target address, otherwise, the operation corresponding to the variable processing tag is determined, if the operation is an add-one operation, the current value of the variable is added with one, the value after the addition is compared with the jump threshold value, whether the jump condition is met or not is judged, if the operation is a subtract-one operation, the current value of the variable is reduced with one, the value after the reduction is compared with the jump threshold value, and whether the jump condition is met or not is judged.
A third aspect of the present invention provides a DSP processor comprising:
the instruction fetching unit is used for reading the loop jump instruction information at an instruction fetching stage of a pipeline cycle, wherein the loop jump instruction information specifically comprises a register address used for storing the loop jump instruction variable, a loop jump threshold value and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage, a decoding stage and an execution stage;
a decoding unit, configured to decode the read loop jump instruction in a decoding stage, to obtain decoded loop jump instruction information;
the execution unit is used for executing jump operation according to the decoded loop jump instruction information or executing corresponding operation on the current value of the variable according to the variable processing tag, if the corresponding operation is executed on the current value of the variable according to the variable tag, comparing the operated variable value with the jump threshold value, and judging whether the jump condition is met;
and the register is used for storing the variable of the loop jump instruction.
In a specific embodiment, the decoding unit is specifically configured to:
decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold, the jump target address and the variable processing tag;
the current value of the variable in the register is read.
In a specific embodiment, the execution unit is specifically configured to:
comparing the current value of the variable with the jump threshold value, judging whether the jump condition is met, if the jump condition is met, jumping the instruction execution address to the jump target address, otherwise, determining the operation corresponding to the variable processing tag, if the operation is an adding operation, adding one to the current value of the variable, comparing the value after adding one with the jump threshold value, judging whether the jump condition is met, if the operation is a subtracting operation, subtracting one from the current value of the variable, comparing the value after subtracting one with the jump threshold value, and judging whether the jump condition is met.
In one embodiment, the instruction fetch unit is further configured to fetch all NOP instructions in an instruction fetch stage of the pipeline cycle that is set consecutively after the pipeline cycle.
In a specific embodiment, the register is a special purpose register.
The embodiment of the invention has the following beneficial effects: the method comprises the steps of reading a register address, a loop jump threshold value and a jump target address of a loop jump instruction, wherein the register address is used for storing a loop jump instruction variable, and the jump target address are read at an instruction fetching stage of a pipeline cycle, then decoding the read loop jump instruction and executing the loop jump instruction. By adopting the method, a programmer can realize loop jump only by writing one instruction, the requirement on an instruction storage space is reduced, and the DSP processor can realize more functions in the limited instruction storage space.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
FIG. 1 is a flowchart illustrating a method for processing a loop jump instruction of a DSP processor according to a first embodiment of the present invention;
FIG. 2 is a flow chart of a method for processing a loop jump instruction in a DSP processor according to a first embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for processing a loop jump instruction of a DSP processor according to a first embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for processing a loop jump instruction of a DSP processor according to a second embodiment of the present invention;
FIG. 5 is a diagram illustrating a method for processing a loop jump instruction in a DSP processor according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of a DSP processor according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, an embodiment of the present invention provides a method for processing a loop jump instruction of a DSP processor, including the following steps:
s11, reading the loop jump instruction assembler at the instruction fetching stage of a pipeline cycle, wherein the loop jump instruction assembler comprises a register address for storing the loop jump instruction variable, a loop jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises the instruction fetching stage, a decoding stage and an execution stage.
The pipeline cycle at least comprises an instruction fetching stage, a decoding stage and an execution stage, and also comprises a write-back stage, wherein the execution stage comprises a first execution stage and a second execution stage. As shown in fig. 2, a schematic diagram of a four-stage pipeline cycle is shown.
Wherein, the assembler of the loop jump instruction is as follows: FOR Rx, # immed, TAG, DEAL. Wherein, Rx is a register for storing a variable i, # immed is a jump threshold, TAG is a jump target address, DEAL is a variable processing TAG, which indicates an operation performed on the variable, for example, if DEAL is 1, it indicates that an add 1 operation, i + +, is performed on the variable i, and if DEAL is 0, it indicates that a subtract 1 operation, i- -, is performed on the variable i. The assembler of the loop jump instruction is described with reference to the for (i ═ x; i < ═ y; i + +) program in the C language program. Rx in the assembler FOR instruction represents "i" in the C program; initial value of Rx, representing "x"; immediate "# immed" indicates "y".
S12, in the decoding stage, decoding the read loop jump instruction to obtain the decoded loop jump instruction information.
And decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold, the jump target address and the variable processing tag, and reading the current value of the variable in the register.
And S13, in the execution stage, executing jump operation according to the decoded loop jump instruction information or executing corresponding operation on the current value of the variable according to the variable processing label, and if executing corresponding operation on the current value of the variable according to the variable label, comparing the operated variable value with the jump threshold value, and judging whether the jump condition is met.
Comparing the current value of the variable with a jump threshold, jumping to a corresponding target jump address if the jump condition is met, otherwise, determining the operation corresponding to the variable processing tag, if the corresponding operation is i + +, adding one to the current value of the variable, comparing the value obtained by adding one to the current value of the variable with the jump threshold, judging whether the jump condition is met, jumping to the corresponding target jump address if the jump condition is met, otherwise, continuing adding one, if the corresponding operation is i- - -, subtracting one from the value of the variable, comparing the value obtained by subtracting one from the current value of the variable with the jump threshold, judging whether the jump condition is met, if the jump condition is met, jumping to the corresponding target jump address, otherwise, continuing subtracting one.
The method for processing the loop jump instruction according to the embodiment of the present invention reads a register address, a loop jump threshold, a variable processing tag, and a jump target address of the loop jump instruction, where the register address is used for storing a variable of the loop jump instruction, at an instruction fetch stage of a pipeline cycle, and then decodes the read loop jump instruction and executes the loop jump instruction. By adopting the method, a programmer can realize loop jump only by writing one instruction, the requirement on an instruction storage space is reduced, and the DSP processor can realize more functions in the limited instruction storage space.
The method further comprises the following steps: the instructions read in the instruction fetching stage of the pipeline cycle which is continuously set for one pipeline cycle behind the pipeline cycle are all NOP instructions.
TABLE 1 instruction execution Process
As shown in Table 1, including four loop jump instructions I1, I2, I3 and I4 executed in sequence, wherein I1 is the loop jump instruction, there are three delay slots (i.e. instructions I2, I3 and I4 are loaded on the pipeline) when the pipeline cycle of the FOR loop jump instruction is executed to execute 2 (i.e. when a branch jump is taken). In order to reduce the workload of an assembler or a C compiler, a continuous setting bar instruction following the loop jump instruction I1 is set as a NOP instruction. Preferably, the I2, I3, and I4 instructions following the loop jump instruction are set to null instructions.
A second embodiment of the present invention provides a method for processing a loop jump instruction of a DSP processor, as shown in fig. 4-5, the method includes:
s21, reading the loop jump instruction assembler at the instruction fetching stage of a pipeline cycle, decoding the read loop jump instruction assembler to obtain decoded loop jump instruction information, reading the current value of the variable from the special register, and comparing the current value with the jump threshold, wherein the loop jump instruction assembler comprises a special register address for storing the loop jump instruction variable, a loop jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage and a decoding stage.
Preferably, 4 special registers are used for storing variables in the loop jump instruction, and the 4 special registers are all connected in a hard-wired mode, so that the time sequence problem caused by a multi-stage selector when a general register is read is avoided.
S22, comparing the current value of the variable with the jump threshold value, judging whether the jump condition is satisfied, if the jump condition is satisfied, jumping the instruction execution address to the jump target address, otherwise, determining the operation corresponding to the variable processing tag, if the operation is an add operation, adding one to the current value of the variable, comparing the added value with the jump threshold value, judging whether the jump condition is satisfied, if the operation is a subtract operation, subtracting one from the current value of the variable, comparing the subtracted value with the jump threshold value, and judging whether the jump condition is satisfied.
In the method for processing the loop jump instruction, the special register is adopted to store the loop jump instruction, a programmer only needs to write one instruction to realize loop jump, the requirement on an instruction storage space is reduced, and then a DSP (digital signal processor) can realize more functions in the limited instruction storage space.
Based on the first embodiment of the present invention, the third embodiment of the present invention provides a DSP processor, as shown in fig. 6, where the DSP processor 10 includes an instruction fetching unit 1, a decoding unit 2, and an execution unit 3, where the instruction fetching unit 1 is configured to read the loop jump instruction assembler at an instruction fetching stage of a pipeline cycle, where the loop jump instruction assembler includes a register address for storing the loop jump instruction variable, a loop jump threshold, a variable processing tag, and a jump target address, and the pipeline cycle at least includes an instruction fetching stage, a decoding stage, and an execution stage; the decoding unit 2 is configured to decode the read loop jump instruction, and obtain decoded loop jump instruction information; the execution unit 3 is configured to execute a jump operation according to the decoded loop jump instruction information or execute a corresponding operation on the current value of the variable according to the variable processing tag, and compare the value of the operated variable with the jump threshold to determine whether a jump condition is satisfied.
The decoding unit 2 is specifically configured to decode the read loop jump instruction, obtain decoded loop jump instruction information, and read a current value of the variable in the register.
The execution unit 3 is specifically configured to compare the current value of the variable with the jump threshold, determine whether a jump condition is satisfied, if the jump condition is satisfied, jump the instruction execution address to the jump target address, otherwise, execute a corresponding operation on the current value of the variable according to the variable processing tag, compare the operated variable value with the jump threshold, and determine whether the jump condition is satisfied.
The instruction fetching unit is also used for reading instructions in instruction fetching stages which are continuously set for pipeline cycles after the pipeline cycles, wherein all the instructions are NOP instructions.
Wherein the register is a special purpose register.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (10)
1. A processing method of a loop jump instruction of a DSP processor is characterized in that: the method comprises the following steps:
reading the loop jump instruction assembler at an instruction fetching stage of a pipeline cycle, wherein the loop jump instruction assembler comprises a register address for storing a loop jump instruction variable, a loop jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage, a decoding stage and an execution stage;
in the decoding stage, decoding the read loop jump instruction to obtain decoded loop jump instruction information;
in the execution stage, executing jump operation according to the decoded loop jump instruction information or executing corresponding operation on the current value of the variable according to the variable processing tag, if the corresponding operation is executed on the current value of the variable according to the variable tag, comparing the operated variable value with the jump threshold value, and judging whether the jump condition is met.
2. The method according to claim 1, wherein the decoding the read loop jump instruction to obtain decoded loop jump instruction information specifically comprises:
decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold, the jump target address and the variable processing tag;
the current value of the variable in the register is read.
3. The method according to claim 2, wherein the executing a jump operation according to the decoded loop jump instruction information or executing a corresponding operation on the current value of the variable according to the variable processing tag, and if the executing a corresponding operation on the current value of the variable according to the variable processing tag compares the operated variable value with the jump threshold, determining whether the jump condition is satisfied specifically includes:
comparing the current value of the variable with the jump threshold value, judging whether the jump condition is met, if the jump condition is met, jumping the instruction execution address to the jump target address, otherwise, determining the operation corresponding to the variable processing tag, if the operation is an adding operation, adding one to the current value of the variable, comparing the value after adding one with the jump threshold value, judging whether the jump condition is met, if the operation is a subtracting operation, subtracting one from the current value of the variable, comparing the value after subtracting one with the jump threshold value, and judging whether the jump condition is met.
4. The method of claim 3, further comprising:
the instructions read in the instruction fetching stage of the pipeline cycle which is continuously set for one pipeline cycle behind the pipeline cycle are all NOP instructions.
5. A method of processing a loop jump instruction for a DSP processor, the method comprising:
reading the loop jump instruction assembler at an instruction fetching stage of a pipeline cycle, decoding the read loop jump instruction assembler to obtain decoded loop jump instruction information, reading a current value of the variable from the special register, and comparing the current value with the jump threshold, wherein the loop jump instruction assembler comprises a special register address for storing the loop jump instruction variable, a loop jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage and a decoding stage;
in the decoding stage, whether a jump condition is met or not is judged, if the jump condition is met, an instruction execution address is jumped to the jump target address, otherwise, the operation corresponding to the variable processing tag is determined, if the operation is an add-one operation, the current value of the variable is added with one, the value after the addition is compared with the jump threshold value, whether the jump condition is met or not is judged, if the operation is a subtract-one operation, the current value of the variable is reduced with one, the value after the reduction is compared with the jump threshold value, and whether the jump condition is met or not is judged.
6. A DSP processor, comprising:
the instruction fetching unit is used for reading the loop jump instruction information at an instruction fetching stage of a pipeline cycle, wherein the loop jump instruction information specifically comprises a register address used for storing the loop jump instruction variable, a loop jump threshold value and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage, a decoding stage and an execution stage;
a decoding unit, configured to decode the read loop jump instruction in a decoding stage, to obtain decoded loop jump instruction information;
the execution unit is used for executing jump operation according to the decoded loop jump instruction information or executing corresponding operation on the current value of the variable according to the variable processing tag, if the corresponding operation is executed on the current value of the variable according to the variable tag, comparing the operated variable value with the jump threshold value, and judging whether the jump condition is met;
and the register is used for storing the variable of the loop jump instruction.
7. The DSP processor defined in claim 6 wherein the decode unit is to:
decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold, the jump target address and the variable processing tag;
the current value of the variable in the register is read.
8. The DSP processor defined in claim 7 wherein the execution unit is to:
comparing the current value of the variable with the jump threshold value, judging whether the jump condition is met, if the jump condition is met, jumping the instruction execution address to the jump target address, otherwise, determining the operation corresponding to the variable processing tag, if the operation is an adding operation, adding one to the current value of the variable, comparing the value after adding one with the jump threshold value, judging whether the jump condition is met, if the operation is a subtracting operation, subtracting one from the current value of the variable, comparing the value after subtracting one with the jump threshold value, and judging whether the jump condition is met.
9. The DSP processor defined in claim 8 wherein:
the instruction fetching unit is also used for reading instructions in instruction fetching stages which are continuously set for pipeline cycles after the pipeline cycles, wherein all the instructions are NOP instructions.
10. The DSP processor defined in claim 9 wherein:
the register is a special register.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6330664B1 (en) * | 1996-05-03 | 2001-12-11 | Telefonaktiebolaget Lm Ericsson (Publ) | Method relating to handling of conditional jumps in a multi-stage pipeline arrangement |
| CN1532693A (en) * | 2003-03-24 | 2004-09-29 | ���µ�����ҵ��ʽ���� | Processor and compiler |
| CN102298352A (en) * | 2010-06-25 | 2011-12-28 | 中国科学院沈阳自动化研究所 | Specific processor system structure for high-performance programmable controller and implementation method of dedicated processor system structure |
| CN103218206A (en) * | 2012-01-18 | 2013-07-24 | 上海算芯微电子有限公司 | Instruction branch pre-jump method and system |
| CN112000370A (en) * | 2020-08-27 | 2020-11-27 | 北京百度网讯科技有限公司 | Processing method, device and equipment of loop instruction and storage medium |
-
2021
- 2021-10-09 CN CN202111176313.9A patent/CN113946539B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6330664B1 (en) * | 1996-05-03 | 2001-12-11 | Telefonaktiebolaget Lm Ericsson (Publ) | Method relating to handling of conditional jumps in a multi-stage pipeline arrangement |
| CN1532693A (en) * | 2003-03-24 | 2004-09-29 | ���µ�����ҵ��ʽ���� | Processor and compiler |
| CN102298352A (en) * | 2010-06-25 | 2011-12-28 | 中国科学院沈阳自动化研究所 | Specific processor system structure for high-performance programmable controller and implementation method of dedicated processor system structure |
| CN103218206A (en) * | 2012-01-18 | 2013-07-24 | 上海算芯微电子有限公司 | Instruction branch pre-jump method and system |
| CN112000370A (en) * | 2020-08-27 | 2020-11-27 | 北京百度网讯科技有限公司 | Processing method, device and equipment of loop instruction and storage medium |
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