CN113921521A

CN113921521A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN113921521A
Application number: CN202010729805.5A
Authority: CN
Inventors: 黄圣惠; 张三荣; 张立鹏
Original assignee: Powerchip Technology Corp
Current assignee: Powerchip Technology Corp
Priority date: 2020-07-09
Filing date: 2020-07-27
Publication date: 2022-01-11
Also published as: TW202203430A; TWI725891B

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device has a cell region and a peripheral region, and includes a substrate, a chip on bit line (COB) type Dynamic Random Access Memory (DRAM), and a multi-time programmable (MTP) memory. The COB DRAM is disposed in the cell region and includes a bit line and a first capacitor. The MTP is arranged in the peripheral area and comprises a floating grid formed on the substrate, a second capacitor positioned on the floating grid and at least one contact window electrically connected with the floating grid and the second capacitor. The floating gate is a structure patterned simultaneously with the bit line, and the second capacitor is a capacitor structure fabricated simultaneously with the first capacitor.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

Memories are semiconductor devices for storing information and data, are widely used in personal computers, mobile phones, networks, and the like, and have become important electronic products essential to life. As the functions of computer microprocessors become stronger, programs and operations performed by software increase, and the storage capacity of various data increases, the demand for the capacity of the memory also increases.

In a conventional multi-time programmable (MTP) memory cell structure, a floating gate and a control gate are made of doped polysilicon for erase/write operations. Recently, to avoid the problem of data misjudgment caused by over-erase/write, a selection transistor (select transistor) is connected in series to one side of the memory cell to form two transistor structures, and the programming and reading of the memory cell are controlled by the selection transistor.

However, since the devices in the cell region and the peripheral region are required to be fabricated on the chip at the same time, and the fabrication processes of the memory cells and the peripheral devices are usually performed separately, multiple photomasks and complicated fabrication process steps are required, resulting in increased cost and time.

Disclosure of Invention

The present invention provides a semiconductor device having a multi-time programmable Memory (MTP) fabricated simultaneously with a Capacitor Over Bit (COB) type Dynamic Random Access Memory (DRAM), which can reduce the fabrication process cost and time.

The invention also provides a manufacturing method of the semiconductor device, which can integrate the floating gate, the inter-gate dielectric layer and the control gate of the MTP into the manufacturing process of the COB DRAM.

The semiconductor device of the invention has a cell region and a peripheral region, and comprises a substrate, a capacitor on bit line (COB) type Dynamic Random Access Memory (DRAM) and a multi-time programmable Memory (MTP). The COB DRAM is disposed in the cell region and includes a bit line and a first capacitor. The MTP is arranged in the peripheral area and comprises a floating grid formed on the substrate, a second capacitor positioned on the floating grid and at least one contact window electrically connected with the floating grid and the second capacitor. The floating gate is a structure patterned simultaneously with the bit line, and the second capacitor is a capacitor structure fabricated simultaneously with the first capacitor.

In an embodiment of the invention, the MTP may further include a tunneling oxide layer located between the substrate and the floating gate.

In an embodiment of the invention, a material of the floating gate includes doped polysilicon or a polycide.

In an embodiment of the invention, the MTP may further include a metal film formed on the surface of the floating gate and directly contacting the contact window.

In an embodiment of the invention, the metal film and the bit line are simultaneously deposited structural layers.

In an embodiment of the invention, the first capacitor includes a first lower electrode, a first dielectric layer and a first upper electrode, and the second capacitor includes a second lower electrode, a second dielectric layer and a second upper electrode, wherein the second lower electrode is an electrode structure fabricated simultaneously with the first lower electrode, and the second upper electrode is an electrode structure fabricated simultaneously with the first upper electrode.

In an embodiment of the invention, the semiconductor device may further include a zero-level metal layer interposed between the second bottom electrode and the contact window and directly contacting the contact window.

In an embodiment of the invention, the first capacitor and the second capacitor have a groove structure, and the first upper electrode and the second upper electrode respectively include an upper electrode layer located above the groove and a conductive material filled in the groove and located below the upper electrode layer.

In an embodiment of the invention, the conductive material includes polysilicon or a polycide, and the conductive material in the second capacitor is used as a control gate of the MTP.

In an embodiment of the invention, the number of the grooves in the second capacitor is plural, and the parallel capacitors can be formed.

In an embodiment of the present invention, the second dielectric layer and the first dielectric layer are made of high-k dielectric material.

In an embodiment of the invention, a thickness of the second dielectric layer may be greater than a thickness of the first dielectric layer.

In an embodiment of the invention, the number of the second capacitors is plural, and the capacitors can be connected in series.

The method of manufacturing a semiconductor device of the present invention includes forming a capacitor on bit line (COB) type Dynamic Random Access Memory (DRAM) element including a bit line in a cell region. And forming a floating gate in the peripheral area, wherein the floating gate is a structure which is patterned simultaneously with the bit lines. At least one contact window is formed on the floating grid, and then a first capacitor and a second capacitor are simultaneously manufactured, wherein the first capacitor is formed on the DRAM element, and the second capacitor is formed on the contact window. The second capacitor is electrically connected to the floating gate through the contact window, so that the floating gate, the contact window and the second capacitor form a multi-time programmable Memory (MTP).

In another embodiment of the present invention, a tunnel oxide layer may be formed on the substrate in the peripheral region before the floating gate is formed.

In another embodiment of the present invention, a metal film may be formed on the surface of the floating gate after the floating gate is formed.

In another embodiment of the present invention, the method for simultaneously forming the first and second capacitors includes simultaneously forming a first lower electrode of the first capacitor and a second lower electrode of the second capacitor, forming a first dielectric layer on the first lower electrode and a second dielectric layer on the second lower electrode, and then simultaneously forming a first upper electrode of the first capacitor on the first dielectric layer and a second upper electrode of the second capacitor on the second dielectric layer.

In another embodiment of the present invention, before the first and second capacitors are simultaneously formed, a recess structure may be formed on the DRAM device and the floating gate, respectively.

In another embodiment of the present invention, the method of forming the first and second upper electrodes includes filling a conductive material into the recess structure, and forming an upper electrode layer on the conductive material, wherein the conductive material in the second capacitor is used as a control gate of the MTP.

In another embodiment of the present invention, the number of the groove structures formed on the floating gate is, for example, plural.

In another embodiment of the present invention, the first dielectric layer and the second dielectric layer are formed simultaneously.

In another embodiment of the present invention, the first dielectric layer and the second dielectric layer are separately formed, and the thickness of the second dielectric layer is greater than that of the first dielectric layer.

In another embodiment of the present invention, a zero-level metal layer may be formed on the contact before the first and second capacitors are simultaneously formed.

In another embodiment of the present invention, the number of the second capacitors is plural and the second capacitors are connected in series.

Based on the above, the floating gate, the inter-gate dielectric layer and the control gate of the multi-time programmable memory can be integrated into the manufacturing process of the capacitor-type dynamic random access memory on the bit line through the special manufacturing process, so that the possibility of manufacturing process integration is increased, and the manufacturing process time and cost can be further reduced.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

FIGS. 2A to 2J are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention;

fig. 3 is a schematic cross-sectional view of an MTP in a semiconductor device according to a third embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of an MTP in a semiconductor device according to a fourth embodiment of the present invention.

Description of the symbols

10. 20: substrate

100a COB DRAM

100b:MTP

102. 520 first capacitor

104. 504a first lower electrode

106. 506a first dielectric layer

108. 512 first upper electrode

110. 152 groove

112. 510, 510a upper electrode layer

114. 508, 508a conductor material

116. 220 floating gate

118. 300, 522 second capacitor

120. 148, 226, 228 contact window

122. 216, 504 conductor layer

124. 218a, 218b metal film

126. 504b second bottom electrode

128. 506b second dielectric layer

130. 514 second upper electrode

132. 234 DRAM element

134. 218c bit line

136. 206 buried word line

138. 156, 204, 222 doped region

140. 212 bit line contact

142. 230 storage node contact window

144. 208, 232 insulating layer

146a, 146b, 146c, 146d, 210, 224, 500 interlayer dielectric layer

150 active region isolation structure

154. 214 tunnel oxide layer

200a peripheral area

200b cell region

502 groove structure

M0 layer zero metal layer

M1 first Metal layer

t1, t2 thickness

Detailed Description

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention, wherein a Capacitor Over Bit (COB) type Dynamic Random Access Memory (DRAM) is formed in a cell (cell) region on the left side of fig. 1, and a multi-time programmable Memory (MTP) is formed in a peripheral (peripheral) region on the right side of fig. 1.

Referring to fig. 1, the semiconductor device of the first embodiment has a cell region and a peripheral region, and includes a substrate 10, a COB type DRAM 100a, and an MTP 100 b.

In fig. 1, the COB type DRAM 100a is disposed in a cell region and includes a first capacitor 102, wherein the first capacitor 102 includes a first lower electrode 104, a first dielectric layer 106 and a first upper electrode 108, and the first lower electrode 104 is, for example, Ti/TiN, and the first dielectric layer 106 is, for example, a high dielectric constant (high-k) material. Since the first capacitor 102 may have a recess 110, the first upper electrode 108 may further include an upper electrode layer 112 located above the recess 110 and a conductive material 114 filled in the recess 110 and located below the upper electrode layer 112, wherein the upper electrode layer 112 is, for example, a tungsten layer, and the conductive material 114 is, for example, polysilicon or a polycide. The MTP 100b is disposed in the peripheral region and includes a Floating Gate (FG)116 formed on the substrate 10, a second capacitor 118 located on the floating gate 116, and at least one contact window 120 electrically connecting the floating gate 116 and the second capacitor 118. The floating gate 116 may include a conductive layer 122 (material such as doped polysilicon or polycide) and a metal film 124 (material such as tungsten) thereover, while the contact 120 is a tungsten plug.

With continued reference to fig. 1, the second capacitor 118 of the MTP 100b is a capacitor structure fabricated simultaneously with the first capacitor 102, wherein the second capacitor 118 includes a second lower electrode 126, a second dielectric layer 128 and a second upper electrode 130, the second lower electrode 126 is an electrode structure fabricated simultaneously with the first lower electrode 104, the second upper electrode 130 is an electrode structure fabricated simultaneously with the first upper electrode 108, and the second dielectric layer 128 can also be fabricated simultaneously with the first dielectric layer 106. Thus, the second bottom electrode 126 may be Ti/TiN as well as the first bottom electrode 104, and the second dielectric layer 128 may be a high-k material as well as the first dielectric layer 106. In one embodiment, since the MTP 100b may be able to withstand a large voltage, the second dielectric layer 128 may also be fabricated separately from the first dielectric layer 106, such that the thickness t2 of the second dielectric layer 128 is greater than the thickness t1 of the first dielectric layer 106.

The COB type DRAM 100a generally further includes a DRAM device 132, such as a bit line 134 (e.g., a metal wire), a buried word line 136 in the substrate 10, a doped region 138 on the surface of the substrate 10, a bit line contact 140 (e.g., a tungsten plug) electrically connecting the bit line 134 and the doped region 138, a storage node contact 142 electrically connecting the first bottom electrode 104 and the other doped region 138, and the like, located below the first capacitor 102. However, the invention is not limited thereto, and any DRAM device known in the field of COB type DRAMs may be used in the invention. In addition, an insulating layer 144 (e.g., an oxide layer) for electrical isolation, inter-layer dielectric (ILD) layers 146a, 146b, 146c, 146d, and the like are also present in the above structure. A first metal layer M1 may be disposed above the first capacitor 102 and electrically connected to the top electrode layer 112 via a contact window 148 (e.g., a tungsten plug), and an active area isolation structure 150 (e.g., STI) is disposed in the substrate 10.

With reference to fig. 1, since the first capacitor 102 has the recess 110, the second capacitor 118 can also have the recess 152, but the size of the recess 152 and the size of the recess 110 are determined by the photomask design, so the sizes and shapes of the two may be the same or different. For example, the grooves 152 and the grooves 110 have cylindrical walls, but the diameter of the grooves 152 may be larger or smaller than the diameter of the grooves 110, and the number of the grooves 152 may be one or more according to the requirement. Since the second top electrode 130 and the first top electrode 108 are fabricated simultaneously, the second top electrode may also include the top electrode layer 112 above the recess 152 and the conductive material 114 filled in the recess 152 and below the top electrode layer 112, and the conductive material 114 in the second capacitor 118 serves as a Control Gate (CG) of the MTP 100 b.

In fig. 1, the MTP 100b may further include a tunneling oxide (tunnel oxide)154 between the substrate 10 and the floating gate 116, and doped regions 156 may be formed as a source and a drain in the substrate 10 on both sides of the floating gate 116. The metal film 124 of the MTP 100b of the first embodiment can also be fabricated at the same time as the bit line 134 of the DRAM device 132, so the material of the bit line 134 can be the same as the metal film 124. For example, after forming the bit line contact 140, the tunnel oxide layer 154 and the conductive layer 122 are formed in the peripheral region, a metal film is formed on the entire substrate 10, and then the metal film is patterned to form the bit line 134 of the DRAM device 132 while the step of patterning the floating gate 116 is performed. Moreover, the control gate of the MTP 100b can be fabricated simultaneously with the capacitor of the COB type DRAM, and the structure thereof can be integrated into a general semiconductor fabrication process, and includes a zeroth metal layer M0 between the second bottom electrode 126 and the contact 120 and directly contacting the contact 120. In addition, the electrically insulating

interlayer dielectrics

146b and 146c used in the COB DRAM 100a and the MTP 100b can be simultaneously fabricated. A first metal layer M1 may also be disposed above the second capacitor 118 and electrically connected to the top electrode layer 112 through the contact window 148. The same reference numerals are used to form the same structures, so as to simplify the manufacturing process. However, the invention is not limited thereto and may be formed by different manufacturing processes.

Fig. 2A to 2J are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a second embodiment of the invention.

Referring to fig. 2A, an active region isolation structure 202 is formed in the substrate 20 in the peripheral region 200a and the cell region 200b, and then a doped region 204 is formed in the substrate 20 in the cell region 200 b. Then, the buried word line 206 is formed in the substrate 20 of the cell region 200b, and the insulating layer 208 may be formed before the buried word line 206 is formed.

Then, referring to fig. 2B, after forming an interlayer dielectric layer 210 on the substrate 20 of the cell region 200B, bit line contacts 212 are formed in the interlayer dielectric layer 210; in addition, a tunnel oxide layer 214 and a conductive layer 216 are formed on the substrate 20 in the peripheral region 200 a. Next, a metal film is fully deposited on the substrate 20 in the peripheral area 200a and the cell area 200b, wherein the metal film 218a in the cell area 200b may be used as a bit line, and the metal film 218b in the peripheral area 200a may be used as a part of a floating gate of the MTP, so as to facilitate subsequent electrical characteristics.

Thereafter, referring to fig. 2C, the metal film 218a of the cell area 200b and the metal film 218b of the peripheral area 200a are patterned to form the bit line 218C of the cell area 200b, and the conductive layer 216 and the tunnel oxide layer 214 under the metal film 218b are continuously etched away to form the floating gate 220 of the peripheral area 200 a. Then, doped regions 222 serving as a source and a drain are formed in the substrate 20 in the peripheral region 200 a.

Next, referring to fig. 2D, an interlayer dielectric layer 224 is formed on the entire surface of the substrate 20.

Next, referring to fig. 2E, at least one contact 226 electrically connected to the floating gate 220 is formed in the interlayer dielectric layer 224 in the peripheral region 200a, wherein the contact 226 is, for example, a tungsten plug, and may be in direct contact with the metal film 218 b. In addition, contact windows 228 may be formed in contact with doped regions 222 at the same time as, or before, contact windows 226 are formed. In addition, a storage node contact 230 connected to the doped region 204 may be formed in the cell region 200b, and an insulating layer 232 isolated from the bit line 218c may be formed before the storage node contact 230 is formed, thereby completing the fabrication of the DRAM device 234 of the COB type DRAM. However, the present invention is not limited thereto, and other steps may be added to the above manufacturing process according to the structural design of the conventional DRAM device 234. Next, a zero-level metal layer M0 is formed on the inter-layer dielectric layer 224 and electrically connected to the floating gate 220 through the contact hole 226 and the metal film 218 b. The zeroth metal layer M0 may also be in contact with the contact window 228.

Thereafter, referring to fig. 2F, another interlayer dielectric layer 500 may be formed on the interlayer dielectric layer 224 in the peripheral region 200a and the cell region 200b, and then a recess structure 502 may be formed in the interlayer dielectric layer 500 on the DRAM device 234 and on the floating gate 220, respectively, wherein the recess structure 502 in the peripheral region 200a exposes the zeroth metal layer M0 on the floating gate 220, and the recess structure 502 in the cell region 200b exposes the storage node contact 230. Although one groove structure 502 is shown in the peripheral region 200a in fig. 2F, the present invention is not limited thereto, and the number of the groove structures 502 formed on the floating gate 220 may be plural.

Then, referring to fig. 2G, a conductive layer 504, such as Ti/TiN, conformal with the groove structure 502 is formed on the substrate 20.

Next, referring to fig. 2H, the conductive layer 504 outside the groove structures 502 in the peripheral region 200a and the cell region 200b is removed, and the first lower electrode 504a in the cell region 200b and the second lower electrode 504b in the peripheral region 200a remain. The method of removing the conductor layer 504 outside the groove structure 502 is, for example, to directly remove the conductor layer 504 outside the groove structure 502; alternatively, a mask layer (not shown) is formed over the entire surface, the mask layer outside the groove structure 502 is removed until the conductive layer 504 is exposed, and then the exposed conductive layer 504 is removed, leaving the first bottom electrode 504a and the second bottom electrode 504b in the groove structure 502.

Then, referring to fig. 2I, a first dielectric layer 506a and a second dielectric layer 506b are formed. In the present embodiment, the first dielectric layer 506a of the cell region 200b and the second dielectric layer 506b of the peripheral region 200a are formed at the same time, so the materials (e.g., high-k material) and the thicknesses are the same. However, in another embodiment, the first dielectric layer 506a and the second dielectric layer 506b are separately formed, and the thickness of the second dielectric layer 506b of the peripheral region 200a may be greater than that of the first dielectric layer 506a of the cell region 200b for large voltage operation. Then, a conductive material 508 (e.g., polysilicon or polycide) is filled into the recess structure 502, and an upper electrode layer 510 is formed on the conductive material 508, wherein the conductive material 508 and the upper electrode layer 510 of the cell region 200b form a first upper electrode 512, thereby completing a first capacitor 520 formed by the first lower electrode 504a, the first dielectric layer 506a and the first upper electrode 512.

Next, referring to fig. 2J, the structure on the ild layer 500 in the peripheral region 200a is patterned to form a second capacitor 522 composed of a second lower electrode 504b, a second dielectric 506b and a second upper electrode 514 (including a conductive material 508a and an upper electrode layer 510a), and the conductive material 508a in the second capacitor 522 is used as a control gate of the MTP.

In fig. 2J, a first capacitor 520 is formed over the DRAM element 234 and a second capacitor 522 is formed over the contact 216. The second capacitor 522 is electrically connected to the floating gate 220 through the contact window 216, so that the floating gate 220, the contact window 226 and the second capacitor 522 form a multiple time programmable Memory (MTP). From the above description, it can be seen that the floating gate, the inter-gate dielectric layer and the control gate of the MTP in this embodiment can be integrated into the manufacturing process of the COB type DRAM.

Fig. 3 is a schematic cross-sectional view of an MTP in a semiconductor device according to a third embodiment of the present invention, wherein the same reference numerals as those in fig. 1 are used to indicate the same or similar components, and the same or similar components can be referred to above, which is not repeated herein.

Referring to fig. 3, in the present embodiment, the capacitive coupling ratio (coupling ratio) is increased by increasing the number of the grooves 152 on the floating gate 116. In detail, the recess 152 is changed into a plurality, the size of the floating gate 116 (e.g., the conductive layer 122 and the metal film 124) may become large, and the number of the contact windows 120 may be increased, so that the second capacitor 300 may be like a plurality of capacitors connected in parallel.

Fig. 4 is a schematic cross-sectional view of an MTP in a semiconductor device according to a fourth embodiment of the present invention, wherein the same reference numerals as those in fig. 1 are used to indicate the same or similar components, and the same or similar components can be referred to above, which is not repeated herein.

Referring to fig. 4, the present embodiment achieves the voltage reduction effect by forming a plurality of second capacitors 400 connected in series, wherein the second capacitors 400 except the second capacitor 400 directly above the floating gate 116 can be connected in series by using the zero-level metal layer M0 and finally connected to the first-level metal layer M1.

In summary, the present invention integrates the MTP floating gate, the inter-gate dielectric layer and the control gate into the COB type DRAM manufacturing process, thereby reducing the manufacturing process time and cost.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device having a cell region and a peripheral region, the semiconductor device comprising:

a substrate;

a capacitor over bit line (COB) type Dynamic Random Access Memory (DRAM) disposed in the cell region, the COB type DRAM including a bit line and a first capacitor; and

a multi-time programmable Memory (MTP) disposed in the peripheral region, wherein the MTP includes:

a floating gate formed on the substrate and patterned simultaneously with the bit line;

the second capacitor is positioned on the floating grid and is a capacitor structure which is manufactured simultaneously with the first capacitor; and

at least one contact window electrically connecting the floating gate and the second capacitor.

2. The semiconductor device of claim 1, wherein the MTP further comprises a tunnel oxide layer between the substrate and the floating gate.

3. The semiconductor device of claim 1, wherein the material of the floating gate comprises doped polysilicon or a polycide.

4. The semiconductor device of claim 1, wherein the MTP further comprises a metal film formed on the surface of the floating gate and directly contacting the at least one contact.

5. The semiconductor device according to claim 4, wherein the metal film and the bit line are structural layers deposited simultaneously.

6. The semiconductor device according to claim 1, wherein the first capacitor comprises a first lower electrode, a first dielectric layer, and a first upper electrode, the second capacitor comprises a second lower electrode, a second dielectric layer, and a second upper electrode, the second lower electrode is an electrode structure fabricated simultaneously with the first lower electrode, and the second upper electrode is an electrode structure fabricated simultaneously with the first upper electrode.

7. The semiconductor device of claim 6, further comprising a zero-level metal layer interposed between said second bottom electrode and said at least one contact and in direct contact with said at least one contact.

8. The semiconductor device according to claim 6, wherein the first capacitor and the second capacitor are structures having grooves, and the first upper electrode and the second upper electrode each comprise:

the upper electrode layer is positioned above the groove; and

and the conductor material is filled in the groove and is positioned below the upper electrode layer.

9. The semiconductor device of claim 8 wherein the conductor material comprises polysilicon or a polycide and the conductor material in the second capacitor serves as a control gate for the MTP.

10. The semiconductor device according to claim 8, wherein the number of the grooves in the second capacitor is plural, constituting a capacitor connected in parallel.

11. The semiconductor device of claim 6, wherein the second dielectric layer and the first dielectric layer are high dielectric constant materials.

12. The semiconductor device according to claim 6, wherein a thickness of the second dielectric layer is larger than a thickness of the first dielectric layer.

13. The semiconductor device according to claim 1, wherein the second capacitor is plural in number, constituting a capacitor connected in series.

14. A method of manufacturing a semiconductor device, comprising:

forming a capacitor over bit line (COB) type Dynamic Random Access Memory (DRAM) element of a DRAM in a cell area, the DRAM element including a bit line;

forming a floating gate in a peripheral area, wherein the floating gate is a structure patterned simultaneously with the bit line;

forming at least one contact window on the floating gate;

and simultaneously manufacturing a first capacitor and a second capacitor, wherein the first capacitor is formed on the DRAM element, the second capacitor is formed on the at least one contact window and is electrically connected to the floating gate through the at least one contact window, so that the floating gate, the at least one contact window and the second capacitor form a multi-time programmable Memory (MTP).

15. The method for manufacturing a semiconductor device according to claim 14, wherein before forming the floating gate, further comprising: and forming a tunneling oxide layer on the substrate in the peripheral area.

16. The method for manufacturing a semiconductor device according to claim 14, wherein after forming the floating gate, further comprising: and forming a metal film on the surface of the floating gate.

17. The method for manufacturing a semiconductor device according to claim 14, wherein the method for simultaneously forming the first capacitor and the second capacitor comprises:

simultaneously fabricating a first lower electrode of the first capacitor and the second lower electrode of the second capacitor;

forming a first dielectric layer on the first lower electrode;

forming a second dielectric layer on the second lower electrode; and

simultaneously forming a first upper electrode of the first capacitor on the first dielectric layer and a second upper electrode of the second capacitor on the second dielectric layer.

18. The method of manufacturing a semiconductor device according to claim 17, wherein the step of simultaneously forming the first capacitor and the second capacitor further comprises: a recess structure is formed on each of the DRAM elements and the floating gate.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the method for forming the first upper electrode and the second upper electrode comprises:

filling conductor materials into the groove structure; and

an upper electrode layer is formed on the conductor material, and the conductor material in the second capacitor is used as a control gate of the MTP.

20. The method for manufacturing a semiconductor device according to claim 18, wherein the number of the recess structures formed on the floating gate is plural.

21. The method for manufacturing a semiconductor device according to claim 17, wherein the first dielectric layer and the second dielectric layer are formed simultaneously.

22. The method for manufacturing a semiconductor device according to claim 17, wherein the first dielectric layer and the second dielectric layer are formed separately, and a thickness of the second dielectric layer is larger than a thickness of the first dielectric layer.

23. The method of manufacturing a semiconductor device according to claim 14, wherein the step of simultaneously forming the first capacitor and the second capacitor further comprises: and forming a zero metal layer on the at least one contact window.

24. The method for manufacturing a semiconductor device according to claim 14, wherein the second capacitors are plural in number and connected in series with each other.