CN113921466A - TP RC loading reducing method - Google Patents
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- CN113921466A CN113921466A CN202111173084.5A CN202111173084A CN113921466A CN 113921466 A CN113921466 A CN 113921466A CN 202111173084 A CN202111173084 A CN 202111173084A CN 113921466 A CN113921466 A CN 113921466A
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000011521 glass Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000008878 coupling Effects 0.000 claims abstract description 6
- 238000010168 coupling process Methods 0.000 claims abstract description 6
- 238000005859 coupling reaction Methods 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000001808 coupling effect Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
- G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Manufacturing & Machinery (AREA)
- Position Input By Displaying (AREA)
Abstract
The invention discloses a TP RC loading reducing method, which comprises the following steps: s1: manufacturing a GE layer, namely a grid electrode, on a glass substrate, manufacturing a GI layer on the basis of the GE layer, manufacturing an SE layer on the basis of the GI layer, and manufacturing an ES layer above the SE layer; s2: then, an SD layer is manufactured above the ES layer, the SD layer and the SE layer are connected to form a complete TFT structure by etching a through hole of the ES layer, and meanwhile, another SD layer is manufactured above the ES layer to serve as a TP routing; s3: a PV layer is formed on the SD layer, an OC layer is formed on the PV layer, the drain is connected with the PIXEL ITO, a CH layer is formed on the PIXEL ITO, and VCOM ITO is formed on the CH layer. The invention provides a TP RC loading reducing method, which is characterized in that an electrode film layer is added between a GI layer and an ES layer to shield a Scan signal and a TP signal, so that the TP signal is greatly reduced by the capacitive coupling effect of the Scan signal, and the purpose of optimizing the horizontal stripes of a touch screen is achieved. Effectively reducing the capacitive coupling of the Scan signal to the TP signal.
Description
Technical Field
The invention belongs to the technical field of touch screens, and particularly relates to a TP RC loading reducing method.
Background
In recent years, the touch screen display market has now entered product diversification, from small-sized mobile phones to medium-sized NB, tablet, vehicle-mounted, and even to IT products.
Touch technologies mainly include an Out cell and an In cell, and for mobile phones, tablet phones and NB products, the Out cell is gradually replaced by the In cell In consideration of cost, weight and thickness.
At present, embedded (In cell) products have a trend of gradually increasing toward medium and large sizes, and with the trend of increasing the panel size, under a Flicker screen, TP blocks (touch screen cross stripes) of the embedded (In cell) products become more serious. Therefore, we propose a TP RC loading reduction method to solve the above mentioned problems in the background art.
Disclosure of Invention
The present invention provides a method for reducing TP RC loading, so as to solve the problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: a TP RC loading reducing method comprises the following steps:
s1: manufacturing a GE layer, namely a grid electrode, on a glass substrate, manufacturing a GI layer, namely a first insulating layer, on the basis of the GE layer, manufacturing a SE layer, namely a semiconductor layer, on the basis of the GI layer, and manufacturing an ES layer, namely a second insulating layer, above the SE layer to play a role in protecting the SE layer;
s2: then, an SD layer is manufactured above the ES layer and is used as a source electrode and a drain electrode of the TFT switch, the SD layer and the SE layer are connected through etching a through hole of the ES layer to form a complete TFT structure, and meanwhile, another SD layer is manufactured above the ES layer and is used as a TP routing;
s3: a PV layer, namely a third insulating layer, is manufactured above the SD layer, an OC layer, namely a fourth insulating layer, is manufactured above the PV layer, a drain electrode is connected with the PIXEL ITO through etching through holes of the OC layer and the PV layer, so that a signal of an SD source electrode can be transmitted to the drain electrode through an SE layer and then transmitted to the PIXEL ITO when a grid electrode is in a high voltage state, a CH layer, namely a fifth insulating layer, is manufactured above the PIXEL ITO, and a VCOM ITO layer is manufactured above the CH layer.
The touch screen is characterized in that a coupling phenomenon exists between the TP wiring and the grid electrode, the ITO layer is manufactured above the GI layer and is arranged between the grid electrode and the TP wiring, the grid electrode is prevented from being influenced by the TP wiring, and the cross grains of the touch screen caused by the fact that the TP wiring is coupled with the grid electrode are eliminated.
The thickness of the glass substrate is 0.3-0.5 mm.
In cell, Touch panel (Touch panel), and Touch panel cross stripe (TP Block).
The invention is suitable for an unbound In-cell (Incell) touch screen panel.
Compared with the prior art, the invention has the beneficial effects that: the invention provides a TP RC loading reducing method, which mainly increases a photomask, adds an electrode film layer (namely an ITO layer) between a GI layer and an ES layer, and shields a Scan signal and a TP signal, so that the TP signal is greatly reduced by the capacitive coupling effect of the Scan signal, and the aim of optimizing TP Block is fulfilled. Effectively reducing the capacitive coupling of the Scan signal to the TP signal. The ITO layer is placed between the Scan and the TP to serve as a shield, so that the capacitive coupling effect of the Scan to the TP can be reduced, and the purpose of optimizing the TP Block is achieved.
Drawings
FIG. 1 is a schematic diagram of a pixel arrangement structure according to the prior art;
FIG. 2 is a schematic diagram of a two-pixel arrangement structure according to the prior art;
FIG. 3 is a schematic diagram of the TP capacitive coupling effect before and after improvement;
FIG. 4 is a schematic diagram of a pixel arrangement structure according to the present invention;
FIG. 5 is a schematic cross-sectional view of a pixel cell of the prior art;
FIG. 6 is a schematic cross-sectional view of a pixel cell in accordance with the teachings of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, taking the TOP COM 9PEP architecture as an example, TP lines are all overlapped on Data lines (as shown in fig. 1), but due to the increase in size and resolution, the Data capacitive coupling effect on TP is increased, so that the TP lines are not overlapped on the Data lines (as shown in fig. 2) as a design, and because TP lines are not overlapped on the Data lines, the TP lines can adopt the same film metal2 as the Data lines, and the distance between TP lines and COM layers is increased, so as to reduce the capacitance between TP lines and COM layers (originally, the overlapped TP lines need to adopt metal3, which is close to COM layers), but the TP lines and Scan lines are still overlapped. Therefore, the TP Block mainly comes from the coupling effect of the Scan signal on the TP traces (as shown in fig. 3), the larger the size is, the higher the resolution is, the more severe the TP Block problem becomes, and this patent optimizes the TP Block problem with a new design.
The invention provides a TP RC loading reducing method as shown in figure 3, figure 4 and figure 6, which comprises the following steps:
s1: manufacturing a GE layer, namely a grid electrode, on a glass substrate, manufacturing a GI layer, namely a first insulating layer, on the basis of the GE layer, manufacturing a SE layer, namely a semiconductor layer, on the basis of the GI layer, and manufacturing an ES layer, namely a second insulating layer, above the SE layer to play a role in protecting the SE layer;
s2: then, an SD layer is manufactured above the ES layer and is used as a source electrode and a drain electrode of the TFT switch, the SD layer and the SE layer are connected through etching a through hole of the ES layer to form a complete TFT structure, and meanwhile, another SD layer is manufactured above the ES layer and is used as a TP routing;
s3: a PV layer, namely a third insulating layer, is manufactured above the SD layer, an OC layer, namely a fourth insulating layer, is manufactured above the PV layer, a drain electrode is connected with the PIXEL ITO through etching through holes of the OC layer and the PV layer, so that a signal of an SD source electrode can be transmitted to the drain electrode through an SE layer and then transmitted to the PIXEL ITO when a grid electrode is in a high voltage state, a CH layer, namely a fifth insulating layer, is manufactured above the PIXEL ITO, and a VCOM ITO layer is manufactured above the CH layer.
The touch screen is characterized in that a coupling phenomenon exists between the TP wiring and the grid electrode, the ITO layer is manufactured above the GI layer and is arranged between the grid electrode and the TP wiring, the grid electrode is prevented from being influenced by the TP wiring, and the cross grains of the touch screen caused by the fact that the TP wiring is coupled with the grid electrode are eliminated.
The thickness of the glass substrate is 0.3-0.5 mm.
In summary, there is no masking Pattern between TP and Scan compared to the prior art. In order to reduce the capacitive coupling of Scan to TP, the present invention utilizes an electrode film (the present invention takes Pixel signal as an example) between TP and Scan line for shielding (as shown in fig. 4), and it can be understood from the cross-sectional view that there is no signal between Gate and TP as shielding (as shown in fig. 5) in the prior art.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.
Claims (4)
1. A TP RC loading reducing method is characterized in that: the method comprises the following steps:
s1: manufacturing a GE layer, namely a grid electrode, on a glass substrate, manufacturing a GI layer, namely a first insulating layer, on the basis of the GE layer, manufacturing a SE layer, namely a semiconductor layer, on the basis of the GI layer, and manufacturing an ES layer, namely a second insulating layer, above the SE layer to play a role in protecting the SE layer;
s2: then, an SD layer is manufactured above the ES layer and is used as a source electrode and a drain electrode of the TFT switch, the SD layer and the SE layer are connected through etching a through hole of the ES layer to form a complete TFT structure, and meanwhile, another SD layer is manufactured above the ES layer and is used as a TP routing;
s3: and manufacturing a PV layer (third insulating layer) above the SD layer, manufacturing an OC layer (fourth insulating layer) above the PV layer, connecting the drain with the PIXEL ITO by etching through holes of the OC layer and the PV layer, manufacturing a CH layer (fifth insulating layer) above the PIXEL ITO, and manufacturing a VCOM ITO above the CH layer.
2. The method according to claim 1, wherein the method for reducing TP RC loading comprises: the touch screen is characterized in that a coupling phenomenon exists between the TP wiring and the grid electrode, the ITO layer is manufactured above the GI layer and is arranged between the grid electrode and the TP wiring, the grid electrode is prevented from being influenced by the TP wiring, and the cross grains of the touch screen caused by the fact that the TP wiring is coupled with the grid electrode are eliminated.
3. The method according to claim 1, wherein the method for reducing TP RC loading comprises: the thickness of the glass substrate is 0.3-0.5 mm.
4. The method according to claim 1, wherein the method for reducing TP RC loading comprises: the drain is connected to the PIXEL ITO so that the signal from the SD source can be transmitted to the drain through the SE layer and thus to the PIXEL ITO at high gate voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111173084.5A CN113921466A (en) | 2021-10-08 | 2021-10-08 | TP RC loading reducing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111173084.5A CN113921466A (en) | 2021-10-08 | 2021-10-08 | TP RC loading reducing method |
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| CN113921466A true CN113921466A (en) | 2022-01-11 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2434379A2 (en) * | 2010-09-24 | 2012-03-28 | Hitachi Displays, Ltd. | Display device |
| CN104103647A (en) * | 2014-07-08 | 2014-10-15 | 京东方科技集团股份有限公司 | Array substrate, preparation method and touch control display device |
| CN105470194A (en) * | 2014-09-30 | 2016-04-06 | 朗姆研究公司 | Feature fill with nucleation inhibition |
| CN105528126A (en) * | 2014-10-17 | 2016-04-27 | 瑞鼎科技股份有限公司 | In-cell touch panel and trace layout thereof |
| CN110993563A (en) * | 2019-11-22 | 2020-04-10 | 福建华佳彩有限公司 | OLED panel and manufacturing method thereof |
| CN213149729U (en) * | 2020-09-18 | 2021-05-07 | 福建华佳彩有限公司 | Touch screen structure |
-
2021
- 2021-10-08 CN CN202111173084.5A patent/CN113921466A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2434379A2 (en) * | 2010-09-24 | 2012-03-28 | Hitachi Displays, Ltd. | Display device |
| CN104103647A (en) * | 2014-07-08 | 2014-10-15 | 京东方科技集团股份有限公司 | Array substrate, preparation method and touch control display device |
| CN105470194A (en) * | 2014-09-30 | 2016-04-06 | 朗姆研究公司 | Feature fill with nucleation inhibition |
| CN105528126A (en) * | 2014-10-17 | 2016-04-27 | 瑞鼎科技股份有限公司 | In-cell touch panel and trace layout thereof |
| CN110993563A (en) * | 2019-11-22 | 2020-04-10 | 福建华佳彩有限公司 | OLED panel and manufacturing method thereof |
| CN213149729U (en) * | 2020-09-18 | 2021-05-07 | 福建华佳彩有限公司 | Touch screen structure |
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