CN113917748B

CN113917748B - Array substrate, display panel and display device

Info

Publication number: CN113917748B
Application number: CN202111204327.7A
Authority: CN
Inventors: 任文艳; 古宏刚
Original assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Current assignee: Nanjing Boe Display Technology Co ltd; BOE Technology Group Co Ltd
Priority date: 2021-10-15
Filing date: 2021-10-15
Publication date: 2023-10-13
Anticipated expiration: 2041-10-15
Also published as: CN113917748A

Abstract

The application discloses an array substrate, a display panel and display equipment; wherein the array substrate includes: the GOA device region, the first clock line group and the second clock line group; the input end of each GOA device in the GOA device area is respectively connected with corresponding clock lines in the first clock line group and the second clock line group; the first clock line group is arranged on a first side of the GOA device region, the second clock line group is arranged on a second side of the GOA device region, and the first side and the second side of the GOA device region are opposite sides. The application can reduce the breakdown risk caused by potential accumulation between clock lines when the display panel works for a long time, and improve the phenomena of transverse stripes and black screens of the display panel.

Description

Array substrate, display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.

Background

In an active liquid crystal display, each pixel has a thin film transistor (Thin Film Transistor, TFT) with a Gate electrode (Gate) connected to a horizontal scanning line, a Drain electrode (Drain) connected to a vertical data line, and a Source electrode (Source) connected to a pixel electrode. When a sufficient driving voltage is applied to the horizontal scanning line, all the thin film transistors on the scanning line are turned on, and at the moment, the data line in the vertical direction writes the data voltage into the pixels through the drain electrodes of the thin film transistors, so that the effect of controlling display is achieved. The array substrate row driving technology (Gate Driver on Array, GOA) is a driving circuit structure capable of replacing an external IC, reduces IC Bonding procedures, and can remarkably improve the cost performance of products and reduce the cost; in addition, the design of the narrow frame of the liquid crystal display panel can be realized. However, the conventional display panel is degraded in stability after a long-time start, and is prone to defects such as moire and black screen.

Disclosure of Invention

The present application has been made in view of the above problems, and has as its object to provide an array substrate, a display panel and a display device capable of reducing the risk of breakdown caused by accumulation of electric potential between clock lines when the display panel is operated for a long period of time, and improving the moire and black screen phenomena of the display panel.

In a first aspect, the present application provides, by way of an embodiment, the following technical solutions:

an array substrate, comprising: the GOA device region, the first clock line group and the second clock line group; the input end of each GOA device in the GOA device area is respectively connected with corresponding clock lines in the first clock line group and the second clock line group; the first clock line group is arranged on a first side of the GOA device region, the second clock line group is arranged on a second side of the GOA device region, and the first side and the second side of the GOA device region are opposite sides.

Optionally, the number of clock lines in the first clock line group and the number of clock lines in the second clock line group are the same.

Optionally, the clock lines in the first clock line group are in one-to-one correspondence with the clock lines in the second clock line group, and clock pulse waveforms input on the corresponding two clock lines are inverted.

Optionally, a time interval between rising edges of clock pulses input by every two adjacent clock lines in the first clock line group is 2H; the time interval between the rising edges of clock pulses input by every two adjacent clock lines in the second clock line group is 2H; wherein H represents a time period required to scan 1 line in the display panel while maintaining the original refresh rate.

Optionally, a time interval between rising edges of clock pulses input by every two adjacent clock lines in the first clock line group is 3H; the time interval between the rising edges of clock pulses input by every two adjacent clock lines in the second clock line group is 3H; wherein H represents a time period required to scan 1 line in the display panel while maintaining the original refresh rate.

Optionally, the first clock line group, the second clock line group and the GOA device region are disposed on the same side of the active display region.

Optionally, the GOA device area includes a first GOA area and a second GOA area, where GOA devices in the first GOA area are correspondingly connected to clock lines in the first clock line group, and GOA devices in the second GOA area are correspondingly connected to clock lines in the second clock line group; the first GOA area and the first clock line group are arranged on the first side of the effective display area, and the second GOA area and the second clock line group are arranged on the second side of the effective display area.

Optionally, the first GOA area is disposed between the first clock line group and the effective display area, and the second GOA area is disposed between the second clock line group and the effective display area.

According to the second aspect, based on the same inventive concept, the present application further provides, through an embodiment, the following technical solutions:

a display panel comprising the array substrate of any one of the first aspects.

In a third aspect, based on the same inventive concept, the present application further provides, through an embodiment, the following technical solutions:

a display device comprising the display panel of any one of the above second aspects.

The technical scheme provided by the embodiment of the application has at least the following technical effects or advantages:

the embodiment of the application provides an array substrate, a display panel and display equipment, wherein the array substrate comprises the following components: the GOA device region, the first clock line group and the second clock line group; the input end of each GOA device in the GOA device area is respectively connected with corresponding clock lines in the first clock line group and the second clock line group; the first clock line group is arranged on a first side of the GOA device region, the second clock line group is arranged on a second side of the GOA device region, and the first side and the second side of the GOA device region are opposite sides; therefore, for any clock line, the number of overlines between the clock line and other clock lines is reduced, potential accumulation between the clock lines is reduced when the display panel works or works for a long time, the risk of breakdown between the clock lines is reduced, and the phenomena of transverse stripes and black screens of the display panel are improved.

The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram of a driving waveform of 8CK in an embodiment of the present application;

FIG. 2 is a schematic diagram of a clock line of an array substrate according to the prior art in an embodiment of the present application;

fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

According to the application, the display panel is tested and analyzed, so that the wiring structure of the clock line of the display panel is one of the major reasons for the occurrence of defects such as transverse stripes, black screens and the like; currently, when the clock lines of the display panel are routed, the clock lines are parallel or approximately parallel to the edges of the display panel and then connected to the GOA devices through a turn, and the GOA devices are arranged in rows along the side edges of the display panel, and a cross-line condition exists between different metal lines, as shown in fig. 1. When the display panel is started, potential difference exists in different metal layer circuits in the clock line through level signals for a long time, and breakdown easily occurs between the metal lines after local potential is accumulated to a certain degree, so that defects such as transverse lines, black screens and the like of the display panel are caused. For example, taking 8CK (8 clock, 8clock signal) as an example, by analyzing multiple sets of panels, the results are as follows:

TABLE 1 Cross grain and black screen failure analysis

In table 1, ID represents a panel number, resistance represents a resistance of a short circuit between two clock lines, a short circuit point represents a row where the short circuit occurs, and cause analysis represents analysis of a metal layer of a display panel by a conventional method such as a scanning electron microscope; DGS represents a short circuit formed by breakdown of a metal layer (clock line); the opposite signal indicates the waveform inversion of the driving signal (clock signal) input from the clock line. Further, referring to fig. 2, it can be seen from fig. 2 that in the driving waveform of 8CK, the waveforms of the driving signals of different lines are opposite, especially, the CK1 signal and CK5 signal, the CK2 signal and CK6 signal, the CK3 signal and CK7 signal, and the CK4 signal and CK8 signal, and the waveforms of the driving signals are completely opposite, i.e. inverted, so that the risk of breakdown is higher. Meanwhile, in table 1, it can also be seen that in the position where breakdown occurs, the case where the drive signals are completely opposite occupies nearly half of the ratio.

In view of this, an embodiment of the present application provides an array substrate, so as to improve a clock line wiring structure of a display panel in the prior art, thereby at least partially solving and optimizing defects such as cross grains and black screens of the display panel caused by the wiring structure. The implementation details and the beneficial effects of the GOA circuit structure of the present application are explained and illustrated in more detail below by means of specific embodiments.

Referring to fig. 3, in an embodiment of the application, an array substrate 100 is provided, where the array substrate 100 includes: GOA device region 110, first set of clock lines 120, and second set of clock lines 130.

The GOA device region 110 has a plurality of GOA devices disposed therein, the first clock line group 120 including one or more clock lines, and the second clock line group 130 including one or more clock lines; the input end of each GOA device is respectively connected with the corresponding clock line, and the output end of each GOA device is connected with the corresponding scanning line. The first clock line group 120 is disposed on a first side of the GOA device region 110, the second clock line group 130 is disposed on a second side of the GOA device region 110, and the first side and the second side of the GOA device region 110 are opposite sides. By arranging the clock lines on the first side and the second side of the GOA device region 110 respectively, the structure effectively reduces the number of overlines among the clock lines, and reduces potential accumulation among the clock lines when the display panel works or works for a long time, thereby reducing breakdown risk among the clock lines and improving the cross grain and black screen phenomena of the display panel.

In the present embodiment, the number of clock lines in the first clock line group 120 and the second clock line group 130 is not limited. For example, in a display panel for an 8CK drive signal, the number of clock lines in the first clock line group 120 and the second clock line group 130 may be 4; referring to fig. 3, at this time, GOA1 to GOA4 are correspondingly connected to each clock line in the first clock line group 120, GOA9 to GOA12 are correspondingly connected to each clock line in the first clock line group 120, and so on; GOA 5-GOA 8 are correspondingly connected to each of the second set of clock lines 130, GOA 13-GOA 16 are correspondingly connected to each of the second set of clock lines 130, and so on. In addition, the number of clock lines in the first clock line group 120 and the second clock line group 130 may also be different. For example, the number of clock lines in the first clock line group 120 may be 3, and the number of clock lines in the second clock line group 130 may be 5; at this time, GOA1 to GOA3 are correspondingly connected to each clock line in the first clock line group 120, GOA9 to GOA11 are correspondingly connected to each clock line in the first clock line group 120, and so on; GOA 4-GOA 8 are correspondingly connected with each clock line in the second clock line group 130, GOA 12-GOA 16 are correspondingly connected with each clock line in the second clock line group 130, and so on; not shown in the drawings. Similarly, in the display panel for 16CK driving signals, the number of clock lines in the first clock line group 120 and the second clock line group 130 may be the same or different, and is not limited.

In a preferred implementation, the number of clock lines in the first set of clock lines 120 and the second set of clock lines 130 is the same. In this case, since the clock lines are uniformly distributed on both sides of the GOA device region 110, after the display panel starts to operate, potential accumulation on the clock lines caused by the driving signals on either side is effectively reduced, and breakdown risk between the clock lines is reduced; meanwhile, for any clock line, the number of possible breakdown other clock lines is reduced from 7 to 3 at present, so that the risk of breakdown is further reduced.

In some embodiments, when the positions of the clock lines are set, the positions may be determined according to waveforms of the driving signals corresponding to the clock lines, or in other words, waveforms of the driving signals of the clock lines distributed on two sides of the GOA device may satisfy the following conditions: the clock lines in the first clock line group 120 are in one-to-one correspondence with the clock lines in the second clock line group 130, and the clock pulse waveforms input on the corresponding two clock lines are inverted. For example:

referring to fig. 2 and 3, the pulse waveforms of the CK1 signal and the CK5 signal are inverted, the pulse waveforms of the CK2 signal and the CK6 signal are inverted, the pulse waveforms of the CK3 signal and the CK7 signal are inverted, and the pulse waveforms of the CK4 signal and the CK8 signal are inverted. When the clock pulse waveforms of the two clock lines are in opposite phases, the potential accumulation time between the two clock lines is longest, and breakdown risks are more likely to occur; at this time, clock lines corresponding to CK1 signal, CK2 signal, CK3 signal and CK4 signal may be disposed on one side of the GOA device region 110, and clock lines corresponding to CK5 signal, CK6 signal, CK7 signal and CK8 signal may be disposed on the other side of the GOA device region 110, so that clock lines with completely inverted clock waveforms may be disposed on both sides of the GOA device region 110, thereby effectively reducing breakdown risk between the clock lines.

In some embodiments, the time interval between rising edges of clock pulses input by each adjacent two clock lines in the first clock line group 120 is 2H; the time interval between the rising edges of the clock pulses input by every two adjacent clock lines in the second clock line group 130 is 2H; wherein H represents a time period required to scan 1 line in the display panel while maintaining the original refresh rate. Likewise, the time interval between the rising edges of the clock pulses input by every two adjacent clock lines in the first clock line group 120 may be 3H; by this, the time interval between rising edges of clock pulses input by every two adjacent clock lines in the second clock line group 130 is 3H, and thus, various implementations can be obtained. By adopting the implementation mode, potential accumulation can be reduced, and breakdown risk between clock lines is reduced.

In this embodiment, in the case where two sets of clock lines are respectively disposed on two sides of the GOA device Area 110, the two sets of clock lines and the GOA devices connected thereto may have the following two implementation manners with respect to the Active Area (AA Area) 140 of the display panel: one is that the first clock line group 120, the second clock line group 130, and the GOA device region 110 are disposed on the same side of the active display region 140. The implementation can be effectively applied to a display panel driven by a single side or a display panel driven by two sides. Secondly, the GOA device region 110 includes a first GOA region 111 and a second GOA region 112, where GOA devices in the first GOA region 111 are correspondingly connected to clock lines in the first clock line group 120, and GOA devices in the second GOA region 112 are correspondingly connected to clock lines in the second clock line group 130; the first GOA area 111 and the first clock line group 120 are disposed on a first side of the active display area 140, and the second GOA area 112 and the second clock line group 130 are disposed on a second side of the active display area 140, such as the array substrate 200 shown in fig. 4. Specifically, the first GOA area 111 is disposed between the first clock line group 120 and the active display area 140, and the second GOA area 112 is disposed between the second clock line group 130 and the active display area 140. In the implementation mode, the two groups of scan lines are completely independent, so that the cross line between the clock line and the scan line is avoided, and the potential accumulation is effectively reduced.

Based on the same inventive concept, in yet another embodiment of the present application, there is also provided a display panel including the array substrate described in any one of the foregoing embodiments. The display panel adopts the array substrate structure, wherein the clock lines are arranged at two sides of the GOA device region. Therefore, the differences, specific implementation and beneficial effects of the display panel in this embodiment from the prior art can be seen from the foregoing embodiments, and the details are not repeated in this embodiment. All display panels including the array substrate according to the foregoing embodiments of the present application are within the scope of the present application.

Based on the same inventive concept, in a further embodiment of the present application, there is also provided a display apparatus including the display panel in the foregoing embodiment. The display device adopts the array substrate in the embodiment, wherein the clock lines are arranged at two sides of the GOA device region. Therefore, the differences, specific implementation and beneficial effects of the display device in this embodiment from the prior art can be seen from the foregoing embodiments, and the details are not repeated in this embodiment. All display devices including the array substrate according to the foregoing embodiments of the present application are within the scope of the present application.

It should be noted that, the display device may be: any product or component with display function such as a mobile phone, a liquid crystal panel, an OLED panel, electronic paper, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

In summary, the array substrate, the display panel and the display device provided in the embodiment, where the array substrate or the array substrate included in the display panel and the display device includes: the GOA device region, the first clock line group and the second clock line group; the input end of each GOA device in the GOA device area is respectively connected with corresponding clock lines in the first clock line group and the second clock line group; the first clock line group is arranged on a first side of the GOA device region, the second clock line group is arranged on a second side of the GOA device region, and the first side and the second side of the GOA device region are opposite sides; therefore, for any clock line, the number of overlines between the clock line and other clock lines is reduced, potential accumulation between the clock lines is reduced when the display panel works or works for a long time, the risk of breakdown between the clock lines is reduced, and the phenomena of transverse stripes and black screens of the display panel are improved.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.

Claims

1. An array substrate, characterized by comprising: the GOA device comprises a GOA device region, a first clock line group and a second clock line group, wherein the number of clock lines in the first clock line group is the same as the number of clock lines in the second clock line group; clock lines in the first clock line group correspond to clock lines in the second clock line group one by one, and clock pulse waveforms input on the two corresponding clock lines are in opposite phases; the input end of each GOA device in the GOA device area is respectively connected with corresponding clock lines in the first clock line group and the second clock line group; the first clock line group is arranged on a first side of the GOA device region, the second clock line group is arranged on a second side of the GOA device region, and the first side and the second side of the GOA device region are opposite sides.

2. The array substrate of claim 1, wherein a time interval between rising edges of clock pulses input by every two adjacent clock lines in the first clock line group is 2H; the time interval between the rising edges of clock pulses input by every two adjacent clock lines in the second clock line group is 2H; wherein H represents a time period required to scan 1 line in the display panel while maintaining the original refresh rate.

3. The array substrate of claim 1, wherein a time interval between rising edges of clock pulses input by every two adjacent clock lines in the first clock line group is 3H; the time interval between the rising edges of clock pulses input by every two adjacent clock lines in the second clock line group is 3H; wherein H represents a time period required to scan 1 line in the display panel while maintaining the original refresh rate.

4. The array substrate of claim 1, wherein the first set of clock lines, the second set of clock lines, and the GOA device region are disposed on a same side of an active display region.

5. The array substrate of claim 1, wherein the GOA device region comprises a first GOA region and a second GOA region, the GOA devices in the first GOA region being correspondingly connected to the clock lines in the first clock line group, the GOA devices in the second GOA region being correspondingly connected to the clock lines in the second clock line group; the first GOA area and the first clock line group are arranged on the first side of the effective display area, and the second GOA area and the second clock line group are arranged on the second side of the effective display area.

6. The array substrate of claim 5, wherein the first GOA region is disposed between the first set of clock lines and the active display region, and the second GOA region is disposed between the second set of clock lines and the active display region.

7. A display panel comprising the array substrate of any one of claims 1-6.

8. A display device comprising the display panel of any one of claims 7.