CN113904680A

CN113904680A - Method for quickly relocking DLL circuit

Info

Publication number: CN113904680A
Application number: CN202111082977.9A
Authority: CN
Inventors: 亚历山大; 上官朦朦
Original assignee: Zhejiang Liji Electronics Co ltd
Current assignee: Zhejiang Liji Electronics Co ltd
Priority date: 2021-09-15
Filing date: 2021-09-15
Publication date: 2022-01-07

Abstract

The method for rapidly relocking the DLL circuit provided by the invention comprises the steps of setting the DLL circuit; the method comprises the following steps: and detecting whether overflow or underflow exists in real time, and correspondingly setting a control signal according to a detection result to control the delay of the internal clock. The method can greatly reduce the loss of instructions and data, and can restore the normal phase locking state in time without resetting the DLL circuit; the clock with the minimum error can be provided for the output data when the overflow or underflow occurs, the data can be quickly locked again, and the data transmission accuracy rate is high and the stability is good; the adverse effect of temperature change on clock processing is effectively solved; the method is favorable for improving the working reliability of the DRAM and further promoting the deep application of the integrated circuit technology.

Description

Method for quickly relocking DLL circuit

Technical Field

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a method for quickly re-locking a DLL (delay locked loop) circuit.

Background

The dynamic random access memory DRAM and the external control chip CPU accurately complete the transmission of instructions and data through clocks. In the read operation, the DRAM needs to provide an output clock dqs, which is mainly used to accurately distinguish each transmission cycle within one clock cycle (tCK) and facilitate accurate data reception by the receiving side. When the output clock dqs and the external clock clk are in large phase difference, the CPU will catch up the wrong instructions and data. Adjusting the output clock dqs of the DRAM to align the output clock dqs with the external clock clk is mainly implemented by a delay Locked loop (dll) (delay Locked loop) circuit. The DLL circuit keeps the output clock dqs and the external clock clk phase aligned by providing an amount of delay.

Unstable voltage and temperature variations in the operation of the DRAM chip often cause the DLL circuit to fail to operate properly, which is generally referred to as a DLL circuit loss of lock. Two of these prominent loss-of-lock conditions are commonly referred to as: overflow and underflow. The overflow is generally that the DLL circuit continues to issue instructions to increase the delay, but the DLL circuit has provided the maximum amount of delay, cannot increase the amount of delay any more, the output clock dqs will maintain the current unlocked state, and no adjustments can be made. The underflow is an instruction for the DLL circuit to continue issuing reduced delays, but the DLL circuit already provides the minimum amount of delay it can accommodate, cannot reduce the amount of delay any more, causes phase lock loss, and cannot make adjustments out of the current overflow or underflow. In either case, the memory chip cannot provide data and instructions at the correct time, resulting in a data transfer failure. Particularly, with the development of the integrated circuit technology and the deepening of the application requirements, when the device integrated with the DRAM is applied to an extreme environment, a sudden temperature change occurs, and an overflow or underflow phenomenon is more likely to occur, so that the output clock dqs of the DRAM cannot be aligned with the external clock clk, and at this time, the phase of the output clock dqs cannot be corrected by the existing DLL circuit, and the memory chip cannot accurately transmit data finally.

A known solution is to reset the DLL circuit. It takes a relatively long time to reset the DLL circuit, and for example, in DDR4-2666 memories, the required latch time (locking time) of the DLL circuit is 854 tCK. During this time, the DRAM chip cannot receive any commands and subsequent commands will be lost. For DRAM chips that are in operation, it is clear that resetting the DLL circuit does not quickly relock the DLL circuit, and is not an effective solution to overflow or underflow. Adverse effects from the over flow or under flow induced by temperature variations and the like limit the use of DRAM memory and integrated circuit devices having the same in complex environments.

Therefore, there is a need for a method for quickly re-locking a DLL circuit, which can recover to a normal locked state of the DLL circuit in a short time without resetting the DLL circuit, and solve the problem of a large amount of lost instructions and data when the DLL circuit generates an underflow or overflow phenomenon in a DRAM memory, thereby further promoting the deep development and wide application of semiconductor integrated circuit technology.

Disclosure of Invention

The present invention is directed to solve all or some of the problems of the prior art described above, and provides a method for quickly re-locking a DLL circuit, which is used to enable the DLL circuit to jump out of an overflow or underflow state in time, re-lock in a short time, and achieve correct transmission of data and instructions.

To facilitate an understanding of the present invention, the operating principles of the DLL circuit and the overflow and underflow phenomena involved in the present invention are described by way of example and not limitation. As shown in fig. 1, the external clock clk is provided by the CPU. The DLL circuit comprises a duty ratio adjusting module DCC (duty Cycle correction) for adjusting the duty ratio of the clock and a delay chain module delay _ line for providing adjustable delay. There is also a fixed delay block delay replica to replicate the real delay of the Logic circuit in fig. 1. This is because the Logic circuit needs to add the influence of the Logic circuit on the clock after the DLL circuit, so that the output clock dqs passing through the Logic circuit may be aligned with the clk phase. In the invention, overflow refers to the phase difference indication output by the phase detection module phase detect, which needs to continuously increase the delay amount provided by the current DLL circuit, but the delay chain module delay _ line provides the maximum delay amount at this time. The underflow indicates that the phase difference output by the phase detection module phase detect indicates that the delay amount needs to be reduced continuously, but the delay chain module delay _ line provides the minimum delay amount at this time. Since the amount of delay required to be provided by the delay chain module delay _ line due to underflow or overflow exceeds the adjustable range, if the control module control continuously requires to increase or decrease the delay units participating in the delay chain module delay _ line only according to the phase difference output by the phase detection module, the delay chain module delay _ line will be stuck at the maximum or minimum of the delay amount, so that the DRAM is in an out-of-lock state and needs to be locked again.

The invention provides a method for quickly relocking a DLL circuit, wherein the DLL circuit comprises a control module and a delay chain module; the delay chain module comprises a coarse adjustment delay module and a fine adjustment delay module which are connected in series; the method comprises the following steps: s1, acquiring a phase difference between a current external clock and a DLL circuit feedback clock and a current delay amount provided by a coarse delay module through a control module; s2, judging whether the current delay amount can be continuously changed to compensate the phase difference, and detecting whether overflow or underflow exists in real time; if not, updating the current control signal based on the phase difference by the control module to adjust the current delay amount to update the feedback clock, and returning to the step S1; if so, randomly generating an updated control signal by the control module to set the current delay amount so that the DLL circuit is disengaged from the overflow or the underflow, and returning to the step S1; repeating the steps S1 through S2 until the external clock is phase aligned with the feedback clock. When the DLL circuit overflows or underflows, an updated delay amount can be set by randomly generating an updated control signal, a feedback clock can still be obtained in response to the control signal, and the locking process is restarted in time.

The coarse delay module comprises a plurality of delay chains, the delay chains comprise a plurality of delay units which are cascaded, and the current delay amount is based on the number of the delay units experienced by the internal clock of the DLL circuit; the method for detecting whether overflow or underflow exists in real time comprises the following steps: determining that the current delay amount needs to be increased or decreased continuously according to the phase difference; and acquiring the number of the delay units used currently through the control module, and judging whether the number of the delay units can be continuously changed to continuously increase or decrease the current delay amount.

The method for detecting the existence of the overflow comprises the following steps: if the current delay amount needs to be increased continuously and the number of the delay units used currently is the largest, the overflow is judged to exist.

The method of detecting the presence of the underflow is: if the current delay amount needs to be continuously reduced and the delay units which are currently used are minimum, judging that the underflow exists.

The control signal comprises a first control signal and a second control signal; the internal clock responds to the first control signal and goes through a plurality of delay units to obtain a first clock; the internal clock responds to the second control signal and goes through a plurality of delay units to obtain a second clock; disengaging the DLL circuit from the overflow or the underflow is by: keeping the current first control signal unchanged to keep the current first clock unchanged; randomly generating a new second control signal, and controlling the internal clock to update the second clock through a random number of delay units; updating the feedback clock based on the current first clock and the updated second clock.

Using the current first clock through the DLL circuit as a temporary clock for current output data before randomly generating the updated second control signal. When overflow or underflow of the DLL circuit is detected, the first clock is directly output to an external circuit after being delayed by the subsequent part of the DLL circuit and serves as a temporary clock of output data, a clock with the minimum error is provided for the output data before relocking and serves as the temporary clock before relocking is achieved, reading data is prevented from being interrupted at the moment, continuity of reading data of the DRAM is guaranteed, and instruction and data loss in time required by relocking is reduced.

The DLL circuit also comprises a duty ratio adjusting module connected with the input end of the coarse delay adjusting module and used for receiving an external clock, adjusting the duty ratio of the external clock and outputting the internal clock; the delay chain comprises a first branch chain and a second branch chain, wherein the first branch chain and the second branch chain are respectively provided with N delay units; the first clock is obtained by the following steps: the internal clock is delayed by the i delay units of the first branch chain to obtain a first clock, and i is more than or equal to 1 and less than or equal to N; the second clock is obtained by: the internal clock is delayed by j delay units of the second branched chain to obtain a second clock, and j is more than or equal to 1 and less than or equal to N; wherein N, i and j are positive integers; the process of determining whether to continue changing the number of delay cells to continue increasing or decreasing the current amount of delay includes determining whether the difference between i and j can continue increasing or decreasing.

The first clock is an odd frequency division signal; the second clock is an even frequency division signal.

The control signals further comprise fine tuning control signals; updating the feedback clock comprises: the fine adjustment delay module responds to the fine adjustment control signal, delays the first clock based on the phase difference of the first clock and the second clock, and obtains and outputs a delay clock; and accumulating the system fixed delay for the delay clock to obtain the feedback clock.

The method for obtaining the delay clock comprises the following steps: averaging the first clock and second clock phase difference into a number of delay steps based on a delay precision requirement; and accumulating and delaying the first clock by m delay steps to obtain the delay clock. The unit delay step length is equally divided by the fine adjustment delay module according to the requirement of specific delay precision, and the fraction accumulated delay amount of the delay step length is set by the fine adjustment control signal, so that the locking speed and precision are further improved.

Compared with the prior art, the invention has the main beneficial effects that:

1. according to the method for quickly re-locking the DLL circuit, disclosed by the invention, whether the DLL circuit overflows or underflows is detected in real time by judging whether the current delay amount can be continuously changed to compensate the phase difference, and the external clock and the feedback clock can be quickly aligned by correspondingly setting a control signal according to the detection result; the control signal is updated randomly without resetting the DLL circuit, and the normal phase locking state can be recovered in a short time, so that the phase alignment of the output clock and the input clock of the DRAM is ensured. By using the first clock to be directly output through the DLL circuit when overflow or underflow occurs, a clock with a minimum error is still provided for output data before relocking, transmission interruption is avoided, and instruction and data loss is greatly reduced.

2. The method for quickly re-locking the DLL circuit is very favorable for improving the working reliability of the DRAM, provides a practical and effective solution for breaking through the limitation of adverse effects caused by environmental factors such as temperature and the like on the equipment application of the integrated DRAM, and further promotes the deep application of the integrated circuit equipment in a complex environment.

Drawings

Fig. 1 is a schematic diagram of an exemplary DLL circuit synchronized clock of the present invention.

Fig. 2 is a block diagram of a DLL circuit according to a first embodiment of the present invention.

Fig. 3 is a simplified block diagram of a DLL circuit according to a first embodiment of the present invention.

Fig. 4 is a signal timing diagram of the DLL circuit in the normal phase-locked state according to the first embodiment of the present invention.

Fig. 5 is a schematic diagram of a basic structure of a delay chain module according to a first embodiment of the invention.

Fig. 6 is a schematic diagram of a delay chain according to a first embodiment of the present invention.

Fig. 7 is a timing diagram of the signals output by the fine delay module according to an embodiment of the invention.

Fig. 8 is a schematic diagram of a delay link when an underflow occurs according to an embodiment of the present invention.

Fig. 9 is a process diagram of a method for quickly relocking a DLL circuit according to an embodiment of the present invention.

Fig. 10 is a schematic diagram of a delay chain circuit when a DLL circuit is relocked according to a first embodiment of the present invention.

Fig. 11 is a schematic diagram of a delay link when overflow occurs in the second embodiment of the present invention.

Fig. 12 is a schematic diagram of the delay chain circuit when the DLL circuit is relocked according to the second embodiment of the present invention.

Detailed Description

The operations of the embodiments are depicted in the following embodiments in a particular order, which is provided for better understanding of the details of the embodiments and to provide a thorough understanding of the present invention, but the order is not necessarily one-to-one correspondence with the methods of the present invention, and is not intended to limit the scope of the present invention.

Example one

As shown in fig. 2, the DLL circuit of this embodiment includes a phase detection module, a control module, a duty ratio adjustment module DCC, a delay chain module delay _ line, and a fixed delay module delay _ replica. Wherein the communication connection of each part is the same as that of the conventional DLL circuit and is not expanded. After the external clock clk and the initial feedback clock clk _ fb are subjected to phase comparison by the phase discrimination module phase detect, a control module control makes a control strategy to control the duty ratio adjusting module DCC and the delay chain module delay _ line. In an exemplary case, the duty cycle adjustment module DCC adjusts the duty cycle of the external clock clk to 50% to obtain the internal clock. The external clock clk is delayed by the delay chain module delay _ line to obtain a delay clock clk _1, and the clk _1 is accumulated by the fixed delay module delay _ replica to obtain a system fixed delay updating feedback clock clk _ fb. For the convenience of understanding the gist of the present invention, the duty ratio adjusting module DCC is omitted, as shown in fig. 3, the delay chain portion in the DLL circuit structure of fig. 2 in fig. 3 may be simplified into a delay chain module delay _ line and a fixed delay module delay _ replica, and the expanded example provides the operation condition of the current delay amount. It should be noted that the above is simplified for convenience of explanation, and it cannot be considered that the DLL circuit structure of the present embodiment does not necessarily include the duty ratio adjustment module DCC. In the present embodiment, when the DLL circuit is normally locked, timing diagrams of the delay clock clk _1 output by the delay chain module delay _ line, the input external clock clk, and the feedback clock clk _ fb output by the DLL circuit when locked are shown in fig. 4. The analog delay chain of the fixed delay module delay _ replica is the amount of delay that the replica system carries itself, and it is affected by process drift, temperature, and other factors. For clarity of description, the delay amount is represented by the delay time in the present embodiment. In the application scenario of the embodiment, the temperature is positively correlated with the delay time of the fixed delay module delay _ replica. When the temperature rises, the delay time t _ rep of the fixed delay module becomes longer, and the total delay time t _ delay of the normal phase lock is fixed and unchanged, the delay time t _ line of the delay chain module delay _ line needs to be reduced to ensure that the DLL circuit works normally. However, when the temperature rises beyond a certain range, it is necessary to reduce t _ line to be less than the minimum delay time that the delay chain module delay _ line can provide, and at this time, t _ line cannot be reduced any more, and the DLL circuit cannot lock the phase normally. This embodiment refers to this out-of-lock condition as an underslow. On the contrary, when the temperature decreases, the delay time t _ rep of the fixed delay module delay _ replica is correspondingly shortened, resulting in that the delay time t _ line required by the delay chain module delay _ line continuously increases. When the required delay time t _ line is increased to the maximum delay time that can be provided by the delay chain module delay _ line, the t _ line cannot be increased continuously, the DLL circuit cannot perform normal phase locking, and this unlocking condition is referred to as overflow in this embodiment. In the DRAM memory, the external clock clk is a command clock of the CPU, and the feedback clock clk _ fb is a clock of the output data. When overflow or underflow occurs, the DLL circuit does not have normal phase locking, the external clock clk and the current feedback clock clk _ fb cannot keep the same phase, and the external clock clk and the current feedback clock clk _ fb need to be quickly separated from the overflow or underflow and relocked to ensure that the CPU can normally read the data of the DRAM.

Fig. 5 shows a delay _ line and a signal flow of the delay chain module of this embodiment. The internal clock clk _ coarse input to the coarse delay module coarse delay generates the first clock and the second clock input to the fine delay module fine delay in response to the first control signal and the second control signal output from the control module control. The delay chain as illustrated in fig. 6 includes a first branch a and a second branch B having N delay units, respectively. I is more than or equal to 1 and less than or equal to N, and j is more than or equal to 1 and less than or equal to N; where N, i and j are positive integers. The control module control in this embodiment includes a detection unit and a first counter, a second counter, and a third counter. When there is no underflow or overflow, the control module controls to output a command to increase or decrease the current delay amount depending on the magnitude of the current phase difference. An exemplary first control signal is an odd control code cnt _ odd,; the second control signal is an even control code cnt _ even. The fine control signal is directly input to the fine delay module fine delay, and includes a count control code cnt _ fine. In this embodiment, the first clock clk _ odd is an odd-numbered frequency-divided signal generated after the internal clock clk _ coarse passes through i delay units; the second clock clk _ even is an even-numbered divided signal generated after the internal clock clk _ coarse passes through j delay units. The first clock clk _ odd and the second clock clk _ even are input together to the fine delay module fine delay. As shown in fig. 6, each delay unit is composed of three nand gates, and the output ends of the two nand gates are respectively connected to the first input end and the second input end of the third nand gate. The delay unit may have other structures such as an inverter, a transmission gate, and other circuit structures for implementing the delay function, and is not limited. The delay cells of the example of fig. 6 have a total of 18, i.e. an example value of N is 9. Generating a first clock clk _ odd with at most 9 delay cells; the second clock clk _ even can be generated using up to 9 delay cells. The number of delay units in the coarse delay module coarse delay and the maximum value of i and j are not limited, and may be set according to the actual application or the specific product design parameters. In this embodiment, the numbers of the nand gates experienced by the first clock clk _ odd and the second clock clk _ even are both even numbers or both odd numbers. The first clock clk _ odd and the second clock clk _ even have a phase difference. In this embodiment, the fine adjustment control signal further includes a frequency division signal, which is used to perform frequency division according to the actual requirement of delay precision, and perform a plurality of equal divisions on the phase difference between the first clock clk _ odd and the second clock clk _ even for further fine adjustment of the delay amount, where each equal division is a delay step (the greater the number of equal divisions, the smaller the single delay amount of the fine adjustment delay, the higher the precision of the delay). The phase difference between the first clock clk _ odd and the second clock clk _ even is divided into n equal parts, one delay step is one n times of the phase difference, and the fine control signal cnt _ fine is input into the fine delay module fine delay to select to delay the input first clock clk _ odd by m delay steps, that is, to assign a value to m. The delay clock clk _1 output by the final delay chain module delay _ line is obtained by adding m delay steps to the first clock clk _ odd. As shown in fig. 7, in the exemplary case, an 1/8-ratio divider is used, n being 8 and m being 2. The result of the fine-tuning delay is to add two delay steps on the basis of the first clock clk odd.

In the DLL circuit locking process of this embodiment, the control module control determines whether to increase or decrease the delay amount that has been currently provided according to the magnitude of the acquired phase difference, and the first control signal cnt _ odd and the second control signal cnt _ even generated accordingly determine to use several delay units in the coarse delay module coarse delay, i.e., assign values to i and j. And the number of used delay units in the delay chain passed by the first clock clk _ odd and the second clock clk _ even is alternately increased or decreased according to the first control signal cnt _ odd and the second control signal cnt _ even. In this embodiment, the delay chain when the underflow occurs is as shown in fig. 8, after comparing the phases of the external clock clk and the current feedback clock clk _ fb, the control module issues a command to continue to reduce the current delay amount, but at this time, the delay chain has been involved with the least delay units, i.e. both i and j are already at the minimum value of 1. It is known that the number of delay units used in the first branch a experienced by the first clock clk _ odd and the second branch B experienced by the second clock clk _ even cannot be continuously and alternately reduced, that is, the difference between i and j cannot be continuously reduced. The phase difference between the first clock clk _ odd and the second clock clk _ even as illustrated in fig. 8 is already minimized, and the delay amount of the delayed clock clk _1 cannot be continuously reduced, that is, the t _ line cannot be reduced. The detection unit detects that the underflow occurs at this time. As shown in fig. 9, an exemplary method of quickly relocking a DLL circuit includes: step S1, acquiring the phase difference between the current external clock clk and the feedback clock clk _ fb and the current delay amount provided by the coarse delay module coarse delay through a control module control. And S2, judging whether the current delay amount can be continuously changed to compensate the phase difference or not, and detecting whether underflow exists or not in real time. Respectively carrying out different operations: if not, updating the current control signal based on the phase difference through the control module control to adjust the current delay amount updating feedback clock, and returning to the step S1; if so, a control module randomly generates a new control signal to set the current delay amount so that the DLL circuit is out of underflow, and returns to step S1. Steps S1 through S2 are repeated until the external clock clk is phase aligned with the feedback clock clk _ fb. The method for rapidly relocking the DLL circuit of the present embodiment can be implemented by VLSI design, combining with a corresponding algorithm, and designing the control module by using a digital ASIC flow. The specific application is realized by analog circuit design, and is not limited.

The control module control keeps the current first control signal cnt _ odd unchanged when the underflow occurs, so that the current first clock clk _ odd remains unchanged. The control module control randomly sets a new second control signal cnt _ even to control the internal clock clk _ coarse to pass through a random number of delay units to obtain an updated second clock clk _ even. As shown in fig. 10, the random number in the present embodiment is 5 delay cells, and the random number is larger than the minimum value of j, but is not limited. The new second clock clk _ even and the unchanged current first clock clk _ odd are input into the fine delay module fine delay to generate an updated delay clock clk _1, which outputs an updated feedback clock clk _ fb after passing through the fixed delay module delay _ replica, the phase detection module phase detect performs phase comparison based on the updated feedback clock clk _ fb and the external clock clk, and the control module control updates the first control signal and the second control signal according to the phase difference at this time to restart the DLL circuit phase locking process until the external clock clk is aligned with the final feedback clock clk _ fb in phase. In this embodiment, the first control signal is an odd control code cnt _ odd, and the second control signal is an even control code cnt _ even, for example, so as to facilitate understanding of the present invention, in some implementation cases, the delay link structure of the coarse delay module coarse delay and the circuit structure of the fine delay module fine delay are set correspondingly according to practical applications and product designs, and there may be more corresponding counters or signals generated by the counters; the control signal may be a digital signal or an analog signal, and is set according to the DLL circuit design of a specific application, without limitation.

Example two

As shown in fig. 11, the embodiment is an example of a method for quickly relocking a DLL circuit when overflow occurs. In step S2, it is determined whether the current delay amount can be continuously changed to compensate for the phase difference, and whether there is an overflow is detected in real time. When the phases of the external clock clk and the feedback clock clk _ fb input to the DLL circuit are compared, the control module control determines that a command for increasing the delay needs to be issued, and the detection unit determines that the most delay units in the first branch chain a and the second branch chain B are used to participate in the delay chain. I.e. to determine that the current values of i and j, respectively, have reached their maximum values. Then the occurrence of overflow of the DLL circuit at this time is detected. As shown in fig. 11, the current first clock clk _ odd is generated after the internal clock clk _ coarse passes through 9 delay units, and the second clock clk _ even is obtained after the internal clock clk _ coarse passes through 9 delay units, so that the current delay amount cannot be increased any more. As shown in fig. 12, at this time, the control module control keeps the current first control signal cnt _ odd unchanged, so that the current first clock clk _ odd remains unchanged. On one hand, the clock output after the current first clock clk _ odd passes through the fine delay module fine delay and then passes through the fixed delay module delay _ replica is used as the clock for outputting data, so that the normal reading and writing of data of the current DRAM is ensured, and instructions and data are not lost. On the other hand, the control module control sets a new second control signal cnt _ even to control the internal clock clk _ coarse to pass through a random number of delay units to obtain an updated second clock clk _ even. The random number in this embodiment is 5 delay units, and the random number is smaller than the maximum value of j, and is not limited. The updated second clock clk _ even and the unchanged current first clock clk _ odd are input into the fine delay module fine delay to generate an updated delay clock clk _1, the updated delay clock clk _1 is output after passing through the fixed delay module delay _ replica, the phase detection module phase detect performs phase comparison based on the updated feedback clock clk _ fb and the external clock clk, and the control module control obtains the first control signal and the second control signal according to the phase difference at this time to restart the phase locking process of the DLL circuit until the external clock clk is in the same phase as the final feedback clock clk _ fb.

In this embodiment, the specific configuration of the control module is the detecting unit and the counting unit, and the control signal is taken as the counter signal to illustrate the specific application of the present invention. In some embodiments, the control module control may be configured by other specific circuits, and may further include circuit elements such as an encoder, a buffer, and a logic unit, and the control signal is not limited to a counter signal, such as a current signal, a voltage signal, or other analog signal. In this embodiment, a method for detecting whether the control module is in the overflow state in real time is exemplified, and in some implementation cases, other methods may be used in combination with a specific circuit structure, for example, whether two phase comparison results are different is determined by comparing a current phase difference with a previous time phase difference, so as to detect whether the DLL circuit is in the normal operating state, which is not limited.

For clarity of description, the use of certain conventional and specific terms and phrases is intended to be illustrative and not restrictive, but rather to limit the scope of the invention to the particular letter and translation thereof. It is further noted that, herein, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The structure and operation of the present invention are explained by applying specific examples, and the above description of the embodiments is only used to help understanding the method and core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims

1. A method for quickly relocking a DLL circuit, the DLL circuit comprising a control module and a delay chain module; the delay chain module comprises a coarse adjustment delay module and a fine adjustment delay module which are connected in series; the method is characterized in that: the method comprises the following steps:

s1, acquiring a phase difference between a current external clock and a DLL circuit feedback clock and a current delay amount provided by a coarse delay module through a control module;

s2, judging whether the current delay amount can be continuously changed to compensate the phase difference, and detecting whether overflow or underflow exists in real time;

if not, updating the current control signal based on the phase difference by the control module to adjust the current delay amount to update the feedback clock, and returning to the step S1; if so, randomly generating an updated control signal by the control module to set the current delay amount so that the DLL circuit is disengaged from the overflow or the underflow, and returning to the step S1;

repeating the steps S1 through S2 until the external clock is phase aligned with the feedback clock.

2. The method of fast relock a DLL circuit of claim 1, wherein: the coarse delay module comprises a plurality of delay chains, the delay chains comprise a plurality of delay units which are cascaded, and the current delay amount is based on the number of the delay units experienced by the internal clock of the DLL circuit; the method for detecting whether overflow or underflow exists in real time comprises the following steps:

determining that the current delay amount needs to be increased or decreased continuously according to the phase difference;

and acquiring the number of the delay units used currently through the control module, and judging whether the number of the delay units can be continuously changed to continuously increase or decrease the current delay amount.

3. The method of fast relock a DLL circuit of claim 2, wherein: the method for detecting the existence of the overflow comprises the following steps: if the current delay amount needs to be increased continuously and the number of the delay units used currently is the largest, the overflow is judged to exist.

4. The method of fast relock a DLL circuit of claim 2, wherein: the method of detecting the presence of the underflow is: if the current delay amount needs to be continuously reduced and the delay units which are currently used are minimum, judging that the underflow exists.

5. The method of quickly relocking a DLL circuit as claimed in any one of claims 2 to 4, wherein: the control signal comprises a first control signal and a second control signal; the internal clock responds to the first control signal and goes through a plurality of delay units to obtain a first clock; the internal clock responds to the second control signal and goes through a plurality of delay units to obtain a second clock;

disengaging the DLL circuit from the overflow or the underflow is by:

keeping the current first control signal unchanged to keep the current first clock unchanged;

randomly generating a new second control signal, and controlling the internal clock to update the second clock through a random number of delay units;

updating the feedback clock based on the current first clock and the updated second clock.

6. The method of fast relock a DLL circuit of claim 5, wherein: using the current first clock through the DLL circuit as a temporary clock for current output data before randomly generating the updated second control signal.

7. The method of fast relock a DLL circuit of claim 5, wherein: the DLL circuit also comprises a duty ratio adjusting module connected with the input end of the coarse delay adjusting module and used for receiving an external clock, adjusting the duty ratio of the external clock and outputting the internal clock; the delay chain comprises a first branch chain and a second branch chain, wherein the first branch chain and the second branch chain are respectively provided with N delay units;

the first clock is obtained by the following steps: the internal clock is delayed by the i delay units of the first branch chain to obtain a first clock, and i is more than or equal to 1 and less than or equal to N;

the second clock is obtained by: the internal clock is delayed by j delay units of the second branched chain to obtain a second clock, and j is more than or equal to 1 and less than or equal to N;

wherein N, i and j are positive integers; the process of determining whether to continue changing the number of delay cells to continue increasing or decreasing the current amount of delay includes determining whether the difference between i and j can continue increasing or decreasing.

8. The method of fast relock a DLL circuit of claim 7, wherein: the first clock is an odd frequency division signal; the second clock is an even frequency division signal.

9. The method of fast relock a DLL circuit of claim 8, wherein: the control signals further comprise fine tuning control signals; updating the feedback clock comprises: the fine adjustment delay module responds to the fine adjustment control signal, delays the first clock based on the phase difference of the first clock and the second clock, and obtains and outputs a delay clock; and accumulating the system fixed delay for the delay clock to obtain the feedback clock.

10. The method of fast relock a DLL circuit of claim 9, wherein: the method for obtaining the delay clock comprises the following steps: averaging the first clock and second clock phase difference into a number of delay steps based on a delay precision requirement; and accumulating and delaying the first clock by m delay steps to obtain the delay clock.