CN113886041A - Access management method and device for interrupt event in CPLD - Google Patents
Access management method and device for interrupt event in CPLD Download PDFInfo
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Abstract
The invention provides an access management method and device for interrupt events in a CPLD. The method comprises the following steps that an interrupt register in the CPLD operates the access management of each emergency in an interrupt register list mode, the interrupt register sequences the interrupt register list, the interrupt register is mapped to an upper layer and finally summarized to the topmost layer, the CPLD monitors a bit of 1 in the interrupt register and converts the bit into a hexadecimal form, and an interrupt address register is formed by judging an interrupt address generated in the interrupt register; the CPLD sends an interrupt signal to the CPU, and the CPU processes the interrupt signal by adopting an interrupt processing mechanism. In this way, the interrupt address can be inquired quickly, the interrupt trace can be circulated, when a plurality of interrupts occur simultaneously, the high-priority interrupts can be processed according to the logic sequence, the interrupt processing time is reduced, and the CPU processing efficiency is improved.
Description
Technical Field
Embodiments of the present invention generally relate to the field of communications, and in particular, to an access management method and apparatus for an interrupt event.
Background
In the current circuit design, the method of inquiring and processing the interrupt mainly adopts a time-sharing control method, each peripheral device provides one or more state information, the CPU successively reads and detects the state information of each peripheral device, if the peripheral device requests the service, the peripheral device is served, and then the state information is cleared. Otherwise, skipping, inquiring the state of the next peripheral device, and after the inquiry of each peripheral device is finished, returning from the head inquiry until a stop command is sent. The CPU needs to continuously read the status words and detect the status words, and whether the peripheral equipment has service requests or not, the peripheral equipment needs to inquire one by one, and the inquiry for many times occupies the time of the CPU and is mostly invalid.
When the peripheral equipment needs to request service, an interrupt request is sent to the CPU, the CPU responds to the interrupt of the peripheral equipment, stops executing the current program, transfers to execute a program served by the peripheral equipment, and returns to execute the original program after the interrupt processing is finished. The utilization rate of the CPU can be greatly improved by utilizing the interrupt mode to transmit data, but in the interrupt mode, the interrupt still needs to be inquired by the CPU execution program. Since a plurality of peripheral devices share one interrupt request, the interrupt service routine must be queried again, which wastes much interrupt processing time of the CPU and needs to assign an interrupt request number to each peripheral device.
This method improves the utilization rate of the CPU, but reduces the work efficiency of the CPU, wastes extra time in the interrupt handler of the CPU, and cannot respond to the interrupt request of the peripheral device at the fastest speed.
Disclosure of Invention
According to the embodiment of the invention, the invention provides an access management method and device for interrupt events in a CPLD.
In a first aspect of the present invention, a method for access management with respect to interrupt events in a CPLD is provided. The method comprises the following steps:
s01: an interrupt register in the CPLD operates the access management of each emergency event in the manner of an interrupt register list;
s02: sequencing an interrupt register list by an interrupt register in the CPLD;
s03: the CPLD monitors bit of 1, converts the bit into hexadecimal form, judges the interrupt address in the interrupt register, and forms an interrupt address register
S04: the CPLD sends an interrupt signal to the CPU, and the CPU processes the interrupt signal by adopting an interrupt processing mechanism.
Further, the said interrupt register orders the interrupt register list, including: the interrupt register sorts the interrupt register list by priority, with lower addresses being of higher priority, as shown in table 1.
TABLE 1
Further, the address of the interrupt register includes:
l1: address X + a + 1X +80*a+80
L2: the address X + (a +1) × 8+ (b +1) ═ X +81*a+80*b+81+80
L3: address X + [ (a +1) × 8+ (b +1)]*8+(c+1)＝X+82*a+81*b+80*c+82+81+80
L4: the address X + { [ (a +1) × 8+ (b +1) ] × 8+ (c +1) } × 8+ (d +1)
＝X+83*a+82*b+81*c+80*d+83+82+81+80
..........
Ln, address X +8n-1*a+8n-2*b+8n-3*c+...8n-n*z+8n-1+8n-2+8n-3+...+8n-n
＝X+8n-1*a+8n-2*b+8n-3*c+...8n-n*z+(8n-1)/7
Wherein: wherein a, b, c, d
The minimum number of interrupt registers required in total, as shown in table 2:
TABLE 2
Wherein: n is the number of interrupt events; n is the number of register layers, 8n-1<N<8n。
[ N ] integer functions, also known as Gaussian functions;
l1: interrupt level 1
L2: interrupt level 2
L3: interrupt level 3
……
Ln: interrupt level is n
Can simplify:
the total number of interrupt registers is N + [ N/8 ]n-1]+[N/8n-2]+…+[N/8n-(n-1)]
＝n+[(N/8)*(1-1/8n)/(1-1/8)]
＝n+[(N/7)*(1-1/8n)]
≈n+[N/7]
Further, the interrupt handling mechanism includes:
s041: the CPU receives an interrupt signal sent by the CPLD and responds to the interrupt, and when the interrupt is processed, the shielding signal is pulled down to indicate that the CPU does not receive new interrupt any more;
s042: in the interrupt processing process of the CPU, the CPLD keeps corresponding interrupt and does not change the content of an interrupt address register;
s043: after the CPU processes the interrupt event, the CPU pulls the shielding signal high, and the CPU can process the next interrupt request sent by the CPLD.
Further, after the CPU processes the interrupt event in S043, the contents of the interrupt address register in the CPLD are cleared.
In a second aspect of the present invention, an access management device for interrupt events in a CPLD is provided. The device includes:
a register module: the system comprises an interrupt register module and an interrupt address register;
the interrupt register is used to operate the access management of each emergency in the manner of an interrupt register list, and to order the interrupt register list, as shown in table 3;
TABLE 3
The interrupt address register is used for mapping the interrupt register to the upper layer and finally summarizing the interrupt register to the topmost layer, the CPLD monitors bit of 1 in the interrupt register and converts the bit into a hexadecimal form, and the interrupt address generated in the interrupt register is judged to form an interrupt address register;
a CPU module: and the system is used for receiving the interrupt signal sent by the CPLD and processing the interrupt signal by adopting an interrupt processing mechanism.
Further, the address of the interrupt register includes:
l1: address X + a + 1X +80*a+80
L2: the address X + (a +1) × 8+ (b +1) ═ X +81*a+80*b+81+80
L3: address X + [ (a +1) × 8+ (b +1)]*8+(c+1)＝X+82*a+81*b+80*c+82+81+80
L4: the address X + { [ (a +1) × 8+ (b +1) ] × 8+ (c +1) } × 8+ (d +1)
＝X+83*a+82*b+81*c+80*d+83+82+81+80
..........
Ln, address X +8n-1*a+8n-2*b+8n-3*c+...8n-n*z+8n-1+8n-2+8n-3+...+8n-n
＝X+8n-1*a+8n-2*b+8n-3*c+...8n-n*z+(8n-1)/7
Wherein: a, b, c, d
The minimum number of interrupt registers required in total, as shown in table 4:
TABLE 4
Wherein: n is the number of interrupt events; n is the number of register layers, 8n-1<N<8n。
[ N ] integer functions, also known as Gaussian functions;
l1: interrupt level 1
L2: interrupt level 2
L3: interrupt level 3
……
Ln: interrupt level is n
Can be simplified into:
the total number of interrupt registers is N + [ N/8 ]n-1]+[N/8n-2]+…+[N/8n-(n-1)]
＝n+[(N/8)*(1-1/8n)/(1-1/8)]
＝n+[(N/7)*(1-1/8n)]
≈n+[N/7]
Further, the interrupt handling mechanism includes:
s1: the CPU receives an interrupt signal sent by the CPLD and responds to the interrupt, and when the interrupt is processed, the shielding signal is pulled down to indicate that the CPU does not receive new interrupt any more;
s2: in the interrupt processing process of the CPU, the CPLD keeps corresponding interrupt and does not change the content of an interrupt address register;
s3: after the CPU processes the interrupt event, the CPU pulls the shielding signal high, and the CPU can process the next interrupt request sent by the CPLD.
Further, in S3, after the CPU finishes processing the interrupt event, the contents of the interrupt address register in the CPLD are cleared.
The above-mentioned english abbreviation:
a CPU: central processing unit, Central processing unit
CPLD: complex programmable logic device
The invention can quickly inquire the interrupt address and make the interrupt trace circulated, and can process the high-priority interrupt according to the logic sequence when a plurality of interrupts occur simultaneously, thereby reducing the interrupt processing time and improving the CPU processing efficiency.
It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of any embodiment of the invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of various embodiments of the present invention will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. Wherein:
fig. 1 shows a flow chart of a method of access management with respect to interrupt events in a CPLD according to an embodiment of the invention;
FIG. 2 illustrates a flow diagram of an interrupt handling mechanism according to an embodiment of the invention;
FIG. 3 shows a hardware connection block diagram according to an embodiment of the invention;
fig. 4 shows a block diagram of an access management device with respect to an interrupt event in a CPLD according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In fig. 3, 48 gigabit optical modules are supported on the switch, each optical module having 3 interrupts: SFP _ PRESENT _ N, SFP _ TX _ FAULT, SFP _ RX _ LOS. And (4) connecting 48 × 3-144 interrupts into the CPLD.
Wherein according to the SFF-8431 specification:
tx _ Fault: tx _ Fault is a module output that, when higher, indicates that the module transmitter detected a Fault condition related to laser operation or safety. If Tx _ Fault is not implemented, the Tx _ Fault touch signal will be held low by the module and may be connected to a ground signal within the module. The Tx _ Fault output is an open drain/collector that should be pulled to Vcc _ Host in the Host, with resistances in the range of 4.7k Ω to 10k Ω.
2.MoD_ABS
And the Mod _ ABS is connected with an optical module signal transmitting ground level or an optical module signal receiving ground level in the SFP + module. The host may pull this contact to the main voltage with a 4.7k omega to 10k omega resistor. When the SFP + module is not in the host slot, Mod _ ABS is considered "high". In SFP MSA (info-8074i), this contact has the same function, but is called MOD _ DEFO.
3.Rx_LOS
Rx LOS high indicates that the optical signal level is below the relevant standard. Rx _ LOS is an open drain/collector output but can also be an input to the monitoring circuitry in the module. A nominal 3.3V mains voltage using resistor should have a resistance in the range 4.7k omega to 10k omega and a nominal 2.5V mains voltage using resistor should have a resistance in the range 4.7k omega to 7.2k omega.
Allocate the relevant interrupt registers, see table 5:
TABLE 5
Registers are then allocated for detection of the interrupt input pin and interrupt enable, see table 6:
TABLE 6
The interrupt address register is set to 0x7 f.
Next, de-jittering is carried out on the signals to prevent interruption and false triggering:
then, an array is generated for storing the interrupt register list, and 72 registers are generated for storing the interrupt registers:
--Register Definition
--type describing the byte array consisting of 8byte matrix array
type matrix_int is array(72downto 0)of std_logic_vector(7downto 0)；
signal Int:matrix_int；
144 interrupt signals are monitored, but when the signals change, interrupts are generated:
with interrupt generation, the interrupt register in the CPLD operates the access management for each incident in the manner of an interrupt register list.
The interrupt register list is sorted with lower addresses and higher priority, see table 7.
TABLE 7
The interrupt register maps to the upper layer and finally gathers to the topmost layer, and the CPLD monitors bit of 1:
then converting the address into a hexadecimal form, and judging the address generating the interrupt in the interrupt register:
Int_num<＝64*a+8*b+c；
Reg_0x7f<＝conv_std_logic_vector(Int_num,8)；
the CPLD sends an interrupt signal to the CPU, the CPU receives the interrupt signal and responds to the interrupt, and when the interrupt with the interrupt number of 4 is processed, the shielding signal is pulled down to indicate that the CPU does not receive new interrupt any more;
in the interrupt processing process of the CPU, the CPLD keeps corresponding interrupt and does not change the content of an interrupt address register;
after the CPU finishes processing the interrupt event, the CPLD clears the interrupt to clear the content in the interrupt address register:
the CPU pulls the shielding signal high to indicate that the next interrupt can be received, the CPLD sends a next interrupt request to the CPU, and the CPU responds to the interrupt after receiving and pulls the shielding signal low.
The interrupt address register updates the content in real time according to the shielding signal provided by the CPU, and the CPU reads the interrupt number in the CPLD through the I2C interface and executes the corresponding interrupt operation.
Based on the same inventive concept, the invention also provides an access management device related to the interrupt event in the CPLD. The implementation of the device can be referred to the implementation of the method, and repeated details are not repeated. As shown in fig. 4, the apparatus 100 includes:
the register module 101: includes an interrupt register module 1011 and an interrupt address register module 1012;
the interrupt register module is used for operating the access management of each emergency in an interrupt register list mode and sequencing the interrupt register list;
the interrupt address register module is used for mapping the interrupt register to the upper layer, and finally summarizing the interrupt register to the topmost layer, the CPLD monitors bit of 1 in the interrupt register, and then converts the bit into a hexadecimal form, and the interrupt address register is formed by judging the interrupt address generated in the interrupt register. The CPU module 102: and the system is used for receiving the interrupt signal sent by the CPLD and processing the interrupt signal by adopting an interrupt processing mechanism.
The access management device for the interrupt event in the CPLD can quickly inquire the interrupt address and enable the interrupt trace to be circulated, and can process high-priority interrupts according to a logic sequence when a plurality of interrupts occur simultaneously, thereby reducing the interrupt processing time and improving the CPU processing efficiency.
While the spirit and principles of the invention have been described with reference to several particular embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, nor is the division of aspects, which is for convenience only as the features in such aspects may not be combined to benefit. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
The limitation of the protection scope of the present invention is understood by those skilled in the art, and various modifications or changes which can be made by those skilled in the art without inventive efforts based on the technical solution of the present invention are still within the protection scope of the present invention.
Claims (8)
1. A method for access management with respect to interrupt events in a CPLD, the method comprising:
s01: an interrupt register in the CPLD operates the access management of each emergency event in the manner of an interrupt register list;
s02: sequencing an interrupt register list by an interrupt register in the CPLD;
s03: the interrupt register in the CPLD is mapped to the upper layer and finally gathered to the topmost layer, the CPLD monitors the bit of 1 in the interrupt register and then converts the bit into a hexadecimal form, and the interrupt address generated in the interrupt register is judged to form an interrupt address register.
S04: the CPLD sends an interrupt signal to the CPU, and the CPU processes the interrupt signal by adopting an interrupt processing mechanism.
2. The method of claim 1, wherein the interrupt register of S02 orders the interrupt register list according to priority, and the lower the address, the higher the priority.
3. The method according to claim 1, wherein the interrupt handling mechanism of S04 comprises:
s041: the CPU receives the interrupt signal sent by the CPLD and responds to the interrupt, and when the interrupt is processed, the shielding signal is pulled down, so that the CPU does not receive new interrupt any more;
s042: in the interrupt processing process of the CPU, the CPLD keeps corresponding interrupt and does not change the content of an interrupt address register;
s043: and after the CPU processes the interrupt event, the CPU pulls the shielding signal high, and the CPU can process the next interrupt request sent by the CPLD.
4. The access management method for interrupt events in a CPLD according to claim 3, characterized in that after the CPU processes the interrupt event in S043, the contents of the interrupt address register in the CPLD are cleared.
5. An access management device for an interrupt event in a CPLD, the device comprising:
a register module: the system comprises an interrupt register module and an interrupt address register;
the interrupt register is used for operating the access management of each emergency in the mode of an interrupt register list and sequencing the interrupt register list;
the interrupt address register is used for mapping the interrupt register to the upper layer and finally summarizing the interrupt register to the topmost layer, the CPLD monitors bit of 1 in the interrupt register and converts the bit into a hexadecimal form, and the interrupt address generated in the interrupt register is judged to form an interrupt address register;
a CPU module: and the system is used for receiving the interrupt signal sent by the CPLD and processing the interrupt signal by adopting an interrupt processing mechanism.
6. The device of claim 5, wherein the interrupt register lists interrupt registers in a prioritized order, with lower addresses having higher priority.
7. The device as claimed in claim 5, wherein the interrupt handling mechanism comprises:
s1: the CPU receives the interrupt signal sent by the CPLD and responds to the interrupt, and when the interrupt is processed, the shielding signal is pulled down, so that the CPU does not receive new interrupt any more;
s2: in the interrupt processing process of the CPU, the CPLD keeps corresponding interrupt and does not change the content of an interrupt address register;
s3: after the CPU processes the interrupt event, the CPU pulls the shielding signal high, and the CPU can process the next interrupt request sent by the CPLD.
8. The device of claim 7, wherein the interrupt address register in the CPLD is cleared after the CPU processes the interrupt event in S3.
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