CN113885831A - Storage and calculation integrated circuit based on mixed data input, chip and calculation device - Google Patents
Storage and calculation integrated circuit based on mixed data input, chip and calculation device Download PDFInfo
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
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Abstract
The embodiment of the disclosure discloses a save and calculate integrative circuit, chip, calculating device based on mixed data input, wherein, this circuit includes: the device comprises a storage calculation unit array and a mixed data input unit array; the mixed data input unit in the mixed data input unit array comprises a calculation data input subunit, a storage data input subunit, a data switching subunit, a data input port and a data switching signal input port; the storage data input subunits are connected with the corresponding data storage subunits, and the calculation data input subunits are connected with the corresponding calculation subunits; the data switching subunit is used for inputting the data received by the data input port into the data storage subunit or the calculation subunit according to the data switching signal input by the data switching signal input port. Compared with the traditional scheme that the storage data input unit and the calculation data input unit are separately arranged, the embodiment of the disclosure reduces the area of circuit layout by arranging the mixed data input unit.
Description
Technical Field
The disclosure relates to the technical field of computers, in particular to a storage and calculation integrated circuit, a chip and a calculation device based on mixed data input.
Background
The storage and calculation integration is a storage and calculation combined design integrating a static random access memory and a calculation module, and generally comprises a storage structure and a multiplication and addition structure. Compared with the traditional memory, the integrated memory has a port for writing the stored data and a port for inputting data multiplied by the stored data, and the port is responsible for transmitting the input data to the storage calculation unit for calculation.
The existing implementation scheme is that a storage data writing port and an input port for operation data are separately designed, and the input port for operation data is often as many as the number of word lines of a memory, so that the design of integrated storage has more ports than that of the traditional memory, the area of the integrated storage design is increased, and the routing of the butt joint input port when the integrated storage design is used outside is obviously increased.
Disclosure of Invention
An embodiment of the present disclosure provides a storage and computation integrated circuit based on hybrid data input, the circuit including: the mixed data input unit array comprises a storage calculation unit array and a mixed data input unit array, wherein the storage calculation unit array comprises a first preset number of storage calculation unit groups, and the storage calculation units in each storage calculation unit group correspond to the mixed data input units in the mixed data input unit array one by one; the mixed data input unit in the mixed data input unit array comprises a calculation data input subunit, a storage data input subunit, a data switching subunit, a data input port and a data switching signal input port; the storage data input subunit is connected with the data storage subunit included by the corresponding storage calculation unit, and the calculation data input subunit is connected with the calculation subunit included by the storage calculation unit in the corresponding storage calculation unit group; the data switching subunit is used for inputting the data received by the data input port into the data storage subunit or the calculation subunit according to the data switching signal input by the data switching signal input port.
In some embodiments, the calculation subunit includes a multiplier for multiplying the data in the corresponding data storage subunit and calculation subunit.
In some embodiments, the circuit further comprises a main controller for adjusting a current storage mode, wherein the storage mode comprises a storage mode and a calculation mode, and in the storage mode, the main controller sends the first switching signal to the data switching signal input port; in a calculation mode, the main controller sends a second switching signal to the data switching signal input port; the first switching signal is used for indicating that the data received by the current data input port is input into the corresponding storage data input subunit; the second switching signal is used for indicating that the data received by the current data input port is input into the corresponding calculation data input subunit.
In some embodiments, the circuit further comprises an address decoder; the main controller is also used for acquiring a data address to be input and sending the data address to be input to the address decoder; the address decoder is used for determining a target storage calculation unit group from a first preset number of storage calculation unit groups according to the data address to be input; the main controller is also used for sending the data to be input to the target storage computing unit group through a data input port included in a mixed data input unit in the mixed data input unit array.
In some embodiments, the circuit further comprises an adder array for adding the calculation results input from the first preset number of memory calculation unit groups to obtain an accumulated result.
In some embodiments, the adder array includes a second predetermined number of adder groups, the second predetermined number of adder groups are sequentially connected in a cascade manner, and input ends of adders included in a first-stage adder group of the second predetermined number of adder groups are respectively connected to corresponding storage calculation unit groups.
In some embodiments, the circuit further includes a shift accumulator, where the shift accumulator is configured to shift and accumulate at least two values output by the adder array in sequence by corresponding bits to obtain an accumulation result.
According to another aspect of the disclosed embodiments, there is provided a chip including the above-mentioned memory integrated circuit based on hybrid data input.
According to another aspect of the embodiments of the present disclosure, there is provided a computing device including the above chip.
According to the integrated circuit, the chip and the computing device based on the mixed data input, the input ports of the computing data and the input ports of the storage data are integrated into one mixed data input unit, the number of the input ports of the integrated circuit is reduced to be the same as that of the input ports of a traditional memory with only a storage function, and therefore the consumption of routing resources caused by the connection and routing of the inside and the outside of the integrated circuit and the data input ports is reduced. By combining the calculation data input subunit and the storage data input subunit, compared with the conventional scheme that the storage data input unit and the calculation data input unit are separately arranged, the embodiment of the disclosure reduces the area of the circuit layout by arranging the mixed data input unit.
The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail embodiments of the present disclosure with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. In the drawings, like reference numbers generally represent like parts or steps.
Fig. 1 is a schematic diagram of a prior art integrated circuit.
Fig. 2 is a schematic structural diagram of a hybrid data input-based storage integrated circuit according to an exemplary embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of a hybrid data input unit according to an exemplary embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of an adder array according to an exemplary embodiment of the present disclosure.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the embodiments of the present disclosure and not all embodiments of the present disclosure, with the understanding that the present disclosure is not limited to the example embodiments described herein.
It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
It will be understood by those of skill in the art that the terms "first," "second," and the like in the embodiments of the present disclosure are used merely to distinguish one element from another, and are not intended to imply any particular technical meaning, nor is the necessary logical order between them.
It is also understood that in embodiments of the present disclosure, "a plurality" may refer to two or more and "at least one" may refer to one, two or more.
It is also to be understood that any reference to any component, data, or structure in the embodiments of the disclosure, may be generally understood as one or more, unless explicitly defined otherwise or stated otherwise.
In addition, the term "and/or" in the present disclosure is only one kind of association relationship describing an associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the former and latter associated objects are in an "or" relationship.
It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and the same or similar parts may be referred to each other, so that the descriptions thereof are omitted for brevity.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Summary of the application
Compared with the traditional memory, the existing memory and computation integrated design architecture has the additional computation data input units, so that the area is increased, and meanwhile, the input data ports are increased. As shown in fig. 1, the input of 128-bit memory data and the input of 128-bit calculation data require 256-bit data input ports in total, i.e., 128 memory data input units and 128 calculation data input units. In the prior art, the area of the whole storage and calculation integrated circuit is large due to the large number of ports for inputting data, and the required wiring resource consumption for butting the input ports is obviously increased when the storage and calculation integrated circuit is used outside.
Exemplary Structure
Fig. 2 is a schematic structural diagram of a hybrid data input-based storage integrated circuit according to an exemplary embodiment of the present disclosure. The various components of the circuit may be integrated into a single chip or may be implemented on different chips or circuit boards that establish data communication links therebetween.
As shown in fig. 2, the circuit includes: a memory calculation unit array 201 and a mixed data input unit array 202. The storage computing unit array 201 includes a first preset number of storage computing unit groups, and the storage computing units in each storage computing unit group are in one-to-one correspondence with the mixed data input units in the mixed data input unit array 202. As shown in fig. 2, the first predetermined number is N, and M cells (i.e., memory computing units) in each row represent a memory computing unit group, that is, one memory computing unit group can store M single-bit data. The mixed data input unit array 202 includes M mixed data input units.
In the present embodiment, each mixed data input cell in the mixed data input cell array 202 also corresponds to one memory calculation cell group. For example, the mth mixed data input unit shown in fig. 2 corresponds to the nth memory computing unit group (i.e., nth cell).
As shown in fig. 3, a structure of one of the mixed data input units 2021 is shown. The mixed data input unit 2021 includes a calculation data input subunit 20211, a stored data input subunit 20212, a data switching subunit 20213, a data input port 20214, and a data switching signal input port 20215. The storage data input subunit 20212 is connected to the data storage subunit 20112 included in the corresponding storage calculation unit 2011, and the calculation data input subunit 20211 is connected to the calculation subunits (such as the calculation subunits 20111, 20121, …, 20131 in fig. 3) included in the storage calculation units in the corresponding storage calculation unit group (i.e., one row of cells in fig. 2 including the storage calculation units 2011, 2012, …, 2013 in fig. 3).
The data storage subunit 20112 is configured to store one single-bit data, and the calculation subunit 20111 is configured to perform calculation in a preset manner on the stored data in the data storage subunit 20112 and the single-bit calculation data input by the calculation data input subunit 20211. The functions of the other computing subunits are the same, and are not described in detail here.
It should be noted that a row of cells as shown in fig. 2 usually stores different bits in a multi-bit data, so that when performing calculation of stored data and calculated data, the calculated data input subunit 20211 inputs the same single-bit data to a row of cells at the same time, and after inputting for multiple times, the single bit included in a complete multi-bit calculated data can be calculated with the multi-bit stored data stored in the row of cells respectively.
In this embodiment, the data switching subunit 20213 is configured to input the data received by the data input port 20214 to the data storage subunit 20112 or the calculation subunit 20111 according to the data switching signal input by the data switching signal input port 20215.
Wherein, the data switching signal can be a signal sent by a main controller or an external electronic device included in the circuit. The data switching subunit 20213 may include a circuit block simulating a single pole double throw switch, which may connect the data switching signal input port 20215 with the calculation data input subunit 20211 or the storage data input subunit 20212.
According to the circuit provided by the above embodiment of the disclosure, the input ports for calculating data and the input ports for storing data are integrated into one mixed data input unit, so that the number of the input ports of the integrated circuit is reduced to be the same as that of the input ports of the traditional memory with only a storage function, and thus, the consumption of routing resources caused by the connection and routing between the inside and the outside of the integrated circuit and the data input ports is reduced. By combining the calculation data input subunit and the storage data input subunit, compared with the conventional scheme that the storage data input unit and the calculation data input unit are separately arranged, the embodiment of the disclosure reduces the area of the circuit layout by arranging the mixed data input unit.
In some alternative implementations, the calculation subunit may include a multiplier for performing a multiplication calculation on the data in the corresponding data storage subunit and calculation subunit. The multiplier is usually a single-bit multiplier, and the implementation manner of the single-bit multiplier can be various, such as an and gate, a combination of an not gate and a nor gate (i.e., inverting the stored data and the calculated data and then performing a nor operation), and the like.
The realization mode sets the calculation subunit as a single-bit multiplier, can realize the internal multiplication operation, and can realize the internal multiplication and addition operation by combining with the adder array, thereby effectively utilizing the characteristic of small port number of the circuit and improving the efficiency of the internal multiplication or multiplication and addition operation.
In some alternative implementations, as shown in fig. 2, the circuit further includes a master controller 203, and the master controller 203 is configured to adjust the current storage mode. The storage mode comprises a storage mode and a calculation mode.
In the storage mode, the main controller 203 sends a first switching signal to the data switching signal input port; in the calculation mode, the main controller sends a second switching signal to the data switching signal input port.
Wherein, referring to fig. 3, the first switching signal is used to instruct to input the data received by the current data input port 20214 into the corresponding stored data input subunit 20212; the second switching signal is used to instruct to input the data received by the current data input port 20214 into the corresponding calculation data input subunit 20211.
Specifically, if the circuit is used in a conventional data storage scenario, the main controller 203 may adjust the storage mode to a storage mode, where the mixed data input cell array 202 corresponds to a conventional storage data input array. If the circuit is used in a scenario of performing memory calculation on algorithms such as a neural network, the controller may first adjust the memory calculation mode to the storage mode, and at this time, the mixed data input unit array 202 inputs the storage data received by the data input port into the corresponding memory calculation unit group for storage. Then, the main controller 203 can adjust the calculation mode to the calculation mode, and the calculation data received by the data input port is input into the corresponding storage calculation unit group for calculation.
According to the implementation mode, the main controller is arranged in the circuit and adjusts the storage mode, so that data transmission and data calculation of each component in the circuit can be effectively controlled, the function of the storage and calculation integrated circuit is more perfect, and the efficiency of storage calculation from the storage and calculation integrated circuit is improved.
In some alternative implementations, as shown in fig. 2, the circuit further includes an address decoder 204.
The main controller 203 is also used for acquiring the address of the data to be input and sending the address of the data to be input to the address decoder. Wherein the address of the data to be input can be automatically determined by the program running on the main controller 203.
The address decoder is used for determining a target storage calculation unit group from the first preset number of storage calculation unit groups according to the data address to be input. After sending the to-be-input data address add1 to the address decoder 204, the address decoder 204 further selects a target memory computing unit group. As shown in fig. 2, the memory calculation unit group located in the first row is a target memory calculation unit group.
The main controller 203 is also configured to send data to be input to the target memory calculation unit group through a data input port included in a mixed data input unit in the mixed data input unit array 202. Specifically, the main controller 203 may control the word line corresponding to the target storage computing unit group to communicate with the mixed data input unit array 202, and the main controller 203 sends the data switching signal to the data switching signal input port of each mixed data input unit according to the current storage computing mode, so that each mixed data input unit sends the data to be input to the target storage computing unit group for data storage or computation.
The implementation mode can accurately determine the target storage calculation unit group by arranging the address decoder, thereby being beneficial to further improving the accuracy of data transmission under the condition of using less data input ports.
In some optional implementations, as shown in fig. 2, the circuit further includes an adder array 205, where the adder array 205 is configured to add the calculation results input from the first preset number of memory calculation unit groups to obtain an accumulation result.
The implementation mode can add the calculation results output by the storage calculation unit array to obtain an accumulation result by arranging the adder array, can support multiply-add operation in scenes such as a neural network and the like, and reduces the area of a multiply-add operation circuit and consumed routing resources by reducing the number of data input ports.
In some optional implementations, the adder array includes a second preset number of adder groups, the second preset number of adder groups are sequentially connected in a cascade manner, and input ends of adders included in a first-stage adder group in the second preset number of adder groups are respectively connected to corresponding storage calculation unit groups.
As shown in fig. 4, the adder array includes P (i.e., a second predetermined number) columns, each of which includes adders in one adder group, i.e., a first column labeled "adder _ 1" is a first-level adder group, a second column labeled "adder _ 2" is a second-level adder group, … …, and a pth column labeled "adder _ P" is a pth-level adder group. Starting from the second-stage adder group, each adder corresponds to two adders of a previous stage, namely the outputs of the two adders of the previous stage are used as the inputs of the adder of the next stage. The adder group of the first level comprises adders each receiving the calculation result input by the corresponding storage calculation unit, and the adder group of the P level comprises only one adder, and the output data of the adder group of the P level is the sum of the data output by the N storage calculation unit groups respectively.
The implementation mode can effectively save the area occupied by the adder array by arranging the cascaded adder groups, improve the area utilization rate of the circuit, shorten the length of a data transmission line in the circuit and be beneficial to reducing the power consumption of the circuit.
In some optional implementations, as shown in fig. 2, the circuit further includes a shift accumulator 206, where the shift accumulator is configured to shift and accumulate at least two values output by the adder array sequentially by corresponding bits to obtain an accumulation result.
As an example, if the mixed data input unit array 202 sequentially inputs the 0 th bit, the 1 st bit, the 2 nd bit, and the 3 rd bit of the N calculation data through the respective calculation data input sub-units four times, the summation results sequentially output by the adder array are s0, s1, s2, and s3, and the shift accumulator obtains the multiplication and addition result by the following calculation: SUM-s 3 × 8+ s2 × 4+ s1 × 2+ s 0.
According to the implementation mode, the shift accumulator is arranged, multiplication and addition operation of multi-bit data can be realized, the characteristic that the number of data input ports is small is effectively utilized, the area utilization rate of the multi-bit data multiplication and addition operation circuit is further improved, the wiring complexity in the circuit is reduced, and the reduction of the power consumption of the circuit is facilitated.
Embodiments of the present disclosure also provide a chip, on which a banker circuit based on hybrid data input is integrated, and the technical details of the banker circuit based on hybrid data input are shown in fig. 1 to 4 and related description, and are not described herein.
Embodiments of the present disclosure also provide a computing device including the chip described in the above embodiments. Furthermore, the computing device may also include input devices, output devices, and necessary memory, etc. The input device may include a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting stored data, calculated data, etc., among others. The output means may include, for example, a display, a printer, and a communication network and a remote output device connected thereto, etc., for outputting data such as the accumulation result. The memory is used for storing the data input by the input device and the data generated in the operation process of the integrated circuit based on the mixed data input. The memory may include volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, flash memory, and the like.
The foregoing describes the general principles of the present disclosure in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present disclosure are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present disclosure. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the disclosure is not intended to be limited to the specific details so described.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other.
The block diagrams of devices, apparatuses, systems referred to in this disclosure are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
The circuitry of the present disclosure may be implemented in a number of ways. For example, the circuitry of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of the steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, the program including machine-readable instructions for implementing the functions of the circuit according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the functions of the circuit according to the present disclosure.
It is further noted that in the circuits of the present disclosure, components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered equivalents of the present disclosure.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (9)
1. A memory integrated circuit based on hybrid data input, comprising: the mixed data input unit comprises a storage calculation unit array and a mixed data input unit array, wherein the storage calculation unit array comprises a first preset number of storage calculation unit groups, and the storage calculation units in each storage calculation unit group correspond to the mixed data input units in the mixed data input unit array one by one;
the mixed data input unit in the mixed data input unit array comprises a calculation data input subunit, a storage data input subunit, a data switching subunit, a data input port and a data switching signal input port;
the storage data input subunit is connected with the data storage subunit included by the corresponding storage computing unit, and the computing data input subunit is connected with the computing subunit included by the storage computing unit in the corresponding storage computing unit group;
the data switching subunit is configured to input the data received by the data input port to the data storage subunit or the computation subunit according to the data switching signal input by the data switching signal input port.
2. The circuit of claim 1, wherein the computation subunit comprises a multiplier to multiply data in the corresponding data storage subunit and computation subunit.
3. The circuit of claim 1, wherein the circuit further comprises a master controller for adjusting a current save mode, wherein the save mode includes a save mode and a calculate mode, and in the save mode, the master controller sends a first switch signal to the data switch signal input port; in the calculation mode, the main controller sends a second switching signal to the data switching signal input port; the first switching signal is used for indicating that the data received by the data input port at present is input into the corresponding storage data input subunit; the second switching signal is used for indicating that the data received by the data input port at present is input into the corresponding calculation data input subunit.
4. The circuit of claim 3, wherein the circuit further comprises an address decoder;
the main controller is also used for acquiring a data address to be input and sending the data address to be input to the address decoder;
the address decoder is used for determining a target storage calculation unit group from the first preset number of storage calculation unit groups according to the data address to be input;
the main controller is further configured to send data to be input to the target storage computing unit group through a data input port included in a mixed data input unit in the mixed data input unit array.
5. The circuit of claim 1, wherein the circuit further comprises an adder array for adding the calculation results input from the first preset number of memory calculation unit groups to obtain an accumulation result.
6. The circuit of claim 5, wherein the adder array comprises a second predetermined number of adder groups, the second predetermined number of adder groups are sequentially connected in a cascade manner, and the input terminals of the adders included in the first-stage adder group of the second predetermined number of adder groups are respectively connected to the corresponding storage and computation unit groups.
7. The circuit of claim 5, further comprising a shift accumulator, wherein the shift accumulator is configured to shift and accumulate at least two values output by the adder array sequentially by corresponding bits to obtain an accumulation result.
8. A chip comprising a memory integrated circuit based on hybrid data input according to any one of claims 1-7.
9. A computing device comprising the chip of claim 8.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115756388A (en) * | 2023-01-06 | 2023-03-07 | 上海后摩智能科技有限公司 | Multi-mode storage and calculation integrated circuit, chip and calculation device |
| CN115906735A (en) * | 2023-01-06 | 2023-04-04 | 上海后摩智能科技有限公司 | Multi-bit-number storage and calculation integrated circuit based on analog signals, chip and calculation device |
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2021
- 2021-10-25 CN CN202111240214.2A patent/CN113885831A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115756388A (en) * | 2023-01-06 | 2023-03-07 | 上海后摩智能科技有限公司 | Multi-mode storage and calculation integrated circuit, chip and calculation device |
| CN115906735A (en) * | 2023-01-06 | 2023-04-04 | 上海后摩智能科技有限公司 | Multi-bit-number storage and calculation integrated circuit based on analog signals, chip and calculation device |
| CN115906735B (en) * | 2023-01-06 | 2023-05-05 | 上海后摩智能科技有限公司 | Multi-bit number storage and calculation integrated circuit, chip and calculation device based on analog signals |
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