CN113885651A - Low dropout voltage stabilizing circuit and low dropout voltage stabilizer - Google Patents
Low dropout voltage stabilizing circuit and low dropout voltage stabilizer Download PDFInfo
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- CN113885651A CN113885651A CN202111214767.0A CN202111214767A CN113885651A CN 113885651 A CN113885651 A CN 113885651A CN 202111214767 A CN202111214767 A CN 202111214767A CN 113885651 A CN113885651 A CN 113885651A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
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Abstract
The invention discloses a low dropout voltage stabilizing circuit and a low dropout voltage stabilizer, wherein an input port is used for inputting voltage to be stabilized, an output port is connected to an external load and outputs stabilized voltage to the external load, and an amplifying unit is used for converting the voltage to be stabilized into output current with high-impedance differential characteristics; the lower peak unit is used for inhibiting the lower peak voltage value of the regulated voltage when the regulated voltage drops suddenly; the peak rising unit is used for reducing the peak value of the voltage stabilizing voltage when the voltage stabilizing voltage output by the output port suddenly rises; the transmission unit is used for controlling the static current to synchronously change proportionally according to the change of the output current flowing through the external load; the buffer unit is used for buffering the change amplitude of the output current flowing through the external load when the stabilized voltage suddenly changes; the invention effectively reduces and controls the overshoot and undershoot voltage spikes caused by sudden load change, and effectively enhances the current driving capability.
Description
Technical Field
The invention relates to the technical field of voltage stabilizer manufacturing, in particular to a low dropout voltage stabilizing circuit and a low dropout voltage stabilizer.
Background
With the strong demand of electronic mobile products and the rapid development of battery density, the proportion of the electronic products powered by batteries is increasing, and even automobiles tend to use batteries as driving sources. All of these electronic products need to design and integrate a set of power management system to meet the requirement of stable power supply. Among them, the ldo (low dropout voltage) regulator has good power efficiency, transient response and immunity, and is a commonly used circuit.
A low dropout regulator is a dc linear regulator that can regulate an output voltage even if a power supply voltage is very close to the output voltage. Advantages of low dropout regulators over other DC-DC regulators include: no switching noise; the device size is smaller; the circuit is simpler; the linear direct current voltage stabilizer has the defect that the output voltage can be regulated only by dissipating heat through a regulating circuit to dissipate power. Key performance indicators of the low dropout regulator include a linear regulation (line regulation), a load regulation (load regulation), a maximum load current (max load current), a transient response (transient response), an on-chip capacitance (on-chip capacitance), a stability, a quiescent current amplitude (quiescent current), a power supply rejection ratio (power supply rejection ratio), and the like. They all have a trade-off relationship, such as decreasing the quiescent current, the transient response is affected. In recent years, a number of new low dropout regulator architectures and design optimization schemes have been presented, however, various existing architectures and designs have limitations, such as increasing the order of transmission characteristics by using a local common mode feedback technique, so that better regulation can be achieved at low quiescent current. In another example, a plurality of small gain stages are used to avoid the load of the voltage regulator being distributed between two transmission transistors and on-chip capacitance, but the linear regulation rate and the load regulation rate are not ideal. Again, an inverted voltage follower output stage is used to improve response time and reduce voltage spikes during load transitions, but the output current is not high.
In addition, the use of an integrated on-chip capacitor is a common design approach for low dropout regulators, so the chip area occupied by the low dropout regulator depends to a large extent on the size of the on-chip capacitor, but if the chip area is reduced for reducing the capacitance value, transient response and stability are reduced.
Disclosure of Invention
The invention aims to provide a low dropout voltage stabilizing circuit and a low dropout voltage stabilizer, which can effectively reduce and control overshoot and undershoot voltage spikes caused by sudden load change and effectively enhance current driving capability.
In order to achieve the purpose, the invention discloses a low-dropout voltage stabilizing circuit which comprises an input port, an output port, an amplifying unit, a lower peak unit, an upper peak unit, a transmission unit and a buffer unit, wherein the input port is used for inputting voltage to be stabilized, the output port is connected to an external load and outputs stabilized voltage to the external load, and the amplifying unit is used for converting the voltage to be stabilized into output current with high-impedance differential characteristics; the lower peak unit is used for inhibiting an undershoot voltage peak value of the regulated voltage when the regulated voltage suddenly drops; the peak rising unit is used for reducing the peak value of the voltage-stabilizing voltage when the voltage-stabilizing voltage output by the output port suddenly rises; the transmission unit is used for controlling the static current to synchronously change in proportion according to the change of the output current flowing through the external load; the buffer unit is used for buffering the change amplitude of the output current flowing through the external load when the stabilized voltage changes suddenly.
Compared with the prior art, the low-dropout regulator is provided with the amplifying unit, the low-dropout unit, the high-dropout unit, the transmission unit and the buffer unit, wherein the low-dropout unit inhibits the down-rush voltage peak value of the regulated voltage when the regulated voltage suddenly drops, the high-dropout unit reduces the up-rush voltage peak value of the regulated voltage when the regulated voltage output by the output port suddenly rises, and the transmission unit controls the static current to synchronously change proportionally according to the change of the output current flowing through the external load, so that the overshoot and the down-rush voltage peak caused by the sudden change of the load can be effectively reduced and controlled, the current driving capability can be effectively enhanced, in addition, the capacitors adopted by the low-dropout regulator are all capacitors at the class of picofarad, the integrated area of a chip is effectively reduced, and the low-dropout regulator is suitable for being manufactured into a small-sized low-dropout regulator.
Preferably, the amplifying unit is a voltage-controlled current source, the amplifying unit is provided with a high-impedance differential input stage with high-impedance differential characteristics, and the voltage to be stabilized is connected to the high-impedance differential input stage.
Preferably, the amplifying unit includes a fourth fet M4 and a seventh fet M7, sources of the fourth fet M4 and the seventh fet M7 are respectively connected to the input port, and drains of the fourth fet M4 and the seventh fet M7 are shorted.
Preferably, the down peak unit includes a first fet M1, a first resistor R1, a first capacitor C1 and a first constant current source I1, one end of the first resistor R1 is connected to the gate of the first fet M1, the other end is connected to the gates of the first capacitor C1 and the fourth fet M4, the source of the first fet M1 is connected to the input port, the input of the first constant current source I1 is connected to the drain of the first fet M1, the output is grounded, and the first resistor R1 and the first capacitor C1 together form a first differentiator to reduce the down peak voltage of the regulated parasitic voltage by providing a larger static current and charging the parasitic capacitor when the VGS value of the fourth fet M4 increases instantaneously.
Preferably, the peaking unit includes a twelfth fet M12, a thirteenth fet M13, a fourteenth fet M14, a second resistor R2, a second capacitor C2, a third capacitor C3 and a second constant current source I2, a gate of the twelfth fet M12 is connected to a gate of the seventh fet M7, a source of the twelfth fet M7 is connected to the input port, a drain of the thirteenth fet M13 is connected to a drain of the thirteenth fet M13, a gate of the thirteenth fet M13 is connected to a gate of the fourteenth fet M14 through the second resistor R2, sources of the thirteenth fet M13 and the fourteenth fet M14 are respectively grounded, a short circuit is formed between the gate and the drain of the fourteenth fet M14, an input of the second constant current source I2 is connected to the input port, an output of the fourteenth fet M14 is connected to a drain of the second capacitor C2 and a third capacitor C3 in series, and the output port is connected to a third capacitor C3, one end of the first capacitor C1, which is far away from the first resistor R1, is connected between the second capacitor C2 and a third capacitor C3, one end of the third capacitor C3, which is far away from the second capacitor C2, is connected between the gate of the thirteenth fet M13 and the second resistor R2, and the second resistor R2 and the third capacitor C3 together form a second differentiator, so that a quiescent current is fed back and regulated through the thirteenth fet M13, the twelfth fet M12 and the seventh fet M7, thereby reducing an overshoot voltage peak of the regulated voltage.
Preferably, the transmission unit includes a fifteenth fet M15, a sixteenth fet M16, a seventeenth fet M17, an eighteenth fet M18, a nineteenth fet M19, a twentieth fet M20, a third constant current source I3 and a schottky diode D1, the schottky diode D1 is integrated on a chip, a gate of the fifteenth fet M15 is connected to an end of the second capacitor C2 away from the third capacitor C3, a drain is connected to the input port, a source is connected to a source of the sixteenth fet M16, a substrate is connected to an output terminal of the schottky diode D1, a gate of the eighteenth fet M18 is connected to a gate of the fifteenth fet M15, a drain is connected to the input port, a source is connected to the output port, a substrate is connected to an output terminal of the schottky diode D1, a gate of the sixteenth fet M16 is connected to a gate of the nineteenth fet M19, the drain of the seventeenth fet M17 is connected to the drain of the seventeenth fet M17, the drain of the nineteenth fet M19 is connected to the input terminal of the third constant current source I3, the drain of the nineteenth fet M19 is also shorted to the gate of the nineteenth fet M19, the output terminal of the third constant current source I3 is grounded, the source of the seventeenth fet M17 is grounded, the gate is connected to the gate of the twentieth fet M20, the drain of the twentieth fet M20 is connected to the output terminal of the schottky diode D1, the source is grounded, the input terminal of the schottky diode D1 is connected to the input port, the sixteenth fet M16 and the nineteenth fet M19 together form a current mirror, so that the eighteenth fet M18 and the fifteenth fet M15 have the same drain voltage, and the seventeenth fet M17 and the twentieth fet M20 together form a transistor structure, so as to adaptively control the bias point of the schottky diode D1 according to the change of the output current of the external load, thereby enabling the quiescent current to be synchronously changed in proportion to the change of the output current of the external load.
Preferably, the buffer unit comprises a twenty-first field effect transistor M21, a third resistor R3, a fourth resistor R4 and a fourth capacitor C4, the grid electrode of the twenty-first field effect transistor M21 is connected with the grid electrode of the eighth field effect transistor M8, the source electrode is grounded, the drain electrode is connected with the output port, one end of the fourth capacitor C4 is connected between the gate of the twenty-first fet M21 and the gate of the eighth fet M8, and the other end is connected between the drain of the twenty-first fet M21 and the source of the nineteenth fet M19, one end of the third resistor R3 is connected between the fourth capacitor C4 and the drain of the twenty-first FET M21, the other end is connected between the fourth capacitor C4 and the gate of the twenty-first FET M21, one end of the fourth resistor R4 is connected between the fourth capacitor C4 and the gate of the twenty-first fet M21, and the other end is grounded.
Preferably, the quiescent current is an internal current of the low dropout voltage regulator circuit after the low dropout voltage regulator circuit is electrically disconnected from the external load.
Correspondingly, the invention also discloses a low dropout regulator which comprises the low dropout voltage stabilizing circuit.
Drawings
FIG. 1 is a circuit diagram of a low dropout voltage regulator circuit of the present invention.
Detailed Description
In order to explain technical contents, structural features, and objects and effects of the present invention in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1, the low dropout regulator of the present embodiment can effectively improve current and voltage spikes during load sudden change, and a large amount of small-sized capacitors are used to meet the requirements of stability and miniaturization. The low dropout voltage regulator comprises a low dropout voltage regulator circuit. The specific circuit structure of the low dropout voltage regulator circuit is described in detail below.
Referring to fig. 1, the low dropout voltage regulator of the present embodiment includes an input port 10, an output port 20, an amplifying unit 30, a peak descending unit 40, a peak ascending unit 50, a transmission unit 60, and a buffer unit 70, wherein the input port 10 is used for inputting a voltage to be regulated, and the output port 20 is connected to an external load (not shown) and outputs the regulated voltage to the external load. It can be understood that the voltage to be regulated enters the low dropout voltage regulator circuit through the input port 10, is subjected to voltage regulation processing, and is output to an external load from the output port 20. The external load here includes, but is not limited to, various electric devices.
When the low dropout voltage regulator circuit is connected to an external load and normally operates, working current flows through the low dropout voltage regulator circuit, and when the low dropout voltage regulator circuit is disconnected from the external load, the internal current of the low dropout voltage regulator circuit is quiescent current.
The amplifying unit 30 is used for converting the voltage to be stabilized into an output current with high impedance difference characteristics; the lower peak unit 40 is used for suppressing an undershoot voltage peak value of the regulated voltage when the regulated voltage suddenly drops; the peak rising unit 50 is used for reducing the peak value of the surge voltage of the regulated voltage when the regulated voltage output by the output port 20 suddenly rises; the transmission unit 60 is used for controlling the quiescent current to synchronously change proportionally according to the change of the output current flowing through the external load; the buffering unit 70 is used for buffering the variation amplitude of the output current flowing through the external load when the regulated voltage abruptly changes.
Specifically, the amplifying unit 30 is a voltage-controlled current source, the amplifying unit 30 is provided with a high-impedance differential input stage with high-impedance differential characteristics, and the voltage to be stabilized is connected to the high-impedance differential input stage. After the voltage to be stabilized is amplified by the amplifying unit 30, an output current with high impedance difference characteristic is generated.
Preferably, the amplifying unit 30 includes a fourth fet M4 and a seventh fet M7, sources of the fourth fet M4 and the seventh fet M7 are respectively connected to the input port 10, and drains of the fourth fet M4 and the seventh fet M7 are shorted.
It is understood that the amplifying unit 30 can be regarded as an operational transconductance amplifier to implement a high impedance differential amplifying process of the voltage to be regulated.
Preferably, the peak load unit 40 includes a first fet M1, a first resistor R1, a first capacitor C1 and a first constant current source I1, one end of the first resistor R1 is connected to the gate of the first fet M1, the other end is connected to the gates of the first capacitor C1 and the fourth fet M4, the source of the first fet M1 is connected to the input port 10, the input of the first constant current source I1 is connected to the drain of the first fet M1, the output is grounded, and the first resistor R1 and the first capacitor C1 together form a first differential undershoot device, so that when the VGS value of the fourth fet M4 is increased instantaneously, the peak voltage value of the regulated voltage is reduced by providing a larger static current and charging the parasitic capacitor.
It can be understood that when the stabilized voltage at the output port 20 suddenly drops due to a sudden change of the external load, the first differentiator can instantaneously increase the VGS value of the fourth fet M4 so as to obtain a larger quiescent current for the low dropout regulation circuit, and the first differentiator can charge the parasitic capacitor formed by the low dropout regulation circuit, thereby reducing the undershoot voltage peak of the stabilized voltage. When the first differentiator operates, the peaking unit 50 is in a cutoff state.
Preferably, the upper peak unit 50 includes a twelfth fet M12, a thirteenth fet M13, a fourteenth fet M14, a second resistor R2, a second capacitor C2, a third capacitor C3 and a second constant current source I2, a gate of the twelfth fet M12 is connected to a gate of the seventh fet M7, a source is connected to the input port 10, a drain is connected to a drain of the thirteenth fet M13, a gate of the thirteenth fet M13 is connected to a gate of the fourteenth fet M14 through the second resistor R2, sources of the thirteenth fet M13 and the fourteenth fet M14 are respectively connected to ground, a short circuit is formed between the gate and the drain of the fourteenth fet M14, an input of the second constant current source I2 is connected to the input port 10, an output is connected to a drain of the fourteenth fet M14, the second capacitor C2 and the third capacitor C3 are connected in series, an output port 20 is connected between the second capacitor C2 and the third capacitor C3, and a first capacitor C3 is connected to a third capacitor C3, one end of the third capacitor C3, which is far from the second capacitor C2, is connected between the gate of the thirteenth fet M13 and the second resistor R2, and the second resistor R2 and the third capacitor C3 together form a second differentiator, so as to feed back and adjust the quiescent current through the thirteenth fet M13, the twelfth fet M12 and the seventh fet M7, thereby reducing the overshoot voltage peak of the regulated voltage.
It can be understood that when the steady-state voltage at the output port 20 overshoots, the peaking unit 50 is activated, and the second differentiator feeds back and regulates the quiescent current through the thirteenth fet M13, the twelfth fet M12 and the seventh fet M7 to reduce the overshoot voltage peak of the regulated voltage. When the second differentiator operates, the lower peak unit 40 is in a cut-off state.
Preferably, the transmission unit 60 includes a fifteenth fet M15, a sixteenth fet M16, a seventeenth fet M17, an eighteenth fet M18, a nineteenth fet M19, a twentieth fet M20, a third constant current source I3 and a schottky diode D1, the schottky diode D1 is integrated on the chip, the gate of the fifteenth fet M15 is connected to the end of the second capacitor C2 away from the third capacitor C3, the drain is connected to the input port 10, the source is connected to the source of the sixteenth fet M16, the substrate is connected to the output terminal of the schottky diode D1, the gate of the eighteenth fet M18 is connected to the gate of the fifteenth fet M15, the drain is connected to the input port 10, the source is connected to the output port 20, the substrate is connected to the output terminal of the schottky diode D1, the gate of the sixteenth fet M16 is connected to the gate of the nineteenth fet M19, and the drain is connected to the seventeenth drain of the schottky diode M17, the drain of the nineteenth field effect transistor M19 is connected with the input end of the third constant current source I3, the drain of the nineteenth field effect transistor M19 is also short-circuited with the gate of the nineteenth field effect transistor M19, the output end of the third constant current source I3 is grounded, the source of the seventeenth field effect transistor M17 is grounded, the gate is connected with the gate of the twentieth field effect transistor M20, the drain of the twentieth field effect transistor M20 is connected with the output end of the Schottky diode D1, the source is grounded, the input end of the Schottky diode D1 is connected with the input port 10, the sixteenth field effect transistor M16 and the nineteenth field effect transistor M19 jointly form a current mirror, so that the eighteenth FET M18 and the fifteenth FET M15 have the same drain voltage, the seventeenth FET M17 and the twentieth FET M20 together form a transistor structure, to adaptively control the bias point of the schottky diode D1 according to the change of the output current of the external load, thereby enabling the quiescent current to synchronously vary in proportion to changes in the output current of the external load.
It will be appreciated that in order to reduce the quiescent current and steady state voltage spikes during sudden changes in the external load, the transistor structure described above adaptively changes the bias point of schottky diode D1 in response to changes in the current of the external load, such that the magnitude of the quiescent current is controlled and proportionately changed by the external load current, with larger quiescent current values occurring only during sudden changes in the external load. The schottky diode D1 is integrated on the chip.
Preferably, the buffer unit 70 includes a twenty-first fet M21, a third resistor R3, a fourth resistor R4 and a fourth capacitor C4, the gate of the twenty-first fet M21 is connected to the gate of the eighth fet M8, the source is grounded, the drain is connected to the output port 20, one end of the fourth capacitor C4 is connected between the gate of the twenty-first fet M21 and the gate of the eighth fet M8, the other end is connected between the drain of the twenty-first fet M21 and the source of the nineteenth fet M19, one end of the third resistor R3 is connected between the drain of the fourth capacitor C4 and the drain of the twenty-first fet M21, the other end is connected between the fourth capacitor C4 and the gate of the twenty-first fet M21, one end of the fourth resistor R4 is connected between the fourth capacitor C4 and the gate of the twenty-first fet M21, and the other end is grounded.
It will be appreciated that the twenty-first fet M21 acts as a current buffer during transient external load transitions, and that as the external load changes from a minimum to a maximum in a short period of time, the voltage at the output and gate of the twenty-first fet M21 will drop, forcing the twenty-first fet M21 to receive less current. Meanwhile, the transmission unit 60 guides the current to be output, so that the transient response of the low dropout voltage regulator circuit of the embodiment is improved, and the voltage regulation performance is effectively improved.
It should be noted that all components or some components understood in this embodiment may be integrated together on a chip to further reduce the overall size.
With reference to fig. 1, the present invention provides an amplifying unit 30, a lower peak unit 40, an upper peak unit 50, a transmission unit 60 and a buffering unit 70, wherein the lower peak unit 40 suppresses an undershoot voltage peak of the regulated voltage when the regulated voltage suddenly drops, the upper peak unit 50 decreases an overshoot voltage peak of the regulated voltage when the regulated voltage output from the output port 20 suddenly rises, and the transmission unit 60 controls the static current to synchronously change proportionally according to the change of the output current flowing through the external load, so that the present invention can effectively reduce and control the overshoot and undershoot voltage peaks caused by the sudden change of the load, and can effectively enhance the current driving capability.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the present invention, therefore, the present invention is not limited by the appended claims.
Claims (9)
1. A low dropout voltage regulator circuit is characterized by comprising an input port, an output port, an amplifying unit, a lower peak unit, an upper peak unit, a transmission unit and a buffer unit, wherein the input port is used for inputting voltage to be regulated, the output port is connected to an external load and outputs the voltage to be regulated to the external load, and the amplifying unit is used for converting the voltage to be regulated into output current with high-impedance differential characteristics; the lower peak unit is used for inhibiting an undershoot voltage peak value of the regulated voltage when the regulated voltage suddenly drops; the peak rising unit is used for reducing the peak value of the voltage-stabilizing voltage when the voltage-stabilizing voltage output by the output port suddenly rises; the transmission unit is used for controlling the static current to synchronously change in proportion according to the change of the output current flowing through the external load; the buffer unit is used for buffering the change amplitude of the output current flowing through the external load when the stabilized voltage changes suddenly.
2. The low dropout voltage regulator circuit of claim 1, wherein the amplifying unit is a voltage controlled current source, the amplifying unit has a high impedance differential input stage with high impedance differential characteristics, and the voltage to be regulated is coupled to the high impedance differential input stage.
3. The low dropout voltage regulator circuit of claim 2 wherein the amplifying unit comprises a fourth fet M4 and a seventh fet M7, wherein the sources of the fourth fet M4 and the seventh fet M7 are respectively connected to the input port, and the drains of the fourth fet M4 and the seventh fet M7 are shorted.
4. The low dropout voltage regulator circuit of claim 3 wherein the down-peak unit comprises a first fet M1, a first resistor R1, a first capacitor C1 and a first constant current source I1, wherein one end of the first resistor R1 is connected to the gate of the first fet M1, the other end is connected to the gates of the first capacitor C1 and the fourth fet M4, respectively, the source of the first fet M1 is connected to the input port, the input of the first constant current source I1 is connected to the drain of the first fet M1, and the output is connected to ground, and the first resistor R1 and the first capacitor C1 together form a first differentiator to reduce the down-peak voltage of the regulated voltage by providing a larger quiescent current and charging a parasitic capacitor when the VGS value of the fourth fet M4 increases momentarily.
5. The low dropout voltage regulator circuit of claim 4 wherein the peaking unit comprises a twelfth FET M12, a thirteenth FET M13, a fourteenth FET M14, a second resistor R2, a second capacitor C2, a third capacitor C3 and a second constant current source I2, wherein the gate of the twelfth FET M12 is connected to the gate of the seventh FET M7, the source of the twelfth FET M12 is connected to the input port, the drain of the twelfth FET M13 is connected to the drain of the thirteenth FET M13, the gate of the thirteenth FET M13 is connected to the gate of the fourteenth FET M14 through the second resistor R2, the sources of the thirteenth and fourteenth FETs M13 and M14 are grounded, respectively, the gate and the drain of the fourteenth FET M14 are shorted, the input of the second constant current source I2 is connected to the input port, and the output of the fourteenth FET M14 is connected to the drain of the fourteenth FET M14, the second capacitor C2 and the third capacitor C3 are connected in series, the output port is connected between the second capacitor C2 and the third capacitor C3, one end of the first capacitor C1, which is far away from the first resistor R1, is connected between the second capacitor C2 and the third capacitor C3, one end of the third capacitor C3, which is far away from the second capacitor C2, is connected between the gate of the thirteenth fet M13 and the second resistor R2, and the second resistor R2 and the third capacitor C3 together form a second differentiator to feed back and adjust a static current through the thirteenth fet M13, the twelfth fet M12 and the seventh fet M7, so as to reduce an overshoot voltage peak of the regulated voltage.
6. The low dropout voltage regulator circuit of claim 5 wherein the pass unit comprises a fifteenth FET M15, a sixteenth FET M16, a seventeenth FET M17, an eighteenth FET M18, a nineteenth FET M19, a twentieth FET M20, a third constant current source I3, and a Schottky diode D1, the Schottky diode D1 is integrated on a chip, the gate of the fifteenth FET M15 is connected to an end of the second capacitor C2 away from the third capacitor C3, the drain is connected to the input port, the source is connected to the source of the sixteenth FET M16, the substrate is connected to the output terminal of the Schottky diode D1, the gate of the eighteenth FET M18 is connected to the gate of the fifteenth FET M15, the drain is connected to the input port, the source is connected to the output port, and the substrate is connected to the output terminal of the Schottky diode D1, the gate of the sixteenth fet M16 is connected to the gate of the nineteenth fet M19, the drain of the sixteenth fet M19 is connected to the drain of the seventeenth fet M17, the drain of the nineteenth fet M19 is connected to the input terminal of the third constant current source I3, the drain of the nineteenth fet M19 is also shorted to the gate of the nineteenth fet M19, the output terminal of the third constant current source I3 is grounded, the source of the seventeenth fet M17 is grounded, the gate of the seventeenth fet M17 is connected to the gate of the twentieth fet M20, the drain of the twentieth fet M20 is connected to the output terminal of the schottky diode D1, the source of the third constant current source is grounded, the input terminal of the schottky diode D1 is connected to the input port, and the sixteenth fet M16 and the nineteenth fet M19 together form a current mirror, so that the eighteenth fet M18 and the fifteenth fet M15 have the same drain voltage, the seventeenth fet M17 and the twentieth fet M20 together form a transistor structure to adaptively control the bias point of the schottky diode D1 according to the change of the output current of the external load, so that the quiescent current can be synchronously changed in proportion to the change of the output current of the external load.
7. The low dropout voltage regulator circuit of claim 6 wherein the buffer unit comprises a twenty-first FET M21, a third resistor R3, a fourth resistor R4 and a fourth capacitor C4, wherein the gate of the twenty-first FET M21 is connected to the gate of the eighth FET M8, the source is grounded, the drain is connected to the output port, one end of the fourth capacitor C4 is connected between the gate of the twenty-first FET M21 and the gate of the eighth FET M8, the other end is connected between the drain of the twenty-first FET M21 and the source of the nineteenth FET M19, one end of the third resistor R3 is connected between the fourth capacitor C4 and the drain of the twenty-first FET M21, the other end is connected between the fourth capacitor C4 and the gate of the twenty-first FET M21, one end of the fourth resistor R4 is connected between the gate of the fourth capacitor C4 and the twenty-first FET M21, the other end is grounded.
8. The low dropout voltage regulator circuit of claim 1, wherein the quiescent current is an internal current of the low dropout voltage regulator circuit after the low dropout voltage regulator circuit is electrically disconnected from the external load.
9. A low dropout regulator comprising a low dropout voltage regulator circuit according to any one of claims 1 to 8.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020130646A1 (en) * | 2001-01-26 | 2002-09-19 | Zadeh Ali Enayat | Linear voltage regulator using adaptive biasing |
| CN102063146A (en) * | 2011-01-21 | 2011-05-18 | 东南大学 | Adaptive frequency-compensation linear voltage stabilizer with low voltage difference |
| TW201504782A (en) * | 2013-03-06 | 2015-02-01 | Seiko Instr Inc | Voltage regulator |
| CN113064464A (en) * | 2021-03-31 | 2021-07-02 | 电子科技大学 | High-precision low-dropout linear regulator with quick transient response |
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2021
- 2021-10-19 CN CN202111214767.0A patent/CN113885651B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020130646A1 (en) * | 2001-01-26 | 2002-09-19 | Zadeh Ali Enayat | Linear voltage regulator using adaptive biasing |
| CN102063146A (en) * | 2011-01-21 | 2011-05-18 | 东南大学 | Adaptive frequency-compensation linear voltage stabilizer with low voltage difference |
| TW201504782A (en) * | 2013-03-06 | 2015-02-01 | Seiko Instr Inc | Voltage regulator |
| CN113064464A (en) * | 2021-03-31 | 2021-07-02 | 电子科技大学 | High-precision low-dropout linear regulator with quick transient response |
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