CN113873184A - Image sensor chip-level ADC trimming system - Google Patents

Image sensor chip-level ADC trimming system Download PDF

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CN113873184A
CN113873184A CN202111277411.1A CN202111277411A CN113873184A CN 113873184 A CN113873184 A CN 113873184A CN 202111277411 A CN202111277411 A CN 202111277411A CN 113873184 A CN113873184 A CN 113873184A
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trimming
module
adc
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control
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CN113873184B (en
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何杰
李婷
曹天娇
袁昕
张曼
徐晚成
崔双韬
李海松
杨靓
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Xian Microelectronics Technology Institute
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters

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Abstract

The invention discloses an image sensor chip-level ADC (analog-to-digital converter) trimming system, which comprises a trimming control module and a trimming pre-writing module, wherein the trimming control module is connected with the trimming pre-writing module, the trimming control module is used for outputting a control signal to the trimming pre-writing module, the trimming output of the trimming pre-writing module is connected to the control end of the ADC module and is connected with each module to be trimmed of the ADC module and used for outputting a trimming control signal, and aiming at system trimming pre-writing, capacitance mismatch trimming, power consumption trimming and error trimming, the performance parameter reduction and power consumption over-tolerance caused by factors such as process deviation mismatch and process angle deviation can be effectively compensated, the key dynamic and static parameters of the ADC are improved, and the system has high practicability.

Description

Image sensor chip-level ADC trimming system
Technical Field
The invention relates to the field of complementary metal-oxide-semiconductor (CMOS) image sensors and data converters, in particular to an ADC trimming system on an image sensor chip.
Background
The on-chip ADC has significant advantages: low power consumption, low noise and high consistency. The chip-level ADC usually adopts a pipeline structure and has higher speed and resolution, the invention is a chip-level ADC IP applied to a million-pixel-level CMOS image sensor, and is a pipeline-type structure ADC with the length of 180nm, the length of 14bit and the length of 200 Msps.
The pipeline ADC is suitable for various environment applications, in particular to the field of high-speed and high-precision applications. A common pipelined ADC consists of a sample-and-hold circuit (SH), a multi-stage quantization circuit (MDAC) and a flash ADC. The SH circuit is usually realized by a charge sharing or capacitance overturning structure, the multi-stage MDAC outputs a final code value after digital code shift correction, and core parameters of the final code value are SNR, SNDR, SFDR, offset error, gain error and full chip power consumption.
After the circuit design is finished, layout parasitic and process deviation can affect the key parameters, the misadjustment of a comparator can reduce SFDR, capacitance mismatching can reduce SNR and SFDR, the parasitic difference of a power supply can cause the increase of offset error and gain error, the process deviation can affect the power consumption of a system and the like, many errors cannot be solved by post simulation, if no corresponding correction measures exist, the product performance can be reduced, the expected purpose of the design cannot be achieved, and relevant correction measures need to be considered.
Disclosure of Invention
The invention aims to provide an image sensor chip-level ADC trimming system to overcome the defects of the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
the utility model provides an image sensor chip level ADC trimming system, includes trimming control module and trimming write-in module in advance, and trimming control module connects trimming write-in module in advance, and trimming control module is used for output control signal to trimming write-in module in advance, and the trimming output of trimming write-in module in advance is connected to the control end of ADC module, is connected with each module of waiting to be corrected of ADC module for output trimming control signal.
Furthermore, the trimming control module comprises a series NMOS switch array, a first self-bias current mirror, a second self-bias current mirror, an NMOS self-bias, a bias control resistor, a pull-down switch and a reverse driver, wherein one end of the series NMOS switch array is grounded, the other end of the series NMOS switch array is connected with the drain electrode of the first self-bias current mirror, and the grid electrode of the series NMOS switch array is connected with a high level VDD(ii) a Source end connection power supply V of first self-bias current mirrorDDThe grid electrode and the drain electrode of the first self-bias current mirror are connected and then connected with the grid electrode of the second self-bias current mirror, and the grid voltage V of the grid electrode of the first self-bias current mirror and the grid electrode of the second self-bias current mirrorA(ii) a The drain electrode of the NMOS self-bias is connected with the drain electrode of the second self-bias current mirror and the drain electrode of the pull-down switch through the grid electrode of the NMOS self-bias, the source electrode of the NMOS self-bias is connected with one end of the bias control resistor, and the other end of the bias control resistor is grounded; the grid of the pull-down switch is connected with the output of the reverse driver, and the source of the pull-down switch is grounded.
Further, the inverting driver input is an enable control signal ENP.
Furthermore, the trimming pre-writing module comprises a plurality of trimming units with the same structure, and the trimming units are connected in series.
Furthermore, the trimming unit comprises a trigger, a phase inverter, a gate, a PMOS (P-channel metal oxide semiconductor) tube, an NMOS (N-channel metal oxide semiconductor) tube and a trimming resistor, wherein the trigger is provided with a plurality of resistors
Figure BDA0003329943870000021
Is connected with the input end of the phase inverter, the firstThe D end of the trigger is connected with the pre-written data Din, the output end Q of the first trigger is connected with the D end of the next series trigger, the output end of the phase inverter is connected with the positive input end of the gate, the negative input end of the gate is connected with the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the source electrode of the PMOS tube is connected with the power supply VDDThe grid of the PMOS tube is connected with the output bias voltage V of the trimming control moduleAThe source electrode of the NMOS tube is connected with one end of the trimming resistor, and the grid electrode of the NMOS tube (108) is connected with the output bias voltage V of the trimming control moduleBThe other end of the trimming resistor is grounded; gating path gate output F controlled by signals S and SN by the gateun。
Furthermore, each trigger is connected with a trigger control clock which triggers the control signal CFU。
Further, the output signal F of the trimming unitU1Fun is a DC signal.
Further, the trimming circuit of the SH module: the negative output end and the positive output end are symmetrically provided with a switch capacitor set.
Furthermore, the switch capacitor group adopts three groups of capacitors and switches which are connected in parallel, and the capacitors and the switches in the same group are connected in series.
Furthermore, the output signal of the trimming unit is not turned over in the working process of the device, the external connection end of the trimming unit is the grid end of a PMOS or NMOS tube, and intervention of a trimming capacitor, adjustment of power consumption, correction of voltage, correction of offset and correction of process angle deviation are controlled in a long on/off mode.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention relates to an image sensor chip-level ADC (analog-to-digital converter) trimming system, which comprises a trimming control module and a trimming pre-writing module, wherein the trimming control module is connected with the trimming pre-writing module, the trimming control module is used for outputting a control signal to the trimming pre-writing module, the trimming output of the trimming pre-writing module is connected to the control end of the ADC module and is connected with each module to be trimmed of the ADC module and used for outputting a trimming control signal, and aiming at system trimming pre-writing, capacitance mismatch trimming, power consumption trimming and error trimming, the performance parameter reduction and power consumption over-tolerance caused by factors such as process deviation mismatch and process angle deviation can be effectively compensated, the key dynamic and static parameters of the ADC are improved, and the system has high practicability.
Furthermore, the pre-written result is solidified by the trimming control module through the trimming equipment, so that the performance parameter reduction and power consumption over-tolerance caused by factors such as process deviation mismatch and process angle deviation caused by process deviation and design redundancy deficiency can be effectively improved, and the key dynamic and static parameters of the ADC are improved.
Furthermore, the device is not turned over in the working process, the external connection end of the device is the grid end of a PMOS or NMOS tube, and intervention of a trimming capacitor, adjustment of power consumption, correction of voltage, correction of offset and correction of process angle deviation are controlled in a long on/off mode, so that dynamic and static performances of the ADC can be effectively improved, and the overall performance of the sensor is improved.
Drawings
Fig. 1 is a schematic circuit diagram of a trimming control module according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of a trimming and pre-writing module according to an embodiment of the invention.
Fig. 3 is an overall structure diagram of ADC trimming control according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of an SH module offset correction circuit according to an embodiment of the invention.
FIG. 5 is a diagram of a linearity correction circuit applied to a first stage according to an embodiment of the present invention.
FIG. 6 is a diagram of a calibration circuit applied to local power consumption/reference in an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
the utility model provides an image sensor chip level ADC trimming system, including trimming control module and trimming write in module in advance, trimming control module connects trimming write in module in advance, trimming control module is used for output control signal to trimming write in module in advance, trimming output connection of trimming write in module in advance is to the control end of ADC module, be connected with each module of treating the trimming of ADC module, be used for outputting trimming control signal, this application image sensor chip level ADC trimming system is to system trimming write in advance, electric capacity mismatch trimming, power consumption trimming and error trimming, can effectively compensate performance parameter decline and power consumption overproof that factors such as process deviation mismatch, process angle skew arouse, promote ADC's key dynamic and static parameter, have very high practicality.
As shown in fig. 1, the trimming control module includes a serial NMOS switch array 10, a first self-biased current mirror 101, a second self-biased current mirror 102, an NMOS self-bias 103, a bias control resistor 104, a pull-down switch 105 and a reverse driver 106, one end of the serial NMOS switch array 10 is grounded, the other end is connected to the drain of the first self-biased current mirror 101, the gate of the serial NMOS switch array 10 is connected to a high level VDDThe effect is equivalent to a resistor, and the resistor can be used for replacing the function; the source of the first self-bias current mirror 101 is connected to the power supply VDDThe gate and drain of the first self-bias current mirror 101 are connected to the gate of the second self-bias current mirror 102, and the gate voltage V of the gate of the first self-bias current mirror 101 and the gate of the second self-bias current mirror 102A(ii) a The drain and gate of NMOS self-bias 103 are connected to the drain of second self-bias current mirror 102 and the drain of pull-down switch 105, and self-bias voltage VBThe source of the NMOS self-bias 103 is connected with one end of a bias control resistor 104, and the other end of the bias control resistor 104 is grounded; the gate of the pull-down switch 105 is connected to the output of the inversion driver 106, the input of the inversion driver 106 is the enable control signal ENP, and the source of the pull-down switch 105 is grounded.
As shown in fig. 2, the trimming pre-write module includes a plurality of trimming units with the same structure, the trimming units are connected in series, each trimming unit includes a flip-flop 11, an inverter 14, a gate 15, a PMOS transistor 107, an NMOS transistor 108, and a trimming resistor 109, and the trimming unit of the flip-flop 11
Figure BDA0003329943870000051
The input end of the phase inverter 14 is connected, the D end of the first trigger 11 is connected with the pre-written data Din, the output end Q of the first trigger 11 is connected with the D end of the next series trigger 11, each trigger is connected with a trigger control clock 12, and the trigger control clock 12 triggers a control signal CFUThe output terminal of the inverter 14 is connectedThe positive input end of the gate 15, the negative input end of the gate 15 is connected with the drain electrode of the PMOS tube 107 and the drain electrode of the NMOS tube 108, and the source electrode of the PMOS tube 107 is connected with the power supply VDDThe grid of the PMOS tube 107 is connected with the output bias voltage V of the trimming control moduleAThe source of the NMOS tube 108 is connected to one end of the trimming resistor 109, and the gate of the NMOS tube 108 is connected to the output bias voltage V of the trimming control moduleBThe other end of the trimming resistor 109 is grounded; gating 15 controls the gating path gate output F from signals S and SNunThe output end of the gate 15 is connected with a control port, namely a final trimming result, and the result controls an external working module, and the port is a unique control port no matter the application of the pre-trimming test or the actual trimming result; multiple trimming series unit outputs FU1～FunThe direct current control output can meet various application requirements.
When the circuit normally works, the enable control signal ENP is high at this time, the pull-down switch 105 is turned off, the series NMOS switch array 10 functions as a resistor, self-bias current is generated, and the gate voltage V is generated by mirroring the first self-bias current mirror 101 and the second self-bias current mirror 102AAnd a self-bias voltage VBAnd the module is used for controlling the trimming pre-writing module. Under normal operating conditions, the grid voltage VAAnd a self-bias voltage VBWill be used as the input control signal to the trimming pre-write module shown in fig. 2, where the bias control resistor 104(Rs) has a larger value and the trimming resistor has a lower resistance (generally m Ω), so that the self-bias voltage V is appliedBThe pull-down capability of the NMOS transistor 108 is much higher than the gate voltage VAFor the pull-up capability of 107, at the moment, the gating switch is controlled by S/SN to conduct negative input, the output value is low, and the low is a design default value; when the enable control signal ENP is low, the negative output of the recessive driver 106 is high, at which time the self-bias voltage V is highBIs pulled down to the ground, the NMOS tube 108 is disconnected, the gating switch is controlled by the S/SN to be conducted by the negative input, the output value is high, and F is realizedU1～FunAll are high, which is a measure that can skip physical laser trimming, and laser blowing of trimming resistors is not needed.
Output signal F of trimming unitU1～FunIs a DC signal, and is not used during the operation of the deviceAnd turning over, wherein the external connection end of the transistor is the grid end of a PMOS or NMOS transistor, and the intervention of the trimming capacitor, the adjustment of power consumption, the correction of voltage, the correction of offset, the correction of process angle deviation and the like are controlled in a long on/off mode.
The trimming control is realized by a trimming control module and a trimming and pre-writing module.
The trimming pre-write module shown in fig. 2 can further precisely position the trimming method; in the pre-write mode, the gate 15 is turned on by the S/SN control positive input terminal and at clock CFUUnder the trigger of the first clock edge, a pre-write level 0/1 is input by Din, and the pre-write control level is output to a final value FU1 in a negative direction through a trigger; on a second clock edge trigger, a second pre-write level 0/1 is input from Din, the first pre-write level being passed to F by flip-flop 13U2(ii) a On a third clock edge trigger, a third pre-write level 0/1 is input from Din, the first pre-write level is transferred to F through the flip-flopU3The second pre-write level is transferred to F through the flip-flopU4… …, such operations are repeated until the nth clock edge triggers, the nth pre-write level 0/1 is input by Din, which is passed to F by the flip-flopUnThe n-th pre-write level is transferred to F through the flip-flopU1And the pre-trimming design is completed. After the pre-trimming is finished, the performance of the whole circuit can be subjected to dynamic/static simulation verification, if the verification result does not reach the standard, n trimming levels are written again for verification, the final trimming result is determined after repeated iteration, and after the trimming result is confirmed, physical electrification laser trimming needs to be started.
The trimming pre-write module can realize two functions: trimming pre-writing and local trimming; when trimming and pre-writing, the 15-gate turns off the negative output to the output path, the clock is controlled by the FU end to be input, Din is the pre-designed high and low level, the register is read step by step, and F is controlledU1、FU2……FUnThe output of (1) is a pre-written value, the level of the first input is controlled by FUnLast write value control FU1. After pre-writing to determine which modules need to be burned off, the local trimming is performed by physically burning the end rn by the trimming device,and realizing the accurate trimming function.
The physical electric laser trimming is used for solidifying the prewritten result through trimming equipment, and the concrete operation is to Rf1～RfnPerforming laser trimming, and after any resistor is burned off, setting the negative input end of the gate corresponding to the trimming resistor in FIG. 2 high and setting the output end FUnThen it changes from a normal default low to high and a pre-trimmed circuit cure is achieved.
The trimming output is fed back to the system design, as shown in fig. 3, the trimming pre-write module 09(PFune) controls the trimming modules SH, first pipeline ADC stage, second ADC stage, third pipeline ADC stage, fourth pipeline ADC stage, first pipeline ADC stage and Reference module, as shown in fig. 4, the trimming design of the SH module is as shown in fig. 4, the negative output end switch capacitor banks (111-116) are three groups of compensation designs, the positive and negative symmetrical structures are provided, the first switch 111 and the first capacitor 112 are connected in series as one group, and the three groups are connected in parallel. The trimming design is mainly aimed at the offset error and gain error, when trimming is introduced, phi 1 is closed, 111/113/115 is kept on and off according to the trimming result and is connected to VCM, the switch is closed in the amplification stage 110, the jump voltage is VCM, the output value is used for operating the output end of the amplifier to realize offset correction, and the capacitance values of the capacitors (112, 114 and 116) are used as the process offset supplement. The trimming design of the first pipeline ADC stage is shown in FIG. 5, three groups of switch capacitor groups (118-123) are compensation designs of an amplifying capacitor 124, in the amplifying stage, the switches (118, 120 and 122) are kept on and off according to the trimming result and equal to the capacitance value increased by 124, and if closed-loop amplification factors at two ends are inconsistent, closed-loop gain consistency is realized by correcting the other end, and the SFDR of the system is improved. The power consumption of the system is modified as shown in FIG. 6, IoutFor bias current, normally PU1 and PU2 are turned off, Iout＝Iout1+Iout2Blowing R if increased power consumption is requiredf2Put PU2 high, then Iout＝Iout1+Iout2+Iout3(ii) a Blow R if needed to reduce power consumptionf1Put PU1 high, then Iout＝Iout1(ii) a Positive and negative regulation of power consumption is realized, and similarly, bias voltage and reference voltage can be controlled in the same wayThe output of (1) is offset.
The invention can effectively improve the performance parameter reduction and power consumption over-tolerance caused by the factors of process deviation mismatch, process angle deviation and the like caused by process deviation and design redundancy deficiency, and improve the key dynamic and static parameters of the ADC.
The correction of the invention is laser trimming correction, mainly aiming at various influences of system offset, capacitance mismatch, process deviation, temperature drift and the like, and compensating performance attenuation caused by negative influences of the system offset, the capacitance mismatch, the process deviation, the temperature drift and the like through proper resistance trimming. The trimming method can effectively compensate various influences such as system maladjustment, capacitance mismatch, process deviation, temperature drift and the like, is applied to a chip-level ADC IP of a CMOS image sensor, is a streamline ADC with 180nm, 14bit and 200Msps, and has the advantages that in an ADC test mode, before correction, the SNDR is 68.4dB, the SFDR is 82dB, the offset error is 40LSB, the gain error is 17mV, the total power consumption is 152mW, the PRUN of the sensor is 1.5 percent, and the read noise is 9.3 e-; after correction, the SNDR is 73.2dB, the SFDR is 94dB, the offset error is 14LSB, the gain error is 6.5mV, the total power consumption is 122mW, the sensor PRUN is 0.83%, the read noise is 7.5e-, and the performance of the system is greatly improved.
While the invention has been described in detail with reference to specific preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. The utility model provides an image sensor chip level ADC trimming system, its characterized in that includes trimming control module and trimming write-in module in advance, and trimming control module connects trimming write-in module in advance, and trimming control module is used for exporting control signal for trimming write-in module in advance, and the trimming output of trimming write-in module in advance is connected to the control end of ADC module, is connected with each module of waiting to revise of ADC module for export trimming control signal.
2. The ADC trimming system of claim 1, wherein the trimming control module comprises a series NMOS switch array (10), a first self-biased current mirror (101), a second self-biased current mirror (102), an NMOS self-bias (103), a bias control resistor (104), a pull-down switch (105) and a reverse driver (106), one end of the series NMOS switch array (10) is grounded, the other end of the series NMOS switch array is connected with a drain of the first self-biased current mirror (101), and a gate of the series NMOS switch array (10) is connected with a high level VDD(ii) a The source of the first self-bias current mirror (101) is connected with a power supply VDDThe grid and the drain of the first self-bias current mirror (101) are connected and then connected with the grid of the second self-bias current mirror (102), and the grid voltage V of the grid of the first self-bias current mirror (101) and the grid of the second self-bias current mirror (102)A(ii) a The drain electrode and the grid electrode of the NMOS self-bias (103) are connected with the drain electrode of the second self-bias current mirror (102) and the drain electrode of the pull-down switch (105), the source electrode of the NMOS self-bias (103) is connected with one end of a bias control resistor (104), and the other end of the bias control resistor (104) is grounded; the gate of the pull-down switch (105) is connected to the output of the reverse driver (106), and the source of the pull-down switch (105) is grounded.
3. The image sensor chip-scale ADC trimming system of claim 2, wherein the inverting driver (106) inputs the enable control signal ENP.
4. The ADC trimming system of claim 1, wherein the trimming pre-writing module comprises a plurality of trimming units with the same structure, and the trimming units are connected in series.
5. The ADC trimming system of claim 4, wherein the ADC trimming system comprises a signal generator, a signal processing circuit and a signal processing circuitThe trimming unit comprises a trigger (11), an inverter (14), a gate (15), a PMOS (P-channel metal oxide semiconductor) tube (107), an NMOS (N-channel metal oxide semiconductor) tube (108) and a trimming resistor (109), and the trigger (11) is
Figure FDA0003329943860000011
The output end Q of the first trigger (11) is connected with the D end of the next series trigger (11), the output end of the phase inverter (14) is connected with the positive input end of the gate (15), the negative input end of the gate (15) is connected with the drain electrode of the PMOS tube (107) and the drain electrode of the NMOS tube (108), and the source electrode of the PMOS tube (107) is connected with the power supply VDDThe grid of the PMOS tube (107) is connected with the output bias voltage V of the trimming control moduleAThe source electrode of the NMOS tube (108) is connected with one end of the trimming resistor (109), and the grid electrode of the NMOS tube (108) is connected with the output bias voltage V of the trimming control moduleBThe other end of the trimming resistor (109) is grounded; the gate (15) controls the gate path gate output F from the signals S and SNun。
6. The ADC trimming system of claim 5, wherein each flip-flop is connected to a trigger control clock (12), and the trigger control clock (12) triggers the control signal CFU。
7. The ADC trimming system of claim 5, wherein the trimming unit outputs signal FU1Fun is a DC signal.
8. The image sensor chip-scale ADC trimming system of claim 5, wherein the trimming circuit of the SH module: the negative output end and the positive output end are symmetrically provided with a switch capacitor set.
9. The image sensor chip-scale ADC trimming system of claim 8, wherein the switched capacitor bank comprises three sets of capacitors and switches connected in parallel, wherein the capacitors and switches in the same bank are connected in series.
10. The image sensor chip-level ADC trimming system of claim 7, wherein the output signal of the trimming unit is not inverted during the operation of the device, and the external connection terminal is a gate terminal of a PMOS or NMOS transistor, so as to control the intervention of the trimming capacitor, the adjustment of power consumption, the correction of voltage, the correction of offset and the correction of process corner deviation in a long on/off manner.
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