CN113872837B - Signal processing method, device and system - Google Patents
Signal processing method, device and system Download PDFInfo
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- CN113872837B CN113872837B CN202010614592.1A CN202010614592A CN113872837B CN 113872837 B CN113872837 B CN 113872837B CN 202010614592 A CN202010614592 A CN 202010614592A CN 113872837 B CN113872837 B CN 113872837B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
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Abstract
The application discloses a signal processing method, a device and a system. The method disclosed by the application comprises the following steps: detecting whether the potential of a port connected with the microprocessor changes; if yes, generating a receiving and sending switching control signal; and transmitting the receiving and transmitting switching control signal to an RS485PHY. The method can generate the receiving and sending switching control signal without completely receiving the data sent by the microprocessor, so the delay time of the communication system is reduced to a certain degree; because the data does not need to be completely received, a logic circuit capable of completely receiving the data does not need to be realized by using a logic device, so that the data forwarding logic is simplified, meanwhile, the logic circuit can be realized by using a lower clock, and the circuit cost is also reduced. Accordingly, the signal processing device and the signal processing system disclosed by the application also have the technical effects.
Description
Technical Field
The present disclosure relates to the field of digital circuit technologies, and in particular, to a signal processing method, device and system.
Background
When the RS485 bus works in a half-duplex mode, the microprocessor can complete the switching of the receiving and sending control signals through the logic device. The specific process is as follows: after the microprocessor configures baud rate, character structure and other information to the logic device, the logic device firstly and completely receives data sent by the microprocessor, and then serializes the data, and simultaneously generates a receiving and transmitting switching control signal and sends the receiving and transmitting switching control signal to the RS485PHY.
The process has the following disadvantages: because the data sent by the microprocessor needs to be completely received to generate the receiving and sending switching control signal, the delay of the communication system is larger, and the whole implementation logic is more complex; the logic circuit capable of completely receiving data by using the logic device needs to use a high-power clock, and in a high-baud rate scene, the high-power clock has higher requirements on the logic device, so that the cost for realizing the logic circuit is higher.
Therefore, how to generate the transceiving switching control signal in time and simplify the data forwarding logic is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a signal processing method, device and system, and a method and system for generating a transmit/receive switching control signal to simplify a data forwarding logic. The specific scheme is as follows:
in a first aspect, the present application provides a signal processing method, including:
detecting whether the potential of a port connected with the microprocessor changes;
if yes, generating a receiving and sending switching control signal;
and transmitting the receiving and transmitting switching control signal to an RS485PHY.
Preferably, the transmitting the transceiving switching control signal to the RS485PHY includes:
and transmitting the transceiving switching control signal to the RS485PHY through a delay circuit for holding the transceiving switching control signal.
Preferably, the delay time of the delay circuit is determined according to the transmission time of the character transmitted by the current communication system.
Preferably, the delay time of the delay circuit is determined according to the maximum character transmission time supported by the current communication system.
Preferably, after transmitting the transceiving switching control signal to the RS485PHY, the method further includes:
oversampling the signal sent by the microprocessor to obtain a sampling signal;
carrying out edge detection on the sampling signal to obtain edge information;
if the edge information comprises a data start bit, performing phase shift compensation on data sent by the microprocessor by using the data start bit to obtain a compensation signal;
transmitting the compensation signal to the RS485PHY.
Preferably, the oversampling a signal transmitted by the microprocessor to obtain a sampled signal includes:
oversampling the signal by using a clock of N times of the highest baud rate supported by the current communication system to obtain the sampled signal; n is not less than 3.
Preferably, after performing edge detection on the sampling signal and obtaining edge information, the method further includes:
and if the current sampling rate meets the service requirement of the current communication system, performing phase shift compensation on the data sent by the microprocessor by using a shift register to obtain the compensation signal, and transmitting the compensation signal to the RS485PHY.
In a second aspect, the present application provides a signal processing apparatus comprising:
the detection module is used for detecting whether the potential of a port connected with the microprocessor changes;
the generating module is used for generating a receiving and transmitting switching control signal if the potential of the port changes;
and the transmission module is used for transmitting the receiving and sending switching control signal to the RS485PHY.
In a third aspect, the present application provides a signal processing system comprising: microprocessor, RS485PHY and above-mentioned signal processing device.
According to the above scheme, the present application provides a signal processing method, including: detecting whether the potential of a port connected with the microprocessor changes; if yes, generating a receiving and sending switching control signal; and transmitting the receiving and transmitting switching control signal to an RS485PHY.
Therefore, when the method detects that the potential of the port connected with the microprocessor changes, the method immediately generates a receiving and transmitting switching control signal, and then transmits the receiving and transmitting switching control signal to the RS485PHY, so that the RS485PHY enters a transmitting state, namely: and after receiving the data sent by the microprocessor, the RS485PHY forwards the data to the RS485 bus. The method can generate the receiving and sending switching control signal without completely receiving the data sent by the microprocessor, so the delay time of the communication system is reduced to a certain degree; because the data does not need to be completely received, a logic circuit capable of completely receiving the data does not need to be realized by using a logic device, so that the data forwarding logic is simplified, meanwhile, the logic circuit can be realized by using a lower clock, and the circuit cost is also reduced.
Accordingly, the signal processing device and the signal processing system provided by the application also have the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a signal processing method disclosed herein;
FIG. 2 is a flow chart of another signal processing method disclosed herein;
FIG. 3 is a schematic diagram of a signal processing apparatus disclosed herein;
FIG. 4 is a schematic diagram of a signal processing system according to the present disclosure;
FIG. 5 is a prior art schematic illustration of the present disclosure;
fig. 6 is another prior art schematic disclosed herein.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, because the data sent by the microprocessor needs to be completely received to generate a receiving and sending switching control signal, the delay of a communication system is larger, and the whole implementation logic is more complex; the logic circuit capable of completely receiving data by using the logic device needs to use a high-power clock, and in a high-baud rate scene, the high-power clock has higher requirements on the logic device, so that the cost for realizing the logic circuit is higher. Therefore, the signal processing scheme is provided, the receiving and sending switching control signal can be generated in time, and the data forwarding logic is simplified.
Referring to fig. 1, an embodiment of the present application discloses a signal processing method, including:
s101, detecting whether the potential of a port connected with a microprocessor changes; if yes, executing S102; if the number of the user terminal is not the same as the preset number, no operation is performed;
it should be noted that the method disclosed in this embodiment may be implemented based on a logic device. Logic devices such as: CPLD (Complex Programmable Logic Device), FPGA (Field-Programmable Gate Array), and the like.
In fact, it is detected that the potential of the port connected to the microprocessor has changed, that is, any edge of the data sent by the microprocessor (including the data start bit and others) is detected. Before the microprocessor sends data, the microprocessor always sends a data start bit, so that the logic device detects the edge of the data start bit and then generates a receiving and sending switching control signal; and then in the data transmission process, if any edge is detected, the receiving and transmitting switching control signal is continuously generated, so that the DE port of the RS485PHY keeps high level in the whole data transmission process.
If the transceiving switching control signal is generated when an edge other than the start bit of data is detected, the transceiving switching control signal actually generated may be longer than the character length of the transmitted data by at least 1 character length, which is the simplest to implement but may decrease the communication efficiency. If the transmit/receive switching control signal is generated only when the first falling edge of the start bit of the data is detected, the generated transmit/receive switching control signal can be matched with the character length of the actually transmitted data, so that the start bit needs to be identified, but the communication efficiency is highest.
The microprocessor sends a signal to the logic device by using a Universal Asynchronous Receiver/Transmitter (UART).
And S102, generating a receiving and transmitting switching control signal.
And S103, transmitting the receiving and transmitting switching control signal to an RS485PHY.
In one embodiment, transmitting the transceiving switching control signal to the RS485PHY includes: and transmitting the receiving and transmitting switching control signal to the RS485PHY through a delay circuit for keeping the receiving and transmitting switching control signal. The delay circuit is configured to maintain a transmit/receive switching control signal, maintain a DE port of the RS485PHY at a high level if the RS485PHY needs to receive data transmitted by the microprocessor, and maintain a RE (Receiver Output Enable) port of the RS485PHY at a low level if the RS485PHY needs to transmit data to the microprocessor. The delay time period of the delay circuit is a time period in which the DE port or/RE port is kept at a high level.
The data forwarding logic of this embodiment is: the microprocessor sends data to the RS485PHY through the logic device, the RS485PHY receives the data sent by the microprocessor after entering a sending state and sends the data to the RS485 bus, and the other end of the RS485 bus is connected with other equipment. And after the RS485PHY enters a receiving state, the RS485PHY receives data sent by other equipment through the RS485 bus and directly sends the received data to the microprocessor.
In one embodiment, the delay time of the delay circuit is determined according to the transmission time of the character transmitted by the current communication system. In one embodiment, the delay time of the delay circuit is determined according to the maximum character transmission time supported by the current communication system. Specifically, the delay time period of the delay circuit is usually set to 1 to 1.5 times the character transmission time period transmitted by the current communication system or the maximum character transmission time period supported by the current communication system. Where character transmission duration = single symbol width x number of symbols (i.e. character length).
Assuming that the current communication system supports Modbus serial bus communication, an RTU mode is adopted, the length of a character is 11 bits (each character of the RTU mode comprises 1start bit, 8data bits, 1parity bit and 1stop bit, and then the format is 1startbit +8databits +1paritybit + 1stopbit), and the supported baud rate is 19.2Kbps (symbol width 52.083 us) and 115.2Kbps (8.681 us). The delay for 19.2Kbps may be chosen to be 677.079us (52.083 x 13) and the delay for 115.2Kbps may be chosen to be 112.853us (8.681 x 13). According to specific user or system requirements, 677.079us can be uniformly used for delaying two baud rates, so that the design is simplified.
In order to avoid the situation that the data transmitted by the microprocessor reaches the RS485PHY before the receiving and transmitting switching control signal, so that the code element is lost and the data is incomplete, the data transmitted by the microprocessor can be subjected to phase shift compensation, so that a compensation signal can be obtained, and the compensation signal can reach the RS485PHY later than the receiving and transmitting switching control signal. Specifically, the phase shift compensation is performed on the data sent by the microprocessor, so that not only can the delay introduced when the receiving and sending switching control signal is generated be compensated, but also the time required for driving the DE port of the RS485PHY can be compensated.
In one embodiment, after transmitting the transceiving switching control signal to the RS485PHY, the method further includes: oversampling a signal sent by the microprocessor to obtain a sampling signal; carrying out edge detection on the sampling signal to obtain edge information; if the edge information comprises a data start bit, performing phase shift compensation on data sent by the microprocessor by using the data start bit to obtain a compensation signal; the compensation signal is transmitted to the RS485PHY.
Referring to fig. 2, fig. 2 is another signal processing method provided in this embodiment, the method includes:
s201, oversampling is carried out on the signal sent by the microprocessor to obtain a sampling signal;
s202, carrying out edge detection on the sampling signal to obtain edge information;
s203, if the edge information comprises a data start bit, performing phase shift compensation on data sent by the microprocessor by using the data start bit to obtain a compensation signal;
and S204, transmitting the compensation signal to an RS485PHY.
Specifically, the edge information may indicate a transition of the signal, such as: high/low levels of the signal, signal edges, data start bits of the signal, signal waveforms, etc. The data start bit of the signal, i.e. the bit representing the start bit before the particular data is sent, when this bit appears, indicates to the microprocessor to start sending data. Therefore, when the data start bit is detected, the transceiving switching control signal can be generated and transmitted to the RS485PHY, and the DE (Driver Output Enable) port of the RS485PHY is pulled up.
Suppose that the current communication system uses RS485 for communication, the baud rate is 1Mbps, and the PHY uses MAX485, which is Maxim. If a clock with 4 times baud rate of 4MHz is used for processing, a transmitting signal of a UART (universal asynchronous receiver/transmitter) included in a microprocessor is synchronized across clock domains, and then edge detection is carried out, so that a receiving and transmitting switching control signal is generated. This process requires 3 clock cycles, i.e., 750ns. Since the phase relationship between the processing clock and the data transmitted by the UART is random, there may be 1-2 clock ambiguities, assuming an ambiguity time of 500ns. If the transceiving switching control signal generation process adopts a delay counter cleared by an edge signal, the transceiving switching control signal is generated based on the delay counter, and the process may require 2 clock cycles, namely 500ns. While the MAX485 driver enabled maximum delay is 70ns. Then the delay time from transmit-receive switching control signal generation and RS485PHY driver enable is 750ns +500ns +70ns =1820ns, which is about 8 clock cycles. But the time actually needed for compensation needs to be determined according to the actually adopted signal compensation scheme.
If the edge information comprises a data start bit, the data sent by the microprocessor can be subjected to phase shift compensation in a waveform recording mode. For example: the 4MHz clock is adopted for processing, the sampling rate is low, so the signal compensation scheme can adopt the following modes:
recording a waveform: starting counting (a time delay counter can be multiplexed) by taking the detected falling edge of the data start bit as a timing starting point (marked as t 0), and recording the edge detection result until the generated transceiving switching control signal is invalid, so that the waveform of the UART transmitting signal can be obtained.
Waveform shaping and regeneration output: assume that the recorded waveform is "101 …", where the first 1 to 0 falling edge is the falling edge of the start bit, which is time t 0. Since the 4MHz processing clock is 4 times the 1Mbps baud rate, there will be 4 samples per symbol. In the ideal case, a rising edge of 0 to 1 will occur at time t 4. This rising edge may also occur at time t3 or t5 due to the randomness of the phase relationship of the sampling clock and the signal transmitted by the UART. Since the same cross-clock domain synchronization and edge detection are performed, only 500ns of the processing time generated by the transceiving control signal and 70ns of the MAX485 driver enable maximum delay need to be compensated, plus 250ns of one clock cycle margin. The falling edge recorded at time t0 can be output at time t4, the rising edge recorded at time t4 (or t3 or t 5) can be output at time t8, and the recorded waveforms can be shaped and output in the same way.
In a specific embodiment, the method further comprises the following steps: and if the current sampling rate meets the service requirement of the current communication system, performing phase shift compensation on the data sent by the microprocessor by using the shift register to obtain a compensation signal, and transmitting the compensation signal to the RS485PHY. The phase shift compensation of the data by using the shift register does not depend on the data start bit, so that if the data start bit is not detected and the current sampling rate meets the service requirement of the current communication system, the phase shift compensation of the data can be performed by using the shift register. Of course, when the start bit of data is detected and the current sampling rate meets the traffic requirement of the current communication system, the shift register may also be used to perform phase shift compensation on the data.
Specifically, if an error possibly introduced by the current sampling rate is within an allowable range of a protocol adopted by the current communication system, it is indicated that the current sampling rate meets the service requirement of the current communication system, and then the current scene can be regarded as a high-sampling-rate scene, and the shift register is directly used for performing phase shift compensation on data sent by the microprocessor. This is simpler and easier to implement.
For example: if a 50MHz high-power clock is used for processing, and the requirement for symbol width error is not particularly high (the 50MHz processing clock introduces a maximum error of 4% relative to the 1Mbps baud rate), the signal compensation scheme of UART transmission can be more simplified. For example, after clock domain crossing synchronization, the clock domain crossing synchronization may be performed after the clock domain crossing synchronization is performed, and the clock domain crossing synchronization may be performed after the clock domain crossing synchronization is performed. Therefore, the edge detection time needs to be compensated for by 20ns, the clock ambiguity needs to be compensated for by 40ns, the transceiving control signal generates by 40ns, the MAX485 driver enables the maximum delay to be 70ns, and a cycle margin is added by 20ns, so that a shift register with 10 stages is adopted. Because the performance of the logic devices is good now, and hundreds of megabits of sequential logic can be run, higher clock processing can be used.
In one embodiment, oversampling a signal transmitted by the microprocessor to obtain a sampled signal includes: oversampling the signal by using a clock of N times of the highest baud rate supported by the current communication system to obtain a sampled signal; n is not less than 3.
It should be noted that, if a logic circuit capable of completely receiving data is implemented by using a logic device, oversampling is usually performed by using an 8-time clock or a 16-time clock of the highest baud rate supported by the current communication system, and oversampling can be performed by using a 3-time clock of the highest baud rate supported by the current communication system in this embodiment. The higher the clock multiple, the higher the sampling rate and the higher the performance of the logic devices required to implement the circuit.
Therefore, the embodiment can generate the receiving and sending switching control signal without completely receiving the data sent by the microprocessor, so that the delay time of the communication system is reduced to a certain extent; because the data does not need to be completely received, a logic circuit capable of completely receiving the data does not need to be realized by using a logic device, so that the data forwarding logic is simplified, meanwhile, the logic circuit can be realized by using a lower clock, and the circuit cost is also reduced.
In the following, a signal processing apparatus provided by an embodiment of the present application is described, and a signal processing apparatus described below and a signal processing method described above may be referred to with each other.
Referring to fig. 3, an embodiment of the present application discloses a signal processing apparatus, including:
a detection module 301, configured to detect whether a potential of a port connected to the microprocessor changes;
a generating module 302, configured to generate a transceiving switching control signal if a potential of a port changes;
and a transmission module 303, configured to transmit the transceiving switching control signal to the RS485PHY.
In a specific embodiment, the transmission module is specifically configured to:
and transmitting the receiving and transmitting switching control signal to the RS485PHY through a delay circuit for keeping the receiving and transmitting switching control signal.
In one embodiment, the delay time of the delay circuit is determined according to the transmission time of the character transmitted by the current communication system.
In one embodiment, the delay time of the delay circuit is determined according to the maximum character transmission time supported by the current communication system.
In a specific embodiment, the method further comprises the following steps:
the sampling module is used for oversampling the signal sent by the microprocessor to obtain a sampling signal;
the detection module is used for carrying out edge detection on the sampling signal to obtain edge information;
the first compensation module is used for performing phase shift compensation on data sent by the microprocessor by using the data start bit to obtain a compensation signal if the edge information comprises the data start bit;
and the transmission module is used for transmitting the compensation signal to the RS485PHY.
In an embodiment, the sampling module is specifically configured to:
oversampling the signal by using a clock of N times of the highest baud rate supported by the current communication system to obtain a sampled signal; n is not less than 3.
In a specific embodiment, the method further comprises the following steps:
and the second compensation module is used for performing phase shift compensation on the data sent by the microprocessor by using the shift register to obtain a compensation signal and transmitting the compensation signal to the RS485PHY if the current sampling rate meets the service requirement of the current communication system.
For more specific working processes of each module and unit in this embodiment, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not described here again.
Therefore, the embodiment provides a signal processing device, which can generate the transceiving switching control signal without completely receiving the data sent by the microprocessor, so that the delay time of the generation and the sending of the transceiving switching control signal is reduced to a certain extent; because the data does not need to be completely received, a logic circuit capable of completely receiving the data does not need to be realized by using a logic device, so that the data forwarding logic is simplified, meanwhile, the logic circuit can be realized by using a lower clock, and the circuit cost is also reduced.
In the following, a signal processing system provided by an embodiment of the present application is introduced, and a signal processing system described below and a signal processing method and device described above may be referred to each other.
Referring to fig. 4, an embodiment of the present application discloses a signal processing system, including: microprocessor, RS485PHY, and signal processing means (i.e., logic devices shown in fig. 4).
In this embodiment, the system may use HDLC (High Level Data Link Control) or Modbus to perform communication. Of course, other protocols may be utilized for communication. Among them, HDLC is a typical representative of bit-oriented data link control protocol, and Modbus is an industry standard of industrial field communication protocol.
In fig. 4, a PHY (Port Physical Layer) is a Port Physical Layer interface chip. UART TX denotes a Transmit port, TX, transmit. UART RX denotes a receiving port, RX, receive. DI (Driver Input) is the Driver Input. RO (Receiver Output) is the Receiver Output. A is the non-inverting receiver input and the non-inverting driver output defined in the TIA/EIA-485 standard. B is the inverted receiver input and the inverted driver output defined in the TIA/EIA-485 standard. A and B are connected with an RS485 bus.
The data forwarding logic of the architecture of fig. 4 is: the micro-processing sends data to the RS485PHY through the logic device, after the RS485PHY enters a sending state, the RS485PHY receives the data sent by the micro-processing and sends the data to the RS485 bus, and the other end of the RS485 bus is connected with other equipment. After the RS485PHY enters a receiving state, the RS485PHY receives data sent by other equipment through an RS485 bus and directly sends the received data to the microprocessor.
It should be noted that, in this embodiment, configuration information required for implementing a logic circuit capable of completely receiving data, such as a baud rate, a character structure (for example, several data bits), a configuration of parity bits (parity, even parity, or no parity), a stop bit configuration, and the like, need not be configured. Only the baud rate and character length need be known. In this embodiment, only the baud rate and the character length need to be configured for the logic device, and therefore, the implementation can be realized by using a General Purpose Input/Output (GPIO) interface as a General Purpose Input/Output interface.
Therefore, the configuration information of the microprocessor to the logic device is less in the embodiment, and the logic device can generate the receiving and sending switching control signal without completely receiving the data sent by the microprocessor, so that the data forwarding logic is simplified, meanwhile, a logic circuit can be realized by using a lower clock, and the circuit cost is also reduced.
In order to clearly show the technical effects of the present application, the present application is compared with the prior art in detail.
Referring to fig. 5, the data forwarding logic of the conventional architecture shown in fig. 5 is: after the microprocessor configures more information such as baud rate, character structure, parity check bit configuration, stop bit configuration and the like to the logic device, the logic device firstly and completely receives data sent by the microprocessor, then serializes the data, and simultaneously generates a receiving and transmitting switching control signal and sends the receiving and transmitting switching control signal to the RS485PHY. It can be seen that, in the prior art shown in fig. 5, the data sent by the microprocessor needs to be completely received to generate the transceiving switching control signal, so that the delay of the communication system is large, and the whole implementation logic is complex. However, the logic circuit capable of completely receiving data by using the logic device needs to use a high-power clock, and the high-power clock has a high requirement on the logic device in a high-baud rate scenario, so that the cost for realizing the logic circuit is high.
Compared with the prior art shown in fig. 5, the delay time of the communication system is reduced to a certain extent, the data forwarding logic is simplified, and meanwhile, the logic circuit can be realized by using a lower clock, and the circuit cost is also reduced.
Referring to fig. 6, the data forwarding logic of the conventional architecture shown in fig. 6 is: the microprocessor configures more information such as baud rate, character structure, parity check bit configuration, stop bit configuration and the like to the logic device, the microprocessor sends data to be sent to the logic device through a microprocessor interface, the logic device splits the data based on a physical layer protocol, generates a receiving and sending switching control signal, and sends the split data and the receiving and sending switching control signal to the RS485PHY. It can be seen that, in the prior art shown in fig. 6, the logic device also needs to receive the transmitted data completely to generate the transceiving switching control signal, so that the delay of the communication system is large, and the whole implementation logic is complex. Moreover, the implementation process of the microprocessor interface in fig. 6 is complex, and the implementation cost is also high. If a parallel microprocessor interface is implemented, more pins need to be arranged at the interface, and the increase of the pins increases the cost and the wiring area is more tense. If a serial microprocessor interface is implemented, the delay is relatively large because there is a large amount of data to be transmitted (including configuration information and data to be transmitted).
Compared with the prior art shown in fig. 6, the delay time of the communication system is reduced to a certain extent, pins are saved, the wiring area is saved, the data forwarding logic is simplified, meanwhile, a logic circuit can be realized by using a lower clock, and the circuit cost is also reduced.
References in this application to "first," "second," "third," "fourth," etc., if any, are intended to distinguish between similar elements and not necessarily to describe a particular order or sequence. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, or apparatus.
It should be noted that the descriptions in this application referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (8)
1. A signal processing method, comprising:
detecting whether the potential of a port connected with the microprocessor changes;
if yes, generating a receiving and sending switching control signal;
transmitting the receiving and transmitting switching control signal to an RS485 PHY;
wherein, after transmitting the transceiving switching control signal to the RS485PHY, the method further includes:
oversampling the signal sent by the microprocessor to obtain a sampling signal;
carrying out edge detection on the sampling signal to obtain edge information;
if the edge information comprises a data start bit, performing phase shift compensation on data sent by the microprocessor by using the data start bit to obtain a compensation signal;
transmitting the compensation signal to the RS485PHY.
2. The signal processing method according to claim 1, wherein the transmitting the transmission/reception switching control signal to an RS485PHY comprises:
and transmitting the receiving and transmitting switching control signal to the RS485PHY through a delay circuit for keeping the receiving and transmitting switching control signal.
3. The signal processing method of claim 2, wherein the delay time period of the delay circuit is determined according to a transmission time period of a character transmitted by a current communication system.
4. The signal processing method of claim 2, wherein the delay time of the delay circuit is determined according to a maximum character transmission time supported by a current communication system.
5. The signal processing method according to any one of claims 1 to 4, wherein the oversampling the signal transmitted by the microprocessor to obtain a sampled signal comprises:
oversampling the signal by using a clock of N times of the highest baud rate supported by the current communication system to obtain the sampled signal; n is not less than 3.
6. The signal processing method according to any one of claims 1 to 4, wherein after performing edge detection on the sampled signal to obtain edge information, the method further comprises:
and if the current sampling rate meets the service requirement of the current communication system, performing phase shift compensation on the data sent by the microprocessor by using a shift register to obtain the compensation signal, and transmitting the compensation signal to the RS485PHY.
7. A signal processing apparatus, characterized by comprising:
the detection module is used for detecting whether the potential of a port connected with the microprocessor changes;
the generating module is used for generating a receiving and transmitting switching control signal if the potential of the port changes;
the transmission module is used for transmitting the receiving and transmitting switching control signal to the RS485 PHY;
wherein, still include:
the sampling module is used for oversampling the signal sent by the microprocessor to obtain a sampling signal;
the detection module is used for carrying out edge detection on the sampling signal to obtain edge information;
the first compensation module is used for performing phase shift compensation on data sent by the microprocessor by using the data start bit to obtain a compensation signal if the edge information comprises the data start bit;
and the transmission module is used for transmitting the compensation signal to the RS485PHY.
8. A signal processing system, comprising: a microprocessor, an RS485PHY, and the apparatus of claim 7.
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| DE19853897A1 (en) * | 1998-11-23 | 2000-05-25 | Bosch Gmbh Robert | Procedure for compensation of phase delays in circuits for conversion of analogue signals into digital signals is by consideration of the sampling signal of the previous sampling period |
| CN101719112A (en) * | 2009-11-19 | 2010-06-02 | 北京东方信联科技有限公司 | Half-duplex automatic receiving-transmitting switching circuit of RS485 |
| CN102142951A (en) * | 2011-01-07 | 2011-08-03 | 天津天地伟业数码科技有限公司 | Reversing control structure of RS485 transceiver chip and control method thereof |
| CN104317762A (en) * | 2014-10-28 | 2015-01-28 | 北京四方继保自动化股份有限公司 | Method for adaptively controlling transmitting and receiving directions of RS485 chip by aid of FPGA (field programmable gate array) |
| CN105159194A (en) * | 2015-08-25 | 2015-12-16 | 天津市英贝特航天科技有限公司 | Switching circuit and switching method for switching data receiving/sending operation of RS-485 serial port |
| JP6632432B2 (en) * | 2016-03-09 | 2020-01-22 | 三菱電機株式会社 | Communication device and start-stop synchronization communication method |
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