CN113871456B - LDMOS device and forming method thereof - Google Patents
LDMOS device and forming method thereof Download PDFInfo
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
An LDMOS device and a forming method thereof, wherein the method comprises the following steps: forming a field oxide layer on the surface of the deep well region, wherein the field oxide layer comprises a field oxide region and a beak region positioned at one end of the field oxide region along the first direction, the beak region is positioned on the surface of the first diffusion region, part of the field oxide region is positioned on the surface of the second diffusion region, the field oxide layer has a third dimension along the first direction, the ratio of the first distance to the third dimension is less than or equal to 30%, the ratio of the second distance to the third dimension is 20% to 80%, and after the field oxide layer is formed, a body region with a first conductivity type is formed in the first doped region; and forming a grid electrode on part of the surface of the field oxide layer, wherein the grid electrode also extends to part of the surface of the body region, and different target breakdown voltage performances can be realized by selecting different first distances and second distances.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS device and a forming method thereof.
Background
An LDMOS device (Lateral Double-diffusion metal oxide semiconductor field effect transistor) in the high-voltage power device has good process compatibility with a CMOS device due to the characteristic that current transversely flows on the surface of the device. Meanwhile, compared with the traditional power device, the LDMOS device is widely applied due to the good characteristics of high breakdown voltage and low on-resistance.
In LDMOS devices, the Off-breakdown voltage (Off-BV) and the On-breakdown voltage (On-BV) are important indicators. The off-state breakdown voltage and the on-state breakdown voltage have a great relation with the doping concentration of the drift region of the device, however, because the positions of the strongest points of impact ionization are different between the on-state breakdown and the off-state breakdown of the device, the existing means are difficult to simultaneously meet the requirements of improving the off-state breakdown voltage and the on-state breakdown voltage.
The semiconductor structure formed by the existing LDMOS device technology needs to be further improved.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an LDMOS device and a forming method thereof, so as to improve the performance of the formed device.
In order to solve the technical problems, the technical scheme of the invention provides an LDMOS device, which comprises: a substrate having a first conductivity type; the deep well region comprises a first doped region, a second doped region, a third doped region, a first diffusion region, a second diffusion region, a first distance, and a second distance, wherein the first doped region, the second doped region, the third doped region, the second doped region, the first diffusion region, the second diffusion region and the third doped region are arranged along a first direction, two sides of the first doped region are respectively contacted with the first doped region and the second doped region, two sides of the second diffusion region are respectively contacted with the second doped region and the third doped region, the deep well region is provided with a second conductive type, the second conductive type is opposite to the first conductive type, a first distance is reserved between the first doped region and the second doped region, and a second distance is reserved between the second doped region and the third doped region along the first direction; the field oxide layer is positioned on the surface of the deep well region, comprises a field oxide region and a beak region positioned at one end of the field oxide region along the first direction, the beak region is positioned on the surface of the first diffusion region, part of the field oxide region is positioned on the surface of the second diffusion region, the field oxide layer has a third dimension along the first direction, the ratio of the first distance to the third dimension is less than or equal to 30%, and the ratio of the second distance to the third dimension is 20% -80%; a body region within the first doped region, the body region having a first conductivity type; the grid electrode is positioned on part of the surface of the field oxide layer and also extends to part of the surface of the body region; a source and a drain within the substrate, the source and the drain having a second conductivity type, the source being within the body region on the gate side, the drain being within the third doped region on the field oxide layer side; a channel extraction region within the body region, the channel extraction region having a first conductivity type, and the channel extraction region being remote from the field oxide layer relative to the source.
Correspondingly, the technical scheme of the invention also provides a method for forming the LDMOS device, which comprises the following steps: providing a substrate, wherein the substrate has a first conductivity type; forming a deep well region in the substrate, wherein the deep well region comprises a first doped region, a second doped region, a third doped region, a first diffusion region, a second diffusion region, a first distance, a second distance and a third distance, the first doped region, the second doped region and the third doped region are arranged along a first direction, the second doped region, the third doped region and the first diffusion region are arranged along the first direction, two sides of the first doped region are respectively contacted with the first doped region and the second doped region, two sides of the second diffusion region are respectively contacted with the second doped region and the third doped region, the deep well region is provided with a second conductivity type, the second conductivity type is opposite to the first conductivity type, a first distance is reserved between the first doped region and the second doped region along the first direction, and a second distance is reserved between the second doped region and the third doped region; forming a field oxide layer on the surface of the deep well region, wherein the field oxide layer comprises a field oxide region and a beak region positioned at one end of the field oxide region along the first direction, the beak region is positioned on the surface of the first diffusion region, part of the field oxide region is positioned on the surface of the second diffusion region, the field oxide layer has a third dimension along the first direction, the ratio of the first distance to the third dimension is less than or equal to 30%, and the ratio of the second distance to the third dimension is 20% -80%; forming a body region in the first doped region after forming the field oxide layer, wherein the body region has a first conductivity type; forming a grid electrode on part of the surface of the field oxide layer, wherein the grid electrode also extends to part of the surface of the body region; after the grid electrode is formed, a source electrode and a drain electrode in the substrate are formed, the source electrode and the drain electrode are of a second conduction type, the source electrode is located in the body region on one side of the grid electrode, and the drain electrode is located in the third doped region on one side of the field oxide layer.
Optionally, the method for forming the deep well region includes: implanting first doping ions into the substrate to form a first implantation region, a second implantation region and a third implantation region which are arranged along a first direction and are mutually separated, wherein the second implantation region is positioned between the first implantation region and the third implantation region; and driving the first doped ions to diffuse by adopting a high-temperature push-well process until the first injection region is contacted with the second injection region, the second injection region is contacted with the third injection region to form a deep well region, wherein the deep well region comprises a first doped region, a second doped region, a third doped region, a first diffusion region positioned between the first doped region and the second doped region, and a second diffusion region positioned between the second doped region and the third doped region, the first doped region is formed by the first injection region, the second doped region is formed by the second injection region, and the third doped region is formed by the third injection region.
Optionally, the forming method of the first implantation region, the second implantation region and the third implantation region further includes: forming a mask layer on the surface of the substrate, wherein the mask layer exposes part of the surface of the substrate; and implanting the first doping ions into the substrate by taking the mask layer as a mask.
Optionally, the implantation process parameters of the first doped ions include: the implantation energy ranges from 100KeV to 2000KeV, and the implantation dose ranges from 1E12 atoms per square centimeter to 1E13 atoms per square centimeter.
Optionally, the process parameters of the high-temperature push-trap process include: the temperature range of the pushing stage is 1000 ℃ to 1300 ℃, and the pushing time range is 200 minutes to 1000 minutes.
Optionally, the method further comprises: after forming the gate, a channel-out region within the body region is formed, the channel-out region having a first conductivity type, and the channel-out region being remote from the field oxide layer relative to the source.
Optionally, after forming the source electrode, the drain electrode and the channel extraction region, the method further includes: forming a dielectric layer on the surface of the substrate; and forming a conductive layer in the dielectric layer, wherein the conductive layer comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the first conductive layer is electrically connected with the channel leading-out area, the second conductive layer is electrically connected with the source electrode, the third conductive layer is electrically connected with the drain electrode, and the fourth conductive layer is electrically connected with the grid electrode.
Optionally, the first conductivity type is P-type, and the second conductivity type is N-type.
Optionally, the forming process of the field oxide layer includes a local oxidation isolation process.
Optionally, the third dimension ranges from 2 microns to 100 microns.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the method for forming the LDMOS device, the field oxide layer comprises a field oxide region and a beak region positioned at one end of the field oxide region, the beak region is positioned on the surface of the first diffusion region, part of the field oxide region is positioned on the surface of the second diffusion region, the field oxide layer has a third dimension along the first direction, the ratio range of the first distance to the third dimension is less than or equal to 30%, the ratio range of the second distance to the third dimension is 20% to 80%, the concentration of doped ions in the drift region below the beak region and below the field oxide region can be respectively adjusted by adjusting the first distance and the second distance, the concentration of the drift region positioned near the beak region can be reduced by increasing the first distance, the off-state breakdown voltage of the device can be improved, the concentration of the drain end of the drift region can be increased by reducing the second distance, the on-state breakdown voltage of the device can be improved, and further, different target breakdown voltages can be achieved by selecting different first distances and second distances.
Further, the first doped ions are driven to diffuse by a high-temperature push-well process until the first injection region is contacted with the second injection region and the second injection region is contacted with the third injection region to form a deep well region, and ion concentrations in the first diffusion region and the second diffusion region can be adjusted by adjusting the first distance, the second distance and the high-temperature push-well process, so that different target breakdown voltage performances can be realized.
According to the LDMOS device provided by the technical scheme of the invention, the field oxide layer comprises a field oxide region and a beak region positioned at one end of the field oxide region, the beak region is positioned on the surface of the first diffusion region, part of the field oxide region is positioned on the surface of the second diffusion region, the field oxide layer has a third dimension along the first direction, the ratio range of the first distance to the third dimension is less than or equal to 30%, the ratio range of the second distance to the third dimension is 20% to 80%, the concentration of doped ions in the drift region below the beak region and below the field oxide region can be respectively adjusted by adjusting the first distance and the second distance, the concentration of the drift region positioned near the beak region can be reduced by increasing the first distance, so that the off-state breakdown voltage of the device is improved, the concentration of the drain terminal of the drift region can be increased by reducing the second distance, and the on-state breakdown voltage of the device is improved, and further, different target breakdown voltages can be realized by different first distances and second distances.
Drawings
Fig. 1 is a schematic cross-sectional structure of an LDMOS device;
fig. 2 to 9 are schematic structural diagrams illustrating steps of a method for forming an LDMOS according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of devices formed using existing LDMOS technology is in need of improvement. The analysis will now be described in connection with an LDMOS device.
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1 is a schematic cross-sectional structure of an LDMOS device.
Referring to fig. 1, a schematic cross-sectional structure of an LDMOS device includes: a substrate 101; a deep well region 102 located within the substrate 101, the deep well region 102 having a first conductivity type; the field oxide layer 103 is positioned on the surface of the deep well region 102; a body region 104 located in the deep well region 102 at one side of the field oxide layer 103, the body region 104 having the second conductivity type; a drain electrode 105 located in the deep well region 102 at the other side of the field oxide layer 104, the drain electrode 105 having a first conductivity type; a polysilicon gate 105 located on the surface of the field oxide layer 103, the polysilicon gate 105 further extending to a portion of the surface of the body 104; a source 106 located in the body region 104 at one side of the polysilicon gate 105 and a channel-out region 107 adjacent to the source 106, the channel-out region 107 being remote from the field oxide layer 103 with respect to the source 106, the channel-out region 107 being of a second conductivity type, the source 106 being of a first conductivity type; a doped layer 108 located within the deep well region 102 below the field oxide layer 103, the doped layer 108 having a second conductivity type.
When the structure is used for NLDMOS devices, the first conductivity type is N type, and the second conductivity type is P type. The doped layer 108 is used to improve the off-state breakdown voltage of the device, but affects the on-state breakdown voltage of the device. Because the positions of the strongest points of impact ionization are different in the on-state breakdown and the off-state breakdown of the device, it is difficult to simultaneously meet the requirements of the on-state breakdown voltage and the on-state breakdown voltage by uniformly doping the implanted P-type doped layer 108.
In order to solve the above problems, in the method for forming an LDMOS device according to the present invention, the field oxide layer includes a field oxide region and a beak region located at one end of the field oxide region, and the beak region is located on the surface of the first diffusion region, and a part of the field oxide region is located on the surface of the second diffusion region, and the field oxide layer has a third dimension along the first direction, wherein a ratio of the first distance to the third dimension is in a range of 30% or less, and a ratio of the second distance to the third dimension is in a range of 20% to 80%, and by adjusting the first distance and the second distance, a concentration of dopant ions in a drift region below the beak region and below the field oxide region can be respectively adjusted, and by increasing the first distance, a concentration of drift region located near the beak region can be reduced. Thereby improving the off-state breakdown voltage of the device, reducing the second distance can increase the concentration of the drain terminal of the drift region so as to improve the on-state breakdown voltage of the device, and further, different target breakdown voltage performances can be realized by selecting different first distances and second distances.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 9 are schematic structural diagrams illustrating steps of a method for forming an LDMOS according to an embodiment of the invention.
Referring to fig. 2, a substrate 201 is provided, the substrate 201 having a first conductivity type.
In this embodiment, the material of the substrate 201 is silicon. In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
The first conductivity type includes P-type. In this embodiment, the first conductive type is P-type, and is used to form an N-type LDMOS device.
Subsequently, a deep well region in the substrate 201 is formed, where the deep well region includes a first doped region, a second doped region, a third doped region, a first diffusion region located between the first doped region and the second doped region, and a second diffusion region located between the second doped region and the third doped region, the first doped region, the second doped region, and the third doped region are separated from each other, the second doped region is located between the first doped region and the third doped region, two sides of the first diffusion region are respectively contacted with the first doped region and the second doped region, two sides of the second diffusion region are respectively contacted with the second doped region and the third doped region, the deep well region has a second conductivity type, the second conductivity type is opposite to the first conductivity type, a first distance is provided between the first doped region and the second doped region along the first direction, and a second distance is provided between the second doped region and the third doped region.
In this embodiment, please refer to fig. 3 to 4 for the method for forming the deep well region.
Referring to fig. 3, first doped ions are implanted into the substrate 201 to form a first implanted region 202, a second implanted region 203 and a third implanted region 204 which are arranged along a first direction X and are separated from each other, and the second implanted region 203 is located between the first implanted region 202 and the third implanted region 204.
In this embodiment, the method for forming the first implantation region 202, the second implantation region 203 and the third implantation region 204 further includes: forming a mask layer 205 on the substrate 201, wherein the mask layer 205 exposes three openings (not shown) arranged along the first direction X and separated from each other, and the three openings respectively expose the substrate surfaces on the first, second and third implantation regions 202, 203 and 204; first doping ions are implanted into the substrate 201 using the mask layer 205 as a mask.
The first implant region 202, the second implant region 203, and the third implant region 204 are used to form a deep well region. In this embodiment, the first doped ion is an N-type ion.
The implantation process parameters of the first doped ions comprise: the implantation energy ranges from 100KeV to 2000KeV, and the implantation dose ranges from 1E12 atoms per square centimeter to 1E13 atoms per square centimeter.
Referring to fig. 4, a high temperature push-well process is used to drive the first doped ions to diffuse until the first implanted region 202 contacts the second implanted region 203 and the second implanted region 203 contacts the third implanted region 204 to form a deep well region, wherein the deep well region includes a first doped region 206, a second doped region 207, a third doped region 208, a first diffusion region 209 between the first doped region 206 and the second doped region 207, and a second diffusion region 210 between the second doped region 207 and the third doped region 208, the first doped region 206 is formed by the first implanted region 202, the second doped region 208 is formed by the second implanted region 203, and the third doped region 209 is formed by the third implanted region 204.
The technological parameters of the high-temperature push-trap technology comprise: the temperature range of the pushing stage is 1000 ℃ to 1300 ℃, and the pushing time range is 200 minutes to 1000 minutes.
Adjusting the first distance m, the second distance n, and the high temperature push-well process may adjust the ion concentrations in the first diffusion region 209 and the second diffusion region 210, so as to achieve different target breakdown voltage performances.
Referring to fig. 5, a field oxide layer is formed on the surface of the deep well region, and along the first direction X, the field oxide layer includes a field oxide region 211B and a beak region 211A located at one end of the field oxide region 211B, wherein the beak region 211A is located on the surface of the first diffusion region 209, a portion of the field oxide region 211B is located on the surface of the second diffusion region 210, the field oxide layer has a third dimension z along the first direction X, a ratio of the first distance m to the third dimension z is less than or equal to 30%, and a ratio of the second distance n to the third dimension z is in a range of 20% to 80%.
The third dimension z ranges from 2 microns to 100 microns.
Subsequently, a body region is formed in the first doped region 209 and a drain is formed in the third doped region 208 on the field oxide layer side. The first diffusion region 209 and the second diffusion region 210 are used to form a partial drift region of the LDMOS device.
By adjusting the first distance m and the second distance m, the concentration of doped ions in the drift region below the beak region 211A and below the field oxide region 211B can be respectively adjusted, increasing the first distance m can reduce the concentration of the drift region near the beak region, thereby improving the off-state breakdown voltage of the device, reducing the second distance n can increase the concentration of the drain terminal of the drift region, thereby improving the on-state breakdown voltage of the device, and further, different target breakdown voltage performances can be realized by selecting different first distances m and second distances n.
The selected size ranges of the first distance m and the second distance n are related to the third dimension z-dimension.
The reason for selecting the ratio range of the first distance m to the third dimension z is that: if the first distance m is too large, the concentration of the drift region near the beak region 211A is too small, which results in too small an on-breakdown voltage.
The reason for selecting the ratio range of the second distance n to the third dimension z is that: if the second distance n is too large, the concentration of the drift region near the field oxide region 211B is too small, which results in too small on-state breakdown voltage, whereas if the second distance n is too small, the concentration of the drain terminal of the drift region is higher, which results in too small off-state breakdown voltage.
The process of forming the field oxide layer includes a local oxidation isolation process (local oxidation of silicon, LOCOS).
In this embodiment, an isolation layer 212 is also formed on a portion of the substrate surface. The isolation layer 212 is formed by a process including a partial oxidation isolation process.
The isolation layer 212 and the field oxide layer are used to isolate different device regions, and the isolation layer 212 and the field oxide layer expose a portion of the substrate surface, followed by forming an active region within the exposed substrate.
In this embodiment, the method for forming the field oxide layer and the isolation layer 212 includes: forming a masking layer (not shown) on the surface of the substrate 201, wherein the masking layer exposes a part of the surface of the substrate 201; forming the field oxide layer and the isolation layer 212 on the exposed surface of the substrate 201 by using a wet oxygen process; after forming the field oxide layer and the isolation layer 212, the masking layer is removed.
The material of the masking layer comprises silicon nitride; the materials of the field oxide layer and the isolation layer 212 include silicon oxide.
Referring to fig. 6, after the field oxide layer is formed, a body region 213 is formed in the first doped region 209, and the body region 213 has the first conductivity type.
In this embodiment, the first conductive type is P-type, and the body 213 is a P-type well.
Referring to fig. 7, a gate 215 is formed on a portion of the surface of the field oxide layer, and the gate 215 further extends to a portion of the surface of the body 213.
There is also a gate oxide layer 214 between the gate 215 and the substrate 201.
In this embodiment, the gate 215 is made of polysilicon. The gate oxide layer 214 is made of silicon oxide.
Referring to fig. 8, after the gate 215 is formed, a source 216 and a drain 217 in the substrate 201 are formed, the source 216 and the drain 217 have the second conductivity type, the source 216 is located in the body 213 at one side of the gate 215, and the drain 217 is located in the third doped region 208 at one side of the field oxide layer.
In this embodiment, the second conductivity type is N type, and is used to form an N type LDMOS device.
In this embodiment, after the gate 215 is formed, a channel-out region 218 is formed in the body region 213, the channel-out region 218 has the first conductivity type, and the channel-out region 218 is away from the field oxide layer with respect to the source 216.
In this embodiment, the channel-out region 218 is P-type.
In this embodiment, the channel-out region 218 and the source electrode 216 are respectively located in the body regions 213 at two sides of the isolation layer 212.
Referring to fig. 9, after forming the source 216, the drain 217 and the channel-out region 218, a dielectric layer (not shown) is further formed on the surface of the substrate 201; a conductive layer is formed within the dielectric layer, the conductive layer including a first conductive layer 219, a second conductive layer 220, a third conductive layer 221, and a fourth conductive layer 222, the first conductive layer 219 electrically coupled to the channel-out region 218, the second conductive layer 220 electrically coupled to the source 216, the third conductive layer 221 electrically coupled to the drain 217, and the fourth conductive layer 222 electrically coupled to the gate 215.
Accordingly, an embodiment of the present invention further provides an LDMOS device formed by the above method, please continue to refer to fig. 9, which includes: a substrate 201, the substrate 201 having a first conductivity type; a deep well region located in the substrate 201, the deep well region including a first doped region 206, a second doped region 207, a third doped region 208 arranged along a first direction X, a first diffusion region 209 located between the first doped region 206 and the second doped region 207, a second diffusion region 210 located between the second doped region 207 and the third doped region 208, the second doped region 207 being located between the first doped region 206 and the third doped region 208, the first diffusion region 209 being in contact with the first doped region 206 and the second doped region 207 on both sides, the second diffusion region 210 being in contact with the second doped region 207 and the third doped region 208 on both sides, the deep well region having a second conductivity type opposite to the first conductivity type, a first distance m being located between the first doped region 206 and the second doped region 207, and a second distance n being located between the second doped region 207 and the third doped region 208 along the first direction X; a field oxide layer located on the surface of the deep well region, wherein the field oxide layer includes a field oxide region 211B and a beak region 211A located at one end of the field oxide region 211B along the first direction X, and the beak region 211A is located on the surface of the first diffusion region 209, and a part of the field oxide region 211B is located on the surface of the second diffusion region 210, and the field oxide layer has a third dimension z along the first direction X, and a ratio of the first distance m to the third dimension z is in a range of less than or equal to 30%, and a ratio of the second distance n to the third dimension z is in a range of 20% to 80%; a body region 213 located within the first doped region 206, the body region 213 having a first conductivity type; a gate electrode 215 located on a portion of the surface of the field oxide layer, the gate electrode 215 further extending to a portion of the surface of the body region 213; a source 216 and a drain 217 within the substrate 201, the source 216 and the drain 217 having a second conductivity type, the source 216 being located within the body 213 on the gate 215 side, the drain 217 being located within the third doped region 208 on the field oxide layer side; a channel-out region 218 located within the body region 213, the channel-out region 218 having a first conductivity type, and the channel-out region 218 being remote from the field oxide layer relative to the source 216.
By adjusting the first distance m and the second distance n, the concentration of doped ions in the drift region below the beak region 211A and below the field oxide region 211B can be respectively adjusted, increasing the first distance m can reduce the concentration of the drift region near the beak region 211A, thereby improving the off-state breakdown voltage of the device, reducing the second distance n can increase the concentration of the drain terminal of the drift region, thereby improving the on-state breakdown voltage of the device, and further, different target breakdown voltage performances can be realized by selecting different first distances m and second distances n.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
1. An LDMOS device, comprising:
a substrate having a first conductivity type;
the deep well region comprises a first doped region, a second doped region, a third doped region, a first diffusion region, a second diffusion region, a first distance, and a second distance, wherein the first doped region, the second doped region, the third doped region, the second doped region, the first diffusion region, the second diffusion region and the third doped region are arranged along a first direction, two sides of the first doped region are respectively contacted with the first doped region and the second doped region, two sides of the second diffusion region are respectively contacted with the second doped region and the third doped region, the deep well region is provided with a second conductive type, the second conductive type is opposite to the first conductive type, a first distance is reserved between the first doped region and the second doped region, and a second distance is reserved between the second doped region and the third doped region along the first direction;
the field oxide layer is positioned on the surface of the deep well region, comprises a field oxide region and a beak region positioned at one end of the field oxide region along the first direction, the beak region is positioned on the surface of the first diffusion region, part of the field oxide region is positioned on the surface of the second diffusion region, the field oxide layer has a third dimension along the first direction, the ratio of the first distance to the third dimension is less than or equal to 30%, and the ratio of the second distance to the third dimension is 20% -80%;
a body region within the first doped region, the body region having a first conductivity type;
the grid electrode is positioned on part of the surface of the field oxide layer and also extends to part of the surface of the body region; a source and a drain within the substrate, the source and the drain having a second conductivity type, the source being within the body region on the gate side, the drain being within the third doped region on the field oxide layer side;
a channel extraction region within the body region, the channel extraction region having a first conductivity type, and the channel extraction region being remote from the field oxide layer relative to the source.
2. The method for forming the LDMOS device is characterized by comprising the following steps of:
providing a substrate, wherein the substrate has a first conductivity type;
forming a deep well region in the substrate, wherein the deep well region comprises a first doped region, a second doped region, a third doped region, a first diffusion region, a second diffusion region, a first distance, a second distance and a third distance, the first doped region, the second doped region and the third doped region are arranged along a first direction, the second doped region, the third doped region and the first diffusion region are arranged along the first direction, two sides of the first doped region are respectively contacted with the first doped region and the second doped region, two sides of the second diffusion region are respectively contacted with the second doped region and the third doped region, the deep well region is provided with a second conductivity type, the second conductivity type is opposite to the first conductivity type, a first distance is reserved between the first doped region and the second doped region along the first direction, and a second distance is reserved between the second doped region and the third doped region;
forming a field oxide layer on the surface of the deep well region, wherein the field oxide layer comprises a field oxide region and a beak region positioned at one end of the field oxide region along the first direction, the beak region is positioned on the surface of the first diffusion region, part of the field oxide region is positioned on the surface of the second diffusion region, the field oxide layer has a third dimension along the first direction, the ratio of the first distance to the third dimension is less than or equal to 30%, and the ratio of the second distance to the third dimension is 20% -80%;
forming a body region in the first doped region after forming the field oxide layer, wherein the body region has a first conductivity type;
forming a grid electrode on part of the surface of the field oxide layer, wherein the grid electrode also extends to part of the surface of the body region; after the grid electrode is formed, a source electrode and a drain electrode in the substrate are formed, the source electrode and the drain electrode are of a second conduction type, the source electrode is located in the body region on one side of the grid electrode, and the drain electrode is located in the third doped region on one side of the field oxide layer.
3. The method for forming an LDMOS device of claim 2, wherein the method for forming a deep well region comprises: implanting first doping ions into the substrate to form a first implantation region, a second implantation region and a third implantation region which are arranged along a first direction and are mutually separated, wherein the second implantation region is positioned between the first implantation region and the third implantation region; and driving the first doped ions to diffuse by adopting a high-temperature push-well process until the first injection region is contacted with the second injection region, the second injection region is contacted with the third injection region to form a deep well region, wherein the deep well region comprises a first doped region, a second doped region, a third doped region, a first diffusion region positioned between the first doped region and the second doped region, and a second diffusion region positioned between the second doped region and the third doped region, the first doped region is formed by the first injection region, the second doped region is formed by the second injection region, and the third doped region is formed by the third injection region.
4. The method of forming an LDMOS device of claim 3, wherein the forming of the first implant region, the second implant region, and the third implant region further comprises: forming a mask layer on the surface of the substrate, wherein the mask layer exposes part of the surface of the substrate; and implanting the first doping ions into the substrate by taking the mask layer as a mask.
5. The method of forming an LDMOS device of claim 3, wherein the implantation process parameters of the first dopant ions comprise: the implantation energy ranges from 100KeV to 2000KeV, and the implantation dose ranges from 1E12 atoms per square centimeter to 1E13 atoms per square centimeter.
6. The method of forming an LDMOS device of claim 3, wherein the process parameters of the high temperature push-well process comprise: the temperature range of the pushing stage is 1000 ℃ to 1300 ℃, and the pushing time range is 200 minutes to 1000 minutes.
7. The method of forming an LDMOS device of claim 2, further comprising: after forming the gate, a channel-out region within the body region is formed, the channel-out region having a first conductivity type, and the channel-out region being remote from the field oxide layer relative to the source.
8. The method of forming an LDMOS device of claim 7, wherein after forming the source, the drain, and the channel-out region, further comprising: forming a dielectric layer on the surface of the substrate; and forming a conductive layer in the dielectric layer, wherein the conductive layer comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the first conductive layer is electrically connected with the channel leading-out area, the second conductive layer is electrically connected with the source electrode, the third conductive layer is electrically connected with the drain electrode, and the fourth conductive layer is electrically connected with the grid electrode.
9. The method of forming an LDMOS device of claim 2, wherein the first conductivity type is P-type and the second conductivity type is N-type.
10. The method of forming an LDMOS device of claim 2, wherein the forming of the field oxide layer comprises a local oxidation isolation process.
11. The method of forming an LDMOS device of claim 2, wherein the third dimension ranges from 2 microns to 100 microns.
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