CN113871455A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN113871455A
CN113871455A CN202111144567.2A CN202111144567A CN113871455A CN 113871455 A CN113871455 A CN 113871455A CN 202111144567 A CN202111144567 A CN 202111144567A CN 113871455 A CN113871455 A CN 113871455A
Authority
CN
China
Prior art keywords
region
substrate
ions
type
electric field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111144567.2A
Other languages
Chinese (zh)
Other versions
CN113871455B (en
Inventor
潘嘉
杨继业
邢军军
陈冲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202111144567.2A priority Critical patent/CN113871455B/en
Publication of CN113871455A publication Critical patent/CN113871455A/en
Application granted granted Critical
Publication of CN113871455B publication Critical patent/CN113871455B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: a substrate; the deep groove structure is positioned in the substrate and is inverted with the substrate, the top surface of the substrate is exposed out of the top surface of the deep groove structure, and the bottom surface of the substrate is exposed out of the bottom surface of the deep groove structure; the bottom of the substrate and the deep groove structure is provided with an electric field stopping area and a collecting area; the first epitaxial layer is positioned on the top surfaces of the substrate and the deep groove structure; a body region located within the first epitaxial layer; a source region located within the body region; a gate structure located within the first epitaxial layer. The semiconductor structure has good performance.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
In a switching power supply device with medium and high power, an Insulated Gate Bipolar transistor (IGBT for short) is more and more widely applied in modern power electronic technology due to the characteristics of simple control and driving circuit, high operating frequency and large capacity.
The insulated gate bipolar transistor is a device formed by compounding an MOSFET and a bipolar transistor, wherein the input electrode of the insulated gate bipolar transistor is the MOSFET, and the output electrode of the insulated gate bipolar transistor is the PNP transistor, so that the insulated gate bipolar transistor can be regarded as a Darlington transistor with MOS input. The device integrates the advantages of the two devices, and has the advantages of high input impedance, simple and quick drive of the MOSFET device, low conduction voltage drop of the bipolar device and large capacity.
However, the performance of the prior art igbt still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of an insulated gate bipolar transistor.
To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate; the deep groove structure is positioned in the substrate and is inverted with the substrate, the top surface of the substrate is exposed out of the top surface of the deep groove structure, and the bottom surface of the substrate is exposed out of the bottom surface of the deep groove structure; the bottom of the substrate and the deep groove structure is provided with an electric field stopping area and a collector area, the collector area is positioned below the electric field stopping area, the electric field stopping area is in an inverse shape with the deep groove structure, and the collector area is in an inverse shape with the electric field stopping area; the first epitaxial layer is positioned on the top surfaces of the substrate and the deep groove structure; the body region is positioned in the first epitaxial layer, at least part of the body region is positioned above the deep groove structure, and the body region is higher than the top surfaces of the substrate and the deep groove structure; the source region is positioned in the body region, and the body region exposes part of the surface of the source region; and the grid structure is positioned in the first epitaxial layer, is positioned above the substrate adjacent to the deep groove structure, is higher than the top surfaces of the substrate and the deep groove structure, and is in contact with the surfaces of the body region and the source region.
Optionally, an included angle between the sidewall of the deep trench structure and a normal direction perpendicular to the surface of the substrate is greater than 0 degree and less than or equal to 3 degrees.
Optionally, the depth of the electric field stop region ranges from 1 micron to 30 microns.
Optionally, the depth of the electric field stop region is 5 microns.
Optionally, the depth range of the collector region is 0.1 to 5 micrometers.
Optionally, the substrate is an N-type substrate, the first epitaxial layer is an N-type first epitaxial layer, the deep trench structure above the electric field termination region is a P-type deep trench structure, the electric field termination region is doped with N-type first ions, and the collector region is doped with P-type second ions.
Optionally, the doping concentration of the first ions in the electric field stop region is higher than the doping concentration of the N-type ions in the substrate above the electric field stop region.
Optionally, the doping concentration of the second ions in the collector region is higher than the doping concentration of the P-type ions in the deep trench structure above the electric field stop region.
Optionally, the first ions comprise phosphorus ions and the second ions comprise boron ions.
Optionally, the doping concentration of the first ions in the electric field stop region ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
Optionally, the body region is doped with P-type ions, and the source region is doped with N-type ions.
Optionally, the substrate and the top of the deep trench structure further have a blocking doping region, the top surface of the substrate exposes the blocking doping region, the blocking doping region is doped with third N-type ions, the doping concentration of the third ions in the blocking doping region is higher than that of the N-type ions in the substrate above the electric field stop region, and the doping concentration of the third ions in the blocking doping region is also higher than that of the N-type ions in the first epitaxial layer.
Optionally, the gate structure includes: the gate dielectric layer is also positioned between the gate electrode and the surfaces of the body region and the source region.
Optionally, the top surface of the first epitaxial layer exposes the surfaces of the body region, the source region, and the gate structure, and the semiconductor structure further includes: the interlayer dielectric layer is positioned on the top surface of the first epitaxial layer and the exposed surfaces of the gate structure, the body region and the source region; the first conductive structure is positioned in the interlayer dielectric layer and is connected with the grid structure; and the second conductive structure is positioned in the interlayer dielectric layer and is connected with the body region and the source region.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing an initial substrate; forming an initial deep groove structure in the initial substrate, wherein the initial deep groove structure is inverted to the initial substrate, the initial deep groove structure comprises a second area and a first area positioned on the second area, the top surface of the initial substrate is exposed out of the first area, and the width of the second area is less than or equal to that of the first area; forming a first epitaxial layer on the top surfaces of the initial substrate and the initial deep groove structure; forming a body region, a source region and a gate structure in the first epitaxial layer, wherein at least part of the body region is positioned above the initial deep groove structure, the source region is positioned in the body region, part of the surface of the source region is exposed out of the body region, the gate structure is positioned above the initial substrate adjacent to the initial deep groove structure, the gate structure is in contact with the exposed surfaces of the body region and the source region, and both the body region and the gate structure are higher than the top surfaces of the initial substrate and the initial deep groove structure; after the body region, the source region and the grid electrode structure are formed, carrying out crystal back thinning on the initial substrate from the bottom surface of the initial substrate until the second region of the initial deep groove structure is removed, forming a substrate and a deep groove structure, and exposing the first region from the bottom surface of the substrate; performing ion implantation on the bottom surface of the substrate and the first region exposed from the bottom surface of the substrate, and forming an electric field stopping region in an inverse shape of the deep groove structure at the bottom of the substrate and the deep groove structure; and after the electric field stopping region is formed, carrying out ion implantation on the bottom of the electric field stopping region, and forming a collector region which is in an inverse type with the electric field stopping region on the substrate below the electric field stopping region and the bottom of the deep groove structure.
Optionally, the process of performing the back-of-wafer thinning on the initial substrate from the bottom surface of the initial substrate includes a Taiko thinning process.
Optionally, the height of the deep trench structure in a direction perpendicular to the top surface of the substrate is in a range from 20 micrometers to 100 micrometers.
Optionally, the substrate is an N-type substrate, the first epitaxial layer is an N-type first epitaxial layer, the deep trench structure above the electric field termination region is a P-type deep trench structure, the electric field termination region is doped with N-type first ions, and the collector region is doped with P-type second ions.
Optionally, the ion implantation process parameters for forming the electric field stop region include: the implanted ions are phosphorus ions; the implant dose is 1E11 atoms per square centimeter to 1E15 atoms per square centimeter.
Optionally, the ion implantation process parameters for forming the collector region include: the implanted ions are boron ions; the implant dose is 1E11 atoms per square centimeter to 1E15 atoms per square centimeter.
Optionally, the method further includes: before the first epitaxial layer is formed, ion implantation is carried out on the top of the initial substrate and the top of the first region, a blocking doping region is formed on the top of the initial substrate and the top of the first region, third ions of an N type are doped in the blocking doping region, the doping concentration of the third ions in the blocking doping region is higher than that of the N type ions in the substrate above the electric field stopping region, and the doping concentration of the third ions in the blocking doping region is also higher than that of the N type ions in the first epitaxial layer.
Optionally, the process parameters for performing ion implantation on the initial substrate and the top of the first region include: the implanted ions include phosphorus ions; the implant dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter; the injection energy is 1 MeV-3 MeV.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the initial substrate is thinned from the bottom surface of the initial substrate until the second region of the initial deep groove structure is removed, so that the substrate and the deep groove structure are formed, and the electric field stopping region which is opposite to the deep groove structure is formed at the bottom of the substrate and the deep groove structure, therefore, the part of the second region with inclined side wall in the initial deep groove structure is removed, the part which is easy to lose the pressure resistance in the deep groove structure is reduced, the stability of the whole pressure resistance of the semiconductor structure is good, and meanwhile, the semiconductor structure still forms a super junction structure with higher pressure resistance through the electric field stopping region, the substrate above the electric field stopping region and the deep groove structure. Moreover, since the initial substrate is subjected to back-of-wafer thinning, the overall height of the formed substrate is small, and therefore the conduction voltage drop is also reduced. In conclusion, the performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of an IGBT;
fig. 2 to 9 are schematic cross-sectional views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of the prior art igbt still needs to be improved.
Fig. 1 is a schematic structural diagram of an insulated gate bipolar transistor.
Referring to fig. 1, the igbt includes: an N-type substrate 100, the N-type substrate 100 having opposing top 101 and bottom 102 surfaces; the P-type column structure 110 is positioned in the N-type substrate 100, the top surface 101 exposes the surface of the P-type column structure 110, and the N-type substrate 100 and the P-type column structure 110 form a Super Junction structure (Super Junction) so as to improve the voltage withstanding capability of the insulated gate bipolar transistor when the insulated gate bipolar transistor is turned off; an N-type epitaxial layer 120 located on the top surface 101 and the surface of the P-type pillar structure 110; a P-type body region 130 located within the N-type epitaxial layer 120; an N-type source region 140 located within the P-type body region 130; a gate structure 150 located within the N-type epitaxial layer 120, and the gate structure 150 is in surface contact with the P-type body region 130 and the N-type source region 140; the P-type collector region 160 is located in the N-type substrate 100, and the bottom surface 102 is a surface of the collector region 160.
However, in the above structure, in order to enhance the voltage endurance of the igbt, it is usually necessary to form the P-type pillar structure 110 with a larger height H1 (shown in fig. 1), so when the N-type substrate 100 is etched to form an opening (not shown) in the N-type substrate 100 to provide a space for the P-type pillar structure 110, the opening has a larger aspect ratio, which may cause the sidewall of the bottom of the opening to be more inclined. Therefore, in the formed P-type pillar structure 110, compared to the top of the P-type pillar structure 110, in the region a (as shown in fig. 1) near the bottom, the sidewall of the P-type pillar structure 110 is inclined to a greater degree, which results in a greater loss of voltage resistance in the region a and a lower overall voltage resistance stability of the igbt. In addition, the larger height H1 also results in the larger thickness H2 of the N-type substrate 100, and thus, the larger on-state voltage drop of the igbt. In summary, the performance of the insulated gate bipolar transistor is poor.
In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, in which a back-of-wafer thinning is performed on an initial substrate from a bottom surface of the initial substrate until a second region of the initial deep trench structure is removed to form a substrate and a deep trench structure, and an electric field stop region that is opposite to the deep trench structure is formed at bottoms of the substrate and the deep trench structure, thereby improving performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 2 to 9 are schematic cross-sectional views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 2, an initial substrate 200 is provided.
The initial substrate 200 has opposing top 201 and bottom 202 surfaces.
In this embodiment, the material of the initial substrate 200 includes a semiconductor material. Specifically, the material of the initial substrate 200 includes silicon.
In other embodiments, the material of the initial substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In this embodiment, the initial substrate 200 is an N-type substrate.
In another embodiment, the initial substrate may also be a P-type substrate to form an insulated gate bipolar transistor (hereinafter referred to as an IGBT device) of a conductivity type opposite to that of the present embodiment.
Referring to fig. 3, an initial deep trench structure 210 is formed in the initial substrate 200, wherein the initial deep trench structure 210 is inverted with respect to the initial substrate 200.
In the present embodiment, the initial deep trench structure 210 is a P-type initial deep trench structure.
In another embodiment, the initial deep trench structure is N-type based on an initial substrate of P-type.
The initial moat structure 210 provides material for the subsequent formation of moat structures.
Specifically, the initial deep trench structure 210 includes: a first zone I and a second zone II.
The first region I is located on the second region II in a direction perpendicular to the top surface 201 of the initial substrate 200. The top surface 201 of the initial substrate 200 exposes the first region I. And the width of the second region II is less than or equal to the width of the first region I.
Since the width of the second region II is less than or equal to the width of the first region I, the sidewall of the initial deep trench structure 210 at the second region II is inclined.
In this embodiment, the method for forming the initial deep trench structure 210 includes: forming a first mask layer (not shown) on the top surface 201 of the initial substrate 200; the first mask layer exposes a portion of the top surface 201 of the initial substrate 200; etching the initial substrate 200 by using the first mask layer as a mask, and forming a deep trench (not shown) in the initial substrate 200, wherein the deep trench is exposed from a top surface 201 of the initial substrate 200, the depth of the deep trench is smaller than the thickness of the initial substrate 200 in a direction perpendicular to the top surface 201, and compared with the first region I, sidewalls of the deep trench at the second region II are inclined, and a distance between the sidewalls is gradually reduced; an initial deep trench structure 210 is formed within the deep trench.
In the present embodiment, the process of forming the initial deep trench structure 210 in the deep trench includes an epitaxial growth process and the like.
In the present embodiment, after the initial deep trench structure 210 is formed, the first mask layer is removed.
Referring to fig. 4, ion implantation is performed on the top of the initial substrate 200 and the first region I of the initial deep trench structure 210, and a blocking doped region 220 is formed on the top of the initial substrate 200 and the first region I of the initial deep trench structure 210.
In the embodiment, the blocking doping region 220 is doped with third ions of N type, and the doping concentration of the third ions in the blocking doping region 220 is higher than that of the N type ions in the substrate above the subsequently formed electric field stop region.
Specifically, in the present embodiment, since the blocking doping region 220 is formed, the doping concentration of the third ions in the blocking doping region 220 is higher than the doping concentration of the N-type ions in the substrate between the blocking doping region 220 and the electric field stop region.
By forming the blocking doping region 220 which is inverted with respect to the P-type deep trench structure to be formed later and has a higher third ion doping concentration, carriers injected into the body region (to be formed later) from the collector region (to be formed later) are blocked, and carriers entering the body region through the P-type deep trench structure are reduced. Therefore, carriers injected from the collector region are better gathered in the drift region (i.e., the blocking doping region 220 under the body region and the gate structure, and the substrate and the first epitaxial layer which are formed later) under the body region and the gate structure (formed later), and the carrier concentration of the drift region is improved. Therefore, the on-resistance of the drift region can be reduced, the on-state voltage drop of the IGBT device can be reduced better, and meanwhile, the turn-off loss (EOFF) of the IGBT device can be further improved. Furthermore, the performance of the IGBT device is further improved.
It should be noted that, in this embodiment, the blocking doping region 220 is doped with third ions of an N type, so that the blocking doping region 220 correspondingly blocks holes (carriers) injected by the collector region.
Specifically, the third ion is a phosphorus ion.
In this embodiment, the process parameters for performing the ion implantation on the initial substrate 200 and the top of the first region I of the initial deep trench structure 210 include: the implanted ions include phosphorus ions; the implant dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter; the injection energy is 1 MeV-3 MeV.
By the ion implantation process using the above process parameters, the barrier doping region 220 having a suitable third ion doping concentration can be formed.
In another embodiment, the doped P-type ions in the doped region are blocked on the basis of the P-type substrate and the N-type initial deep groove structure. The P-type ions include boron ions or indium ions.
In other embodiments, the blocking doping region may not be formed.
Referring to fig. 5, a first epitaxial layer 230 is formed on a top surface 201 of the initial substrate 200 and a top surface of the initial deep trench structure 210.
Specifically, in this embodiment, since the blocking doping region 220 is formed, the first epitaxial layer 230 is formed on the blocking doping region 220.
In this embodiment, the first epitaxial layer 230 is an N-type first epitaxial layer.
In the present embodiment, the process of forming the first epitaxial layer 230 includes an epitaxial growth process.
Preferably, the doping concentration of the N-type ions in the first epitaxial layer 230 is lower than that of the third ions in the barrier doping region 220, and the doping concentration of the N-type ions in the first epitaxial layer 230 is greater than that of the N-type ions in the initial substrate 200.
Since the doping concentration of the N-type ions in the first epitaxial layer 230 is lower than the doping concentration of the third ions in the barrier doping region 220, the difficulty of the epitaxial growth process is low, which is beneficial to increasing the process window. Meanwhile, since the doping concentration of the N-type ions in the first epitaxial layer 230 is greater than that of the N-type ions in the initial substrate 200, the blocking capability of carriers entering the body region from the collector region by the first epitaxial layer 230 can be further improved. So as to better improve the performance of the IGBT device.
In another embodiment, a first epitaxial layer of a P-type is formed on the basis of a P-type substrate and an N-type initial deep trench structure.
Referring to fig. 6, a body region 240, a source region 250 and a gate structure 260 are formed within the first epitaxial layer 230.
In the present embodiment, the body region 240 is higher than the barrier doping region 220, and at least a portion of the body region 240 is also located above the initial deep trench structure 210.
In this embodiment, the body region 240 is doped with P-type ions.
In the present embodiment, the source region 250 is located in the body region 240, and the body region 240 exposes a portion of the surface of the source region 250.
In this embodiment, the source region 250 is heavily doped with N-type ions.
In the present embodiment, the gate structure 260 is located above the initial substrate 200 adjacent to the initial deep trench structure 210, the gate structure 260 is in contact with the body region 240 and the exposed surface of the source region 250, and both the body region 250 and the gate structure 260 are higher than the top surface 201 of the initial substrate 200 and the top surface of the initial deep trench structure 210.
Specifically, the gate structure 260 in this embodiment is higher than the blocking doping region 220. The body region 240, the source region 250, and the gate structure 260 are spaced apart from the blocking doping region 220 by the first epitaxial layer 230. The surface of the first epitaxial layer 230 exposes the surfaces of the gate structure 260, the body region 240 and the source region 250.
In this embodiment, the gate structure 260 includes: a gate electrode (not shown), and a gate dielectric layer (not shown) between the gate electrode and the first epitaxial layer 230, the gate dielectric layer also being between the gate electrode and the surfaces of the body region 240 and the source region 250.
In this embodiment, the method for forming the gate structure 260 in the first epitaxial layer 230 includes: forming a second mask layer (not shown) on the surface of the first epitaxial layer 230, wherein the second mask layer exposes a part of the surface of the first epitaxial layer 230 on the initial substrate 200 at least on one side of the initial deep trench structure 210; etching the first epitaxial layer 230 by using the second mask layer as a mask, and forming a gate opening (not shown) in the first epitaxial layer 230; forming a gate dielectric layer on the inner wall surface of the gate opening; after forming a gate dielectric layer, forming a gate electrode in the gate opening to form the gate structure 260; after the gate structure 260 is formed, the second mask layer is removed.
In this embodiment, the method for forming the body region 240 and the source region 250 in the first epitaxial layer 230 includes: performing ion implantation on the first epitaxial layer 230 on at least one side of the gate structure 260 and above the initial deep trench structure 210, and forming a body region 240 in the first epitaxial layer 230; ion implantation is performed on a portion of the body region 240 to form the source region 250 in the body region 240.
In other embodiments, the body region and the source region may also be formed prior to the gate structure.
Referring to fig. 7, an interlayer dielectric layer 270 is formed on the surface of the first epitaxial layer 230 and the exposed surfaces of the gate structure 260, the body region 240, and the source region 250.
The material of the interlayer dielectric layer 270 includes a dielectric material.
In this embodiment, the process of forming the interlayer dielectric layer 270 includes a chemical vapor deposition process and the like.
With continued reference to fig. 7, a first conductive structure (not shown) is formed in the interlayer dielectric layer 270, and the first conductive structure is connected to the gate structure 260; a second conductive structure 280 is formed in the interlayer dielectric layer 270, and the second conductive structure 280 is connected to the body region 240 and the source region 250.
The first conductive structure is used to extract a gate structure 260 (the gate of the IGBT device).
The second conductive structure is used to extract the body region 240 and the source region 250 (emitter of the IGBT device).
In this embodiment, the method for forming the first conductive structure and the second conductive structure 280 in the interlayer dielectric layer 270 includes: forming a third mask layer (not shown) on the surface of the interlayer dielectric layer 270, wherein the third mask layer exposes a part of the surface of the interlayer dielectric layer 270; etching the interlayer dielectric layer 270 with the third mask layer as a mask until a first opening (not shown) and a second opening (not shown) are formed, wherein the first opening exposes a portion of the top surface of the gate structure 260, and the second opening exposes portions of the top surfaces of the source region 250 and the body region 240; conductive material is filled in the first and second openings to form the first and second conductive structures 280.
In other embodiments, the first epitaxial layer may also be patterned according to different mask layers to form a first opening and a second opening, respectively.
Referring to fig. 8, the initial substrate 200 is subjected to back thinning from the bottom surface 202 (as shown in fig. 7) of the initial substrate 200 until the second region II of the initial deep trench structure 210 (as shown in fig. 7) is removed to form a substrate 300 and a deep trench structure 310, and the first region I is exposed at the bottom surface of the substrate 300.
The back of the initial substrate 200 is thinned from the bottom surface 202 of the initial substrate 200 until the second region II of the initial deep trench structure 210 is removed, so that the substrate 300 and the deep trench structure 310 are formed, on one hand, the part of the second region II with inclined side walls in the initial deep trench structure 210 is removed, the part of the deep trench structure 310 which is easy to lose voltage resistance is reduced, the stability of the overall voltage resistance of the semiconductor structure is good, on the other hand, the overall height of the formed substrate 300 is small, and the turn-on voltage drop of the IGBT device is reduced.
Specifically, an included angle between the sidewall of the deep trench structure 310 and a normal direction perpendicular to the substrate surface is greater than 0 degree and less than or equal to 3 degrees.
In the present embodiment, the substrate 300 is an N-type substrate, and the deep trench structure 310 is a P-type deep trench structure.
Preferably, the process of back-thinning the initial substrate 200 from the bottom surface 202 of the initial substrate 200 comprises a Taiko thinning process. Compared with the traditional wafer back thinning process, the Taiko thinning process has the advantages of reducing wafer warpage, improving wafer strength and the like.
In the present embodiment, the height H1 of the deep trench structure 310 in the direction perpendicular to the top surface 301 of the substrate 300 is in the range of 20 micrometers to 100 micrometers.
The height H1 is too small, which, on one hand, removes the bottom region of the initial deep trench structure 210 too much when thinning the back of the wafer, resulting in waste and reduced efficiency, and on the other hand, the height of the region reserved for the subsequent formation of the electric field termination region becomes small, resulting in increased difficulty in the process of forming the electric field termination region. Moreover, the too small height H1 may result in a small height of the deep trench structure 310 above the field stop region and a small depth of the field stop region, which may affect the breakdown voltage and turn-off loss (EOFF) of the IGBT device. The height H1 is too large, which easily results in the inclined sidewall portion of the lower region of the initial deep trench structure 210 not being removed well, and the formed deep trench structure 310 still has the inclined sidewall portion, which is not favorable for further reducing the portion of the deep trench structure 310 that is prone to lose voltage resistance. And, it is also not favorable to better control the overall height of the substrate 300 to better reduce the turn-on voltage drop of the IGBT device. Therefore, the height H1 in a proper range is formed, namely, the height H1 is in a range of 20-100 micrometers, on one hand, waste in the manufacturing process can be reduced, the efficiency is improved, and the process difficulty is reduced, on the other hand, the voltage resistance and turn-off loss of the IGBT device can be better improved, the stability of the whole voltage resistance of the IGBT device is improved, and meanwhile, the turn-on voltage drop of the IGBT device is better reduced.
It should be noted that, in the present embodiment, since the block doped region 220 is formed, the height H1 of the deep trench structure 310 refers to the height of the deep trench structure 310 after the block doped region 220 is removed.
In other embodiments, when the blocking doped region is not formed, the height of the deep trench structure refers to the height of the entire deep trench structure.
Referring to fig. 9, ion implantation is performed on the bottom surface 302 of the substrate 300 and the first region I exposed from the bottom surface 302 of the substrate 300, and an electric field stop region 320 inverse to the deep trench structure 310 is formed at the bottom of the substrate 300 and the deep trench structure 310; after the formation of the field stop 320, an ion implantation is performed at the bottom of the field stop 320, and a collector 330, which is inverted to the field stop 320, is formed at the bottom of the substrate 300 and the deep trench structure 310 below the field stop 320.
Since the electric field stop region 320 which is inverse to the deep trench structure 310 is formed at the bottom of the substrate 300 and the deep trench structure 310, the electric field stop region 320, the substrate 300 above the electric field stop region 320 and the deep trench structure 310 can form a super junction structure with larger voltage resistance on the basis of reducing the part of the deep trench structure 310 which is easy to lose voltage resistance performance and ensuring good stability of the voltage resistance of the whole semiconductor structure. Thus, the performance of the semiconductor structure is improved.
In the present embodiment, the deep trench structure 310 above the electric field stop region 320 is a P-type deep trench structure, the electric field stop region 320 is doped with first ions of N-type, and the collector region 330 is doped with second ions of P-type.
Specifically, in the present embodiment, since the blocking doping region 220 is formed, the deep trench structure 310 between the electric field stop region 320 and the blocking doping region 220 is a P-type deep trench structure.
In another embodiment, the deep trench structure above the electric field stop region is an N-type deep trench structure, the electric field stop region is doped with P-type first ions, and the collector region is doped with N-type second ions.
In this embodiment, the first ions include phosphorous ions.
In the present embodiment, the depth H2 of the electric field stop region 320 is in the range of 1 micron to 30 microns.
If the depth H2 is too small, the electric field cannot be cut off. The depth H2 is too large to improve the conduction voltage drop. Therefore, by selecting an appropriate depth H2(1 to 30 micrometers), both the field cutoff and the on-state voltage drop can be improved.
On the basis that the depth H2 is in the range of 1 to 30 micrometers, it is preferable that the depth H2 of the electric field stop region 320 is 5 micrometers.
In the present embodiment, the doping concentration of the first ions in the electric field stop region 320 is higher than the doping concentration of the N-type ions in the substrate 300 above the electric field stop region 320. Therefore, the electric field can be cut off better, and the turn-off loss of the IGBT device is further reduced.
Specifically, in the present embodiment, since the blocking doping region 220 is formed, the doping concentration of the first ions in the electric field stop region 320 is higher than the doping concentration of the N-type ions in the substrate 300 between the electric field stop region 320 and the blocking doping region 220.
Preferably, the doping concentration of the first ions in the electric field stop region 320 is in a range of 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
In the present embodiment, the ion implantation process parameters for forming the electric field stop region 320 include: the implanted ions are phosphorus ions; the implant dose is 1E11 atoms per square centimeter to 1E15 atoms per square centimeter.
The formation of the electric field stop region 320 having a doping concentration of the first ions in the range of 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter can be achieved by using an ion implantation process with an implantation dose of 1E11 atoms per square centimeter to 1E15 atoms per square centimeter.
In the present embodiment, the doping concentration of the second ions in the collector region 330 is higher than the doping concentration of the P-type ions in the deep trench structure 310 above the electric field stop region 320.
Specifically, in the present embodiment, since the blocking doping region 220 is formed, the doping concentration of the second ions in the collector region 330 is higher than the doping concentration of the P-type ions in the deep trench structure 310 between the electric field stop region 320 and the blocking doping region 220.
In this embodiment, the second ions include boron ions.
In the present embodiment, the depth H3 of the collector region 330 ranges from 0.1 micrometers to 5 micrometers.
Since the field stop 320 is formed with a tailing effect and the depth H3 of the collector region 330 is in the range of 0.1 to 5 microns, i.e., the depth H3 of the collector region 330 is small, the field stop 320 and the collector region 330 under the field stop 320 can be formed by an ion implantation process, respectively.
In this embodiment, the ion implantation process parameters for forming the collector region 330 include: the implanted ions are boron ions; the implant dose is 1E11 atoms per square centimeter to 1E15 atoms per square centimeter.
In this embodiment, after the collector region 330 is formed, a bottom interlayer dielectric layer (not shown) is formed on the bottom surface 302 of the substrate 300 and the exposed surface of the collector region 330; a third conductive structure (not shown) is formed in the bottom interlayer dielectric layer, and the third conductive structure is connected with the collector region 330 to lead out the collector region 330 (collector of the IGBT device).
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, with reference to fig. 9, including: a substrate 300; a deep trench structure 310 located in the substrate 300, wherein the deep trench structure 310 is inverted with respect to the substrate 300, a top surface 201 of the substrate 300 exposes a top surface of the deep trench structure 310, and a bottom surface 302 of the substrate 300 exposes a bottom surface of the deep trench structure 310; the substrate 300 and the bottom of the deep trench structure 310 are provided with an electric field stop region 320 and a collector region 330, the collector region 330 is positioned below the electric field stop region 320, the electric field stop region 320 is inverted to the deep trench structure 310, and the collector region 330 is inverted to the electric field stop region 320; a first epitaxial layer 230 on the top surface 201 of the substrate 300 and the top surface of the deep trench structure 310; a body region 240 located in the first epitaxial layer 230, at least a portion of the body region 240 being located above the deep trench structure 310, and the body region 240 being higher than the top surface 201 of the substrate 300 and the top surface of the deep trench structure 310; a source region 250 located in the body region 240, and the body region 240 exposes a portion of the surface of the source region 250; a gate structure 260 within the first epitaxial layer 230, the gate structure 260 being located above the substrate 300 adjacent to the deep trench structure 310, the gate structure 260 being higher than the top surfaces of the substrate 300 and the deep trench structure 310, and the gate structure 260 being in contact with the body region 240 and the surface of the source region 250.
The semiconductor structure forms a super junction structure with larger capacity, and the whole semiconductor structure has good stability of voltage resistance and small conduction voltage drop. For a detailed principle, please refer to the related explanations in the embodiments of the method for forming a semiconductor structure shown in fig. 2 to 9, which will not be described herein again.
In the present embodiment, the material of the substrate 300 includes a semiconductor material. Specifically, the material of the substrate 300 includes silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In this embodiment, the substrate 300 is an N-type substrate, the body region 240 is doped with P-type ions, and the source region 250 is heavily doped with N-type ions.
In the present embodiment, the substrate 300 and the top of the deep trench structure 310 further have the barrier doping region 220.
Specifically, the first epitaxial layer 230 is located on the blocking doping region 220, the body region 240 is higher than the blocking doping region 220, and the gate structure 260 is higher than the blocking doping region 220. The body region 240, the source region 250, and the gate structure 260 are spaced apart from the blocking doping region 220 by the first epitaxial layer 230.
In this embodiment, the blocking doping region 220 is doped with N-type third ions, the electric field stop region 320 is doped with N-type first ions, the deep trench structure 310 between the electric field stop region 320 and the blocking doping region 220 is a P-type deep trench structure, the collector region 330 is doped with P-type second ions, and the first epitaxial layer 230 is an N-type first epitaxial layer.
Preferably, the doping concentration of N-type ions in the first epitaxial layer 230 is higher than the doping concentration of N-type ions in the substrate 300 between the electric field stop region 320 and the blocking doping region 220.
Since the doping concentration of N-type ions in the first epitaxial layer 230 is higher than the doping concentration of N-type ions in the substrate 300 between the electric field stop region 320 and the blocking doping region 220, the blocking capability of carriers (holes) entering the body region 240 from the collector region 330 can be further improved by the first epitaxial layer 230. So as to better improve the performance of the IGBT device.
In the present embodiment, the doping concentration of the first ions in the electric field stop region 320 is higher than the doping concentration of the N-type ions in the substrate 300 between the electric field stop region 320 and the blocking doping region 220. Therefore, the electric field can be cut off better, and the turn-off loss of the IGBT device is further reduced.
Preferably, the doping concentration of the first ions in the electric field stop region 320 is in a range of 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
In the present embodiment, the doping concentration of the second ions in the collector region 330 is higher than the doping concentration of the P-type ions in the deep trench structure 310 between the electric field stop region 320 and the blocking doping region 220.
In the present embodiment, the doping concentration of the third ions in the blocking doping region 220 is higher than the doping concentration of the N-type ions in the substrate 300 between the electric field stop region 320 and the blocking doping region 220, and the doping concentration of the third ions in the blocking doping region 220 is also higher than the doping concentration of the N-type ions in the first epitaxial layer 230.
In this embodiment, the first ions include phosphorus ions, the second ions include boron ions, and the third ions include phosphorus ions.
In another embodiment, the substrate is a P-type substrate, the deep trench structure between the electric field stop region and the blocking doping region is an N-type deep trench structure, the first epitaxial layer is a P-type first epitaxial layer, the electric field stop region is doped with P-type first ions, the collector region is doped with N-type second ions, and the blocking doping region is doped with P-type third ions.
In other embodiments, the substrate and the top of the deep trench structure may also have no barrier doping region.
In the present embodiment, an angle between the sidewall of the deep trench structure 310 and a normal direction perpendicular to the substrate surface is greater than 0 degree and less than or equal to 3 degrees.
In the present embodiment, the depth H2 of the electric field stop region 320 is in the range of 1 micron to 30 microns.
On the basis that the depth H2 is in the range of 1 to 30 micrometers, it is preferable that the depth H2 of the electric field stop region 320 is 5 micrometers.
In the present embodiment, the depth H3 of the collector region 330 ranges from 0.1 micrometers to 5 micrometers.
In this embodiment, the gate structure 260 includes: a gate electrode (not shown), and a gate dielectric layer (not shown) between the gate electrode and the first epitaxial layer 230, the gate dielectric layer also being between the gate electrode and the surfaces of the body region 240 and the source region 250.
In this embodiment, the surface of the first epitaxial layer 230 exposes the surfaces of the gate structure 260, the body region 240, and the source region 250.
In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 270 on the surface of the first epitaxial layer 230 and the surfaces of the exposed gate structure 260, the body region 240 and the source region 250; a first conductive structure (not shown) located in the interlayer dielectric layer 270, the first conductive structure being connected to the gate structure 260; a second conductive structure 280 located in the interlayer dielectric layer 270, wherein the second conductive structure 280 connects the body region 240 and the source region 250.
The material of the interlayer dielectric layer 270 includes a dielectric material.
The first conductive structure is used to extract a gate structure 260 (the gate of the IGBT device).
The second conductive structure is used to extract the body region 240 and the source region 250 (emitter of the IGBT device).
In this embodiment, the semiconductor structure further includes: a bottom interlevel dielectric layer (not shown) located on the bottom surface 302 of the substrate 300 and on the surface of the exposed collector region 330; and a third conductive structure (not shown) in the bottom interlayer dielectric layer, wherein the third conductive structure is connected with the collector region 330 to lead out the collector region 330 (collector of the IGBT device).
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (22)

1. A semiconductor structure, comprising:
a substrate;
the deep groove structure is positioned in the substrate and is inverted with the substrate, the top surface of the substrate is exposed out of the top surface of the deep groove structure, and the bottom surface of the substrate is exposed out of the bottom surface of the deep groove structure;
the bottom of the substrate and the deep groove structure is provided with an electric field stopping area and a collector area, the collector area is positioned below the electric field stopping area, the electric field stopping area is in an inverse shape with the deep groove structure, and the collector area is in an inverse shape with the electric field stopping area;
the first epitaxial layer is positioned on the top surfaces of the substrate and the deep groove structure;
the body region is positioned in the first epitaxial layer, at least part of the body region is positioned above the deep groove structure, and the body region is higher than the top surfaces of the substrate and the deep groove structure;
the source region is positioned in the body region, and the body region exposes part of the surface of the source region;
and the grid structure is positioned in the first epitaxial layer, is positioned above the substrate adjacent to the deep groove structure, is higher than the top surfaces of the substrate and the deep groove structure, and is in contact with the surfaces of the body region and the source region.
2. The semiconductor structure of claim 1, wherein an angle between a sidewall of the deep trench structure and a normal direction perpendicular to a surface of the substrate is greater than 0 degrees and less than or equal to 3 degrees.
3. The semiconductor structure of claim 1, wherein the depth of the electric field stop region is in a range from 1 micron to 30 microns.
4. The semiconductor structure of claim 3, wherein the depth of the electric field stop region is 5 microns.
5. The semiconductor structure of claim 1, wherein a depth of the collector region ranges from 0.1 microns to 5 microns.
6. The semiconductor structure of claim 1, wherein the substrate is an N-type substrate, the first epitaxial layer is an N-type first epitaxial layer, the deep trench structure above the field stop is a P-type deep trench structure, the field stop is doped with first ions of N-type, and the collector is doped with second ions of P-type.
7. The semiconductor structure of claim 6, wherein a doping concentration of the first ions in the electric field stop region is higher than a doping concentration of N-type ions in the substrate above the electric field stop region.
8. The semiconductor structure of claim 6, wherein the second ions in the collector region have a doping concentration higher than a doping concentration of P-type ions in the deep trench structure above the electric field stop region.
9. The semiconductor structure of claim 6, in which the first ions comprise phosphorous ions and the second ions comprise boron ions.
10. The semiconductor structure of claim 9, wherein a doping concentration of the first ions in the electric field stop region ranges from 1E15 atoms per cubic centimeter to 1E18 atoms per cubic centimeter.
11. The semiconductor structure of claim 6, wherein the body region is doped with P-type ions and the source region is doped with N-type ions.
12. The semiconductor structure of claim 6, wherein the substrate and the top of the deep trench structure further have a barrier doping region, the top surface of the substrate exposes the barrier doping region, the barrier doping region is doped with third ions of N-type, the third ions in the barrier doping region have a doping concentration higher than that of the N-type ions in the substrate above the electric field stop region, and the third ions in the barrier doping region have a doping concentration higher than that of the N-type ions in the first epitaxial layer.
13. The semiconductor structure of claim 1, wherein the gate structure comprises: the gate dielectric layer is also positioned between the gate electrode and the surfaces of the body region and the source region.
14. The semiconductor structure of claim 1, wherein a top surface of the first epitaxial layer exposes surfaces of the body region, source region and gate structure, the semiconductor structure further comprising: the interlayer dielectric layer is positioned on the top surface of the first epitaxial layer and the exposed surfaces of the gate structure, the body region and the source region; the first conductive structure is positioned in the interlayer dielectric layer and is connected with the grid structure; and the second conductive structure is positioned in the interlayer dielectric layer and is connected with the body region and the source region.
15. A method of forming a semiconductor structure, comprising:
providing an initial substrate;
forming an initial deep groove structure in the initial substrate, wherein the initial deep groove structure is inverted to the initial substrate, the initial deep groove structure comprises a second area and a first area positioned on the second area, the top surface of the initial substrate is exposed out of the first area, and the width of the second area is less than or equal to that of the first area;
forming a first epitaxial layer on the top surfaces of the initial substrate and the initial deep groove structure;
forming a body region, a source region and a gate structure in the first epitaxial layer, wherein at least part of the body region is positioned above the initial deep groove structure, the source region is positioned in the body region, part of the surface of the source region is exposed out of the body region, the gate structure is positioned above the initial substrate adjacent to the initial deep groove structure, the gate structure is in contact with the exposed surfaces of the body region and the source region, and both the body region and the gate structure are higher than the top surfaces of the initial substrate and the initial deep groove structure;
after the body region, the source region and the grid electrode structure are formed, carrying out crystal back thinning on the initial substrate from the bottom surface of the initial substrate until the second region of the initial deep groove structure is removed, forming a substrate and a deep groove structure, and exposing the first region from the bottom surface of the substrate;
performing ion implantation on the bottom surface of the substrate and the first region exposed from the bottom surface of the substrate, and forming an electric field stopping region in an inverse shape of the deep groove structure at the bottom of the substrate and the deep groove structure;
and after the electric field stopping region is formed, carrying out ion implantation on the bottom of the electric field stopping region, and forming a collector region which is in an inverse type with the electric field stopping region on the substrate below the electric field stopping region and the bottom of the deep groove structure.
16. The method of forming a semiconductor structure of claim 15, wherein the process of back-thinning the initial substrate from a bottom surface of the initial substrate comprises a Taiko thinning process.
17. The method of claim 15, wherein a height of the deep trench structure in a direction perpendicular to a top surface of the substrate is in a range from 20 microns to 100 microns.
18. The method of claim 15, wherein the substrate is an N-type substrate, the first epitaxial layer is an N-type first epitaxial layer, the deep trench structure above the field stop region is a P-type deep trench structure, the field stop region is doped with first ions of N-type, and the collector region is doped with second ions of P-type.
19. The method of forming a semiconductor structure of claim 18, wherein the ion implantation process parameters for forming the electric field stop region comprise: the implanted ions are phosphorus ions; the implant dose is 1E11 atoms per square centimeter to 1E15 atoms per square centimeter.
20. The method of claim 18, wherein the ion implantation process parameters for forming the collector region comprise: the implanted ions are boron ions; the implant dose is 1E11 atoms per square centimeter to 1E15 atoms per square centimeter.
21. The method of forming a semiconductor structure of claim 18, further comprising: before the first epitaxial layer is formed, ion implantation is carried out on the top of the initial substrate and the top of the first region, a blocking doping region is formed on the top of the initial substrate and the top of the first region, third ions of an N type are doped in the blocking doping region, the doping concentration of the third ions in the blocking doping region is higher than that of the N type ions in the substrate above the electric field stopping region, and the doping concentration of the third ions in the blocking doping region is also higher than that of the N type ions in the first epitaxial layer.
22. The method of forming a semiconductor structure of claim 21, wherein the process parameters for ion implantation into the initial substrate and into the top of the first region comprise: the implanted ions include phosphorus ions; the implant dose is 1E11 atoms per square centimeter to 1E14 atoms per square centimeter; the injection energy is 1 MeV-3 MeV.
CN202111144567.2A 2021-09-28 2021-09-28 Semiconductor structure and forming method thereof Active CN113871455B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111144567.2A CN113871455B (en) 2021-09-28 2021-09-28 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111144567.2A CN113871455B (en) 2021-09-28 2021-09-28 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN113871455A true CN113871455A (en) 2021-12-31
CN113871455B CN113871455B (en) 2023-08-18

Family

ID=78991909

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111144567.2A Active CN113871455B (en) 2021-09-28 2021-09-28 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN113871455B (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003218354A (en) * 2002-01-18 2003-07-31 Fuji Electric Co Ltd Semiconductor device and its manufacturing method
JP2007067447A (en) * 2006-12-04 2007-03-15 Fuji Electric Device Technology Co Ltd Vertical super-junction semiconductor element
US20120153348A1 (en) * 2010-12-16 2012-06-21 Mitsubishi Electric Corporation Insulated gate bipolar transistor and manufacturing method thereof
CN104009072A (en) * 2013-02-25 2014-08-27 中国科学院微电子研究所 Insulated gate bipolar transistor and manufacturing method thereof
CN104795317A (en) * 2015-04-17 2015-07-22 上海华虹宏力半导体制造有限公司 Wafer positioning method
CN104934465A (en) * 2015-05-12 2015-09-23 电子科技大学 Super junction composition preparation method
US20160293745A1 (en) * 2015-03-30 2016-10-06 Semiconductor Manufacturing International (Shanghai) Corporation Power semiconductor device and fabrication method thereof
CN208819886U (en) * 2018-10-25 2019-05-03 上海超致半导体科技有限公司 A kind of superjunction IGBT device structure
CN109888005A (en) * 2019-01-22 2019-06-14 上海华虹宏力半导体制造有限公司 Inverse conductivity type superjunction IGBT device and its manufacturing method
CN111200008A (en) * 2018-11-20 2020-05-26 深圳尚阳通科技有限公司 Super junction device and manufacturing method thereof

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003218354A (en) * 2002-01-18 2003-07-31 Fuji Electric Co Ltd Semiconductor device and its manufacturing method
JP2007067447A (en) * 2006-12-04 2007-03-15 Fuji Electric Device Technology Co Ltd Vertical super-junction semiconductor element
US20120153348A1 (en) * 2010-12-16 2012-06-21 Mitsubishi Electric Corporation Insulated gate bipolar transistor and manufacturing method thereof
CN104009072A (en) * 2013-02-25 2014-08-27 中国科学院微电子研究所 Insulated gate bipolar transistor and manufacturing method thereof
US20160293745A1 (en) * 2015-03-30 2016-10-06 Semiconductor Manufacturing International (Shanghai) Corporation Power semiconductor device and fabrication method thereof
CN106158626A (en) * 2015-03-30 2016-11-23 中芯国际集成电路制造(上海)有限公司 Power device and forming method thereof
CN104795317A (en) * 2015-04-17 2015-07-22 上海华虹宏力半导体制造有限公司 Wafer positioning method
CN104934465A (en) * 2015-05-12 2015-09-23 电子科技大学 Super junction composition preparation method
CN208819886U (en) * 2018-10-25 2019-05-03 上海超致半导体科技有限公司 A kind of superjunction IGBT device structure
CN111200008A (en) * 2018-11-20 2020-05-26 深圳尚阳通科技有限公司 Super junction device and manufacturing method thereof
CN109888005A (en) * 2019-01-22 2019-06-14 上海华虹宏力半导体制造有限公司 Inverse conductivity type superjunction IGBT device and its manufacturing method

Also Published As

Publication number Publication date
CN113871455B (en) 2023-08-18

Similar Documents

Publication Publication Date Title
CN107424928B (en) Power semiconductor device with charge balance design
US11569371B2 (en) Semiconductor device
US11398472B2 (en) RC IGBT with an IGBT section and a diode section
CN110504310B (en) RET IGBT with self-bias PMOS and manufacturing method thereof
CN106997899B (en) A kind of IGBT device and preparation method thereof
TW201515218A (en) Dual trench-gate IGBT structure
CN113838917B (en) Three-dimensional separation gate groove charge storage type IGBT and manufacturing method thereof
CN113725292A (en) IGBT with low-conduction-voltage and high-latching-resistance capability and preparation method thereof
US20220352315A1 (en) Semiconductor device and method for producing same
US11264475B2 (en) Semiconductor device having a gate electrode formed in a trench structure
CN110504313B (en) Transverse groove type insulated gate bipolar transistor and preparation method thereof
CN113838913B (en) Segmented injection self-clamping IGBT device and manufacturing method thereof
CN116387154A (en) Carrier storage groove type bipolar transistor structure and manufacturing method thereof
KR20140118541A (en) Power semiconductor device and fabricating of the same
CN113871455B (en) Semiconductor structure and forming method thereof
CN103531621A (en) Non-punch-through type insulated gate bipolar transistor with side polysilicon electrode trench
CN110504315B (en) Groove-type insulated gate bipolar transistor and preparation method thereof
CN113921595B (en) Semiconductor structure and forming method thereof
KR102042834B1 (en) Power semiconductor device and method of fabricating the same
CN115842049A (en) Insulated gate bipolar transistor and manufacturing method thereof
CN113937156B (en) Semiconductor structure and forming method thereof
WO2021064221A1 (en) Semiconductor device and method for producing same
CN113838915B (en) Trench gate charge storage type IGBT and manufacturing method thereof
CN110459597B (en) Groove-type insulated gate bipolar transistor and preparation method thereof
US11538906B2 (en) Diode with structured barrier region

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant