CN113871419A

CN113871419A - Display substrate and display device

Info

Publication number: CN113871419A
Application number: CN202010621917.9A
Authority: CN
Inventors: 周宏军; 谭文
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2021-12-31
Also published as: WO2022001410A1; US20240147786A1; DE112021000234T5

Abstract

A display base plate and display device, the display base plate has display area and peripheral area at least partially surrounding the display area, and include the substrate base plate; the display area comprises a plurality of pixel units arranged on the substrate in an array mode and a plurality of signal lines electrically connected with the pixel units respectively; the peripheral area comprises at least one first electrode pattern electrically connected with at least one of the signal lines and a second electrode pattern, and the at least one first electrode pattern and the second electrode pattern are at least partially overlapped and arranged at intervals in an insulating mode in a direction perpendicular to the plate surface of the substrate base plate; the peripheral region further includes a gate scan driving circuit configured to supply gate scan signals to the plurality of pixel units, and at least one of the first electrode pattern and the second electrode pattern is located between the gate scan driving circuit and the display region in a direction parallel to a plate surface of the substrate. The display substrate can compensate the transmission load of the signal line, thereby improving the signal transmission effect.

Description

Display substrate and display device

Technical Field

The embodiment of the disclosure relates to a display substrate and a display device.

Background

An Organic Light-Emitting Diode (OLED) display device has the advantages of thin thickness, Light weight, wide viewing angle, active Light emission, continuously adjustable Light emission color, low cost, fast response speed, low energy consumption, low driving voltage, wide working temperature range, simple production process, high Light-Emitting efficiency, flexible display and the like, and is therefore more and more widely applied to the display fields of mobile phones, tablet computers, digital cameras and the like.

Disclosure of Invention

At least one embodiment of the present disclosure provides a display substrate having a display area and a peripheral area at least partially surrounding the display area, and including: a substrate base plate; wherein the display region comprises a plurality of pixel units arranged on the substrate in an array manner and a plurality of signal lines respectively electrically connected with the pixel units, the peripheral region includes at least one first electrode pattern electrically connected to at least one of the plurality of signal lines, and a second electrode pattern, wherein the at least one first electrode pattern and the second electrode pattern are at least partially overlapped in a direction vertical to the plate surface of the substrate base plate and are arranged at intervals in an insulating way, the peripheral region further includes a gate scan driving circuit configured to supply gate scan signals to the plurality of pixel units, the at least one first electrode pattern and the second electrode pattern are located between the gate scan driving circuit and the display region in a direction parallel to a plate surface of the substrate base plate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, an orthogonal projection of the at least one first electrode pattern on the substrate is located within an orthogonal projection of the second electrode pattern on the substrate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the second electrode pattern is located on a side of the at least one first electrode pattern away from the substrate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, at least one of the plurality of pixel units includes a pixel driving circuit on the substrate, the pixel driving circuit including a thin film transistor and a storage capacitor; the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode, and the storage capacitor comprises a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode in the direction vertical to the plate surface of the substrate; the source electrode and the drain electrode are positioned on one side of the active layer far away from the substrate, the first electrode pattern, the grid electrode and the first capacitor electrode are arranged on the same layer, and the second electrode pattern and the second capacitor electrode are arranged on the same layer.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the plurality of signal lines are disposed at the same layer as the source and drain electrodes of the thin film transistor, and the at least one first electrode pattern is electrically connected to at least one of the plurality of signal lines through a via structure.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the second electrode pattern is configured to receive a first voltage signal from a first voltage source.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the peripheral region further includes a power trace pattern, the power trace pattern is electrically connected to the first voltage source, and the second electrode pattern is electrically connected to the power trace pattern to receive the first voltage signal through the power trace pattern.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the power trace pattern is disposed on the same layer as the source and the drain of the thin film transistor, and the second electrode pattern is electrically connected to the power trace pattern through a via structure.

For example, in a display substrate provided in at least one embodiment of the present disclosure, at least a portion of the second electrode pattern is electrically connected between the power trace pattern and the plurality of pixel units in a direction parallel to a plate surface of the substrate, and the power trace pattern provides the first voltage signal to at least a portion of the plurality of pixel units through the second electrode pattern.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the at least one first electrode pattern includes a plurality of first electrode patterns, and the plurality of first electrode patterns are arranged at intervals; the peripheral region further includes a space pattern between two adjacent first electrode patterns and insulated from the first electrode patterns.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the space pattern is configured to receive a second voltage signal from a second voltage source different from the first voltage source.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the space pattern is electrically connected to the second electrode pattern to receive the first voltage signal from the first voltage source.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the spacer pattern is disposed in the same layer as an active layer of the thin film transistor.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the second electrode patterns are continuously disposed along an edge of the display area, and at least partially overlap and are spaced apart from the plurality of first electrode patterns in a direction perpendicular to a plate surface of the substrate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, an extending direction of at least a portion of an edge of the display area intersects with and is not perpendicular to an extending direction of the plurality of signal lines.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the display substrate further includes a first insulating layer located between the first electrode pattern and the second electrode pattern, and a material of the first insulating layer includes silicon nitride or silicon oxynitride.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the plurality of pixel units includes a first column of pixel units and a second column of pixel units, the number of pixel units in the first column of pixel units is less than the number of pixel units in the second column of pixel units, and a signal line electrically connected to the first column of pixel units is electrically connected to one first electrode pattern.

For example, in a display substrate provided in at least one embodiment of the present disclosure, a signal line electrically connected to the second column of pixel units is electrically connected to another first electrode pattern, and a compensation capacitance formed by the second electrode pattern and the one first electrode pattern electrically connected to the signal line electrically connected to the first column of pixel units is larger than a compensation capacitance formed by the second electrode pattern and the another first electrode pattern electrically connected to the signal line electrically connected to the second column of pixel units.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the first electrode patterns and the second electrode patterns are different in length in a column direction, or the first electrode patterns and the second electrode patterns are different in length in a row direction.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the plurality of signal lines are scanning lines or data lines.

For example, in a display substrate provided in at least one embodiment of the present disclosure, a first end or a second end of at least one of the plurality of signal lines is electrically connected to one first electrode pattern, or a first end of at least one of the plurality of signal lines is electrically connected to one first electrode pattern, and a second end of at least one of the plurality of signal lines is electrically connected to another first electrode pattern.

At least one embodiment of the present disclosure further provides a display device including the display substrate according to any one of the embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1A is a schematic plan view of a display substrate according to some embodiments of the present disclosure;

fig. 1B is a schematic plan view of another display substrate provided in some embodiments of the present disclosure;

fig. 2A is a schematic view of a compensation method of the display substrate shown in fig. 1A according to some embodiments of the disclosure;

FIG. 2B is a schematic view of another compensation method for the display substrate shown in FIG. 1A according to some embodiments of the present disclosure;

FIG. 2C is a schematic view of another compensation method for the display substrate shown in FIG. 1A according to some embodiments of the present disclosure;

fig. 3 is a schematic view of a partial structure of a display substrate according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of a partial plan view of a perimeter region of a display substrate according to some embodiments of the present disclosure;

FIG. 5A is a schematic illustration showing a partial cross-sectional structure of a perimeter region of a substrate according to some embodiments of the present disclosure;

FIG. 5B is a schematic illustration of a partial cross-sectional structure of a perimeter region of another display substrate provided by some embodiments of the present disclosure;

fig. 6 is a schematic view illustrating a partial cross-sectional structure of a display area and a partial cross-sectional structure of a peripheral area of a display substrate according to some embodiments of the present disclosure;

fig. 7 is an equivalent circuit diagram of a pixel driving circuit in a display substrate according to some embodiments of the present disclosure;

8A-8E are schematic diagrams of layers of a pixel driving circuit in a display substrate according to some embodiments of the present disclosure;

fig. 9 is a schematic block diagram of a display device provided in some embodiments of the present disclosure; and

fig. 10 is a schematic block diagram of another display device provided in some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

At present, with the continuous popularization of electronic display products, the requirements of users on the functions and the appearances of the electronic display products are further improved. In order to meet different practical requirements of users, the appearance or display area of an electronic display product sometimes needs to be designed into an irregular or special shape. However, due to the irregular or special shape of the display area, the number of pixel cells included in different rows of the display area may be different, or the number of pixel cells included in different columns of the display area may be different. For example, taking the example that the number of pixel units included in different columns in the display area is different, due to the different number of pixel units in different columns, the transmission loads on the plurality of signal lines for providing, for example, data signals or other required electrical signals to the pixel units located in different columns may be different, so that the signal transmission effects (e.g., transmission speeds) of the plurality of signal lines are different, and further, the luminance uniformity and uniformity of the provided display screen are reduced, and even a display abnormal phenomenon may occur.

At least one embodiment of the present disclosure provides a display substrate having a display area and a peripheral area at least partially surrounding the display area, and including a base substrate. The display area comprises a plurality of pixel units arranged on the substrate in an array mode and a plurality of signal lines electrically connected with the pixel units respectively; the peripheral area comprises at least one first electrode pattern electrically connected with at least one of the signal lines and a second electrode pattern, and the at least one first electrode pattern and the second electrode pattern are at least partially overlapped and arranged at intervals in an insulating mode in a direction perpendicular to the plate surface of the substrate base plate; the peripheral region further includes a gate scan driving circuit configured to supply gate scan signals to the plurality of pixel units, and at least one of the first electrode pattern and the second electrode pattern is located between the gate scan driving circuit and the display region in a direction parallel to a plate surface of the substrate.

According to the display substrate provided by the embodiment of the disclosure, the first electrode patterns and the second electrode patterns are at least partially overlapped in the direction perpendicular to the plate surface of the substrate and are arranged at intervals in an insulating manner, so that the first electrode patterns and the second electrode patterns can form a capacitor, and thus, transmission loads on the signal lines electrically connected with the first electrode patterns are compensated, the consistency of signal transmission effects of a plurality of signal lines is improved, the brightness uniformity and consistency of a display picture are improved, abnormal or bad display phenomena of the display picture are reduced or avoided, and the display effect of the picture is improved.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.

Fig. 1A is a schematic plan view of a display substrate according to some embodiments of the present disclosure. As shown in fig. 1A, the display substrate 10 has a display area 101 and a peripheral area 102 that at least partially surrounds (e.g., completely surrounds) the display area 101. For example, the display area 101 of the display substrate 10 may be circular in shape, and the peripheral area 102 surrounds the display area 101 and has an outline similar to a circle, so that the display substrate 10 has a substantially circular shape to meet the actual demands of users for display substrates of different shapes.

It should be noted that, the specific shape of the display substrate is not limited in the embodiments of the present disclosure. For example, fig. 1B is a schematic plan view of another display substrate provided in some embodiments of the present disclosure. As shown in fig. 1B, the display substrate 20 has a display area 201 and a peripheral area 202 that at least partially surrounds (e.g., completely surrounds) the display area 201. For example, the display area 201 of the display substrate 20 may be square with rounded corners, and the peripheral area 202 surrounds the display area 201 and has the same contour as the display area 201, thereby making the display substrate 20 square with rounded corners. In some other embodiments of the present disclosure, the display substrate may also be in a regular shape such as an ellipse, a sector, a triangle, a diamond, a pentagon, or may also be in another suitable irregular shape, which is not limited by the embodiments of the present disclosure.

In the following, the embodiment of the present disclosure takes the shape of the display substrate 10 shown in fig. 1A as an example, and the display substrate provided in the embodiment of the present disclosure is explained, but this is not to be construed as limiting the embodiment of the present disclosure.

Fig. 2A is a schematic view of a compensation method of the display substrate shown in fig. 1A according to some embodiments of the disclosure; fig. 3 is a schematic diagram of a partial structure of a display substrate according to some embodiments of the present disclosure, for example, fig. 3 may correspond to the region REG1 shown in fig. 2A.

For example, as shown in fig. 1A, 2A, and 3, the display substrate 10 includes a substrate 100. The display region 101 includes a plurality of pixel units 110 arranged in an array on the substrate 100 and a plurality of signal lines 120 electrically connected to the plurality of pixel units 110, respectively. The peripheral region 102 includes at least one first electrode pattern 130 electrically connected to at least one of the plurality of signal lines 120 and includes a second electrode pattern 140. The first electrode patterns 130 and the second electrode patterns 140 are at least partially overlapped and spaced apart from each other in a direction perpendicular to the plate surface of the substrate 100 to form a capacitor, so that a transmission load on the signal line 120 electrically connected to the first electrode patterns 130 (for example, the transmission load on the signal line 120 may refer to a transmission resistance of the signal line 120, or a capacitance formed between the signal line 120 and another trace line) can be compensated by the capacitor formed between the first electrode patterns 130 and the second electrode patterns 140, so as to improve the uniformity of the transmission load on the plurality of signal lines 120 in the display area 101. Therefore, the signal transmission effect of the plurality of signal lines 120 in the display area 101 can be improved, the brightness uniformity and consistency of the provided display picture are improved, the display abnormity or bad phenomenon of the display picture is weakened or avoided, and the display effect of the picture is improved.

In some embodiments of the present disclosure, the signal line 120 may be a scan line, for example, for providing a gate scan signal to the pixel unit 110, or may also be a data line, for example, for providing a data signal to the pixel unit 110, or may also be a signal line for providing other electrical signals required for realizing image display to the pixel unit 110.

For example, in the case where the signal line 120 is a scan line, the capacitance formed between the first electrode pattern 130 and the second electrode pattern 140 compensates for a transmission load on the scan line electrically connected to the first electrode pattern 130, so as to improve a transmission effect of, for example, a gate scan signal transmitted on the scan line, and improve uniformity of the transmission effect of the gate scan signal on a plurality of scan lines in the display region 101.

For example, in the case where the signal line 120 is a data line, a transmission load on the data line electrically connected to the first electrode pattern 130 is compensated by a capacitance formed between the first electrode pattern 130 and the second electrode pattern 140, so as to improve a transmission effect of, for example, a data signal transmitted on the data line, and improve uniformity of the transmission effect of the data signal on a plurality of data lines in the display region 101.

The following embodiments of the present disclosure are described by taking the signal line 120 as a data line as an example, but it should be noted that the embodiments of the present disclosure include but are not limited thereto.

For example, as shown in fig. 1A, fig. 2A and fig. 3, the peripheral region 102 further includes a Gate On Array (GOA) 150, and the Gate GOA 150 is configured to provide Gate scanning signals to the plurality of pixel units 110, and is directly fabricated on the substrate 100 through a semiconductor process, for example. In a direction parallel to the plate surface of the substrate 100, the first electrode pattern 130 and the second electrode pattern 140 are located between the gate scan driving circuit 150 and the display area 101, so that the space utilization rate of the peripheral area 102 can be improved, and the space occupied by the first electrode pattern 130 and the second electrode pattern 140 in the display substrate 10 is reduced, thereby facilitating the display substrate 10 to realize a narrow frame design.

For example, the gate scan driving circuit 150 may include a plurality of cascaded shift register units, for example, an output terminal of each shift register unit is electrically connected to a row of pixel units 110 in the display region 101 through a gate line for providing a gate scan signal to the plurality of pixel units 110 in a row. For example, a plurality of pixel units 110 may be arranged in an array in the display region 101, and the gate scan driving circuit 150 is configured to provide, for example, row-by-row shifted gate scan signals to a plurality of rows of pixel units 110 arranged in the array in the display region 101.

For example, the shift register unit in the gate scan driving circuit 150 may have a 4T1C structure, that is, at least includes four transistors and one capacitor to respectively implement the functions of signal input, signal output, register reset, and the like, or may also include more transistors and/or capacitors, for example, a sub-circuit for implementing the functions of pull-up node control, pull-down node control, noise reduction, and the like is added to implement more stable input, output, and reset, which is not limited in this embodiment of the disclosure.

For example, in the case that the signal lines 120 are data lines, the first electrode patterns 130 may be electrically connected between the corresponding data lines and a data driving circuit for respectively providing corresponding data signals to the plurality of columns of pixel units 110 in the display region 101, thereby enabling transmission of the data signals through the signal lines 120 and the first electrode patterns 130; the first electrode pattern 130 also functions, for example, at least in part, to transmit data signals. For example, the data driving circuit may convert digital image data input from the timing controller into data signals according to a plurality of data control signals from the timing controller using the reference gamma voltage. For example, the data driving circuit may be implemented as a semiconductor chip and then mounted on a flexible printed circuit board and coupled to the data lines on the display substrate by means of bonding.

Fig. 4 is a schematic diagram illustrating a partial planar structure of a peripheral region of a display substrate according to some embodiments of the present disclosure, for example, fig. 4 corresponds to the region REG2 shown in fig. 3. Fig. 5A is a schematic view of a partial cross-sectional structure of a peripheral region of a display substrate according to some embodiments of the present disclosure, for example, fig. 5A may be a schematic view of a partial cross-sectional structure of the display substrate 10 along a line a-a' shown in fig. 3. Fig. 5B is a schematic view of a partial cross-sectional structure of a peripheral region of another display substrate according to some embodiments of the present disclosure, for example, fig. 5B may be a schematic view of a partial cross-sectional structure of the display substrate 10 along the line B-B' shown in fig. 3.

For example, as shown in fig. 3 to 5B in conjunction with, the orthographic projection of the first electrode pattern 130 on the base substrate 100 is located within the orthographic projection of the second electrode pattern 140 on the base substrate 100, that is, in the direction R1 perpendicular to the plate surface of the base substrate 100, the second electrode pattern 140 completely covers the first electrode pattern 130, thereby increasing the capacitance of the compensation capacitance formed between the first electrode pattern 130 and the second electrode pattern 140 by increasing the overlapping area of the first electrode pattern 130 and the second electrode pattern 140 in the direction R1 perpendicular to the plate surface of the base substrate 100, so that a stable capacitance can be formed between the first electrode pattern 130 and the second electrode pattern 140. Therefore, the compensation effect on the transmission load of the signal line 120 can be further improved, and the stability and consistency of the signal transmission effect of the plurality of signal lines 120 in the display area 101 can be further improved.

It should be noted that, in some embodiments of the present disclosure, in order to improve the electrical connection effect between the first electrode pattern 130 and the signal line 120, a connection member for electrically connecting the first electrode pattern 130 and the signal line 120 may also be disposed therebetween. For example, the connection member may be located in the same layer as the first electrode pattern 130 or the signal line 120, or may be located in a layer different from the first electrode pattern 130 and the signal line 120, which is not limited in this respect by the embodiments of the present disclosure.

For example, in some embodiments shown in fig. 3, the first electrode pattern 130 extends in a linear shape and has a long bar shape; in other embodiments of the present disclosure, the first electrode pattern 130 may also extend in a curved shape, a zigzag shape, or other suitable contours, and the shape of the first electrode pattern 130 may also be, for example, an oval shape, a square shape, a zigzag shape, or other suitable regular shapes or irregular shapes according to actual needs, which is not limited by the embodiments of the present disclosure.

For example, as shown in fig. 3 to fig. 5B, the second electrode pattern 140 is located on a side of the first electrode pattern 130 away from the substrate 100, so that the second electrode pattern 140 can play a role of shielding an electric field, and can reduce or avoid interference of other structures or devices, etc. located on the side of the second electrode pattern 140 away from the substrate 100, of the display substrate 10 with the electric signal transmitted on the first electrode pattern 130, thereby improving stability of the electric signal transmitted on the signal line 120 electrically connected to the first electrode pattern 130.

Fig. 6 is a schematic diagram of a partial cross-sectional structure of a display area and a partial cross-sectional structure of a peripheral area of a display substrate according to some embodiments of the disclosure, for example, the cross-sectional structure of the display substrate 10 shown in fig. 6 may include the cross-sectional structure of the peripheral area 102 of the display substrate 10 shown in fig. 5A or the partial cross-sectional structure of the peripheral area 102 of the display substrate 10 shown in fig. 5B, and further include a partial cross-sectional structure of a display area 101 of the display substrate 10, for example, a partial cross-sectional structure of a pixel driving circuit of one pixel unit 110 in the display area 101.

For example, as shown in conjunction with fig. 3-6, at least one of the plurality of pixel cells 110 (e.g., each pixel cell 110) includes a pixel driving circuit on the substrate 100, the pixel driving circuit including a thin film transistor 160 and a storage capacitor 170. The thin film transistor 160 includes an active layer 161, a gate electrode 162, a source electrode 163, and a drain electrode 164, and the storage capacitor 170 includes a first capacitor electrode 171 and a second capacitor electrode 172 opposite to the first capacitor electrode 171 in a direction R1 perpendicular to the plate surface of the substrate 100. The source electrode 163 and the drain electrode 164 are located on a side of the active layer 161 away from the base substrate 100.

For example, the first electrode pattern 130, the gate electrode 162, and the first capacitor electrode 171 are disposed at the same layer, and the second electrode pattern 140 and the second capacitor electrode 172 are disposed at the same layer. Therefore, the first electrode pattern 130, the gate electrode 162 and the first capacitor electrode 171 are formed in the same layer in the manufacturing process (for example, the same material layer is used for forming through the patterning process), and the second electrode pattern 140 and the second capacitor electrode 172 are formed in the same layer in the manufacturing process, so that the manufacturing process of the display substrate 10 can be simplified, the manufacturing cost of the display substrate 10 can be reduced, and the display substrate 10 is beneficial to mass production and application of the display substrate 10.

It should be noted that, in the embodiment of the present disclosure, the "same layer arrangement" means that two functional layers or structural layers are formed in the same layer and the same material in the hierarchical structure of the display substrate, that is, in the manufacturing process, the two functional layers or structural layers may be formed by the same material layer, and a desired pattern and structure may be formed by the same patterning process, for example, the material layer may be formed first and then formed by the material layer through the patterning process.

For example, the display substrate 10 further includes a first insulating layer 1101 between the first electrode pattern 130 and the second electrode pattern 140, and a material of the first insulating layer 1101 may include, for example, silicon nitride or silicon oxynitride, or may also include other insulating materials with a higher dielectric constant. Thus, by using an insulating material having a relatively high dielectric constant (e.g., silicon nitride or silicon oxynitride) as the first insulating layer 1101 between the first electrode pattern 130 and the second electrode pattern 140, a compensation capacitor having a relatively large capacitance may be formed between the first electrode pattern 130 and the second electrode pattern 140, so that the sizes of the first electrode pattern 130 and the second electrode pattern 140 may be reduced. Therefore, the space occupied by the first electrode pattern 130 and the second electrode pattern 140 in the plane parallel to the substrate 100 can be further reduced, which is beneficial for the display substrate 10 to realize a narrow bezel design.

For example, the first insulating layer 1101 is located between the first electrode pattern 130 and the second electrode pattern 140, that is, between the first capacitor electrode 171 and the second capacitor electrode 172, so that the first insulating layer 1101 may increase both the capacitance of the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140 and the capacitance of the storage capacitor, for example, formed between the first capacitor electrode 171 and the second capacitor electrode 172, thereby improving the overall performance of the display substrate 10 and improving the stability of the display substrate 10.

For example, the display substrate 10 further includes a buffer layer 1104, a second insulating layer 1102, and a third insulating layer 1103. The buffer layer 1104 is located on the substrate 100, the active layer 161 is located on a side of the buffer layer 1104 away from the substrate 100, the second insulating layer 1102 is located on a side of the active layer 161 away from the substrate 100, the first electrode pattern 130, the gate 162 and the first capacitor electrode 171 are located on a side of the second insulating layer 1102 away from the substrate 100, the first insulating layer 1101 is located on a side of the first electrode pattern 130, the gate 162 and the first capacitor electrode 171 away from the substrate 100, the second electrode pattern 140 and the second capacitor electrode 172 are located on a side of the first insulating layer 1101 away from the substrate 100, the third insulating layer 1103 is located on a side of the second electrode pattern 140 and the second capacitor electrode 172 away from the substrate 100, and the source 163 and the drain 164 are located on a side of the third insulating layer 1103 away from the substrate 100.

For example, as shown in fig. 6, a plurality of signal lines 120 may be disposed at the same layer as the source electrode 163 and the drain electrode 164 of the thin film transistor 160, and the first electrode pattern 130 may be electrically connected to the signal lines 120 through, for example, a via structure penetrating the first insulating layer 1101 and the third insulating layer 1103, thereby achieving compensation of a transmission load of the signal lines 120.

For example, the display substrate further includes a protective layer (not shown) on a side of the source electrode 163 and the drain electrode 164 away from the base substrate 100, and a light emitting element (not shown) disposed on a side of the protective layer away from the base substrate 100, and the source electrode 163 or the drain electrode 164 is electrically connected to the light emitting element disposed on the protective layer through a via hole in the protective layer.

For example, the material of the active layer 161 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate 162 may include a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed by molybdenum, aluminum, titanium, etc., for example, the multi-layer structure is a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Al/Ti/Al)). The source electrode 163 and the drain electrode 164 may be made of a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed by molybdenum, aluminum, titanium, etc., for example, the multi-layer structure may be a multi-metal layer stack (e.g., a titanium, aluminum, and titanium three-layer metal stack (Al/Ti/Al)). The material of each structural or functional layer is not particularly limited by the embodiments of the present disclosure.

For example, the buffer layer 1104 can prevent harmful substances in the substrate 100 from entering the display substrate 10, and can also increase the adhesion of the film layer in the display substrate 10 to the substrate 100. For example, the material of the buffer layer 1104 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. For example, the material of one or more of the first insulating layer 1101, the second insulating layer 1102, the third insulating layer 1103, and the protective layer may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The materials of the first insulating layer 1101, the second insulating layer 1102, the third insulating layer 1103, the buffer layer 1104 and the protection layer may be the same as each other, or may be different from each other, which is not limited in this embodiment of the disclosure.

It should be noted that fig. 6 shows an example in which the thin film transistor 160 is a top gate thin film transistor, but in some other embodiments of the present disclosure, the thin film transistor 160 may also be a bottom gate thin film transistor or another suitable type of thin film transistor, and the embodiments of the present disclosure are not limited thereto.

It should be noted that, for specific description of the pixel driving circuit of the display substrate 10, reference may be made to the content of a specific example of a pixel driving circuit shown in fig. 7 and fig. 8A to 8E, and details are not repeated herein.

In some embodiments of the present disclosure, as shown in fig. 3 to 6, the display substrate 10 further includes a first voltage source 181, and the second electrode pattern 140 is configured to receive a first voltage signal from the first voltage source 181, so that the second electrode pattern 140 has a stable voltage, thereby the stability of the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140 can be improved, and the interference of other structures or devices of the display substrate 10 located on the side of the second electrode pattern 140 away from the substrate 100 to the electrical signal transmitted on the first electrode pattern 130 can be further reduced or avoided by the first voltage signal. For example, the first voltage signal may be a high-level voltage signal or a low-level voltage signal, which is not limited in this respect by the embodiments of the present disclosure.

For example, as shown in fig. 3-6, the peripheral region 102 further includes a power trace pattern 182. The power trace pattern 182 is electrically connected to the first voltage source 181, and the second electrode pattern 140 is electrically connected to the power trace pattern 182 to receive a first voltage signal through the power trace pattern 182. Therefore, the layout structure of the display substrate 10 can be improved, which is beneficial to the display substrate 10 to realize a narrow frame design, and the manufacturing process of the display substrate 10 can be simplified.

For example, in some examples, in a direction parallel to the plate surface of the substrate base plate 100, the power trace pattern 182 may be located between the first voltage source 181 and the second electrode pattern 140, or may also be located on a side of the first voltage source 181 and the second electrode pattern 140 away from the display area 101; alternatively, in some examples, the power trace pattern 182 may also at least partially overlap the second electrode pattern 140 in a direction perpendicular to the plate surface of the substrate base plate 100, which is not limited in this regard by the embodiments of the present disclosure.

For example, the power trace pattern 182 may be disposed on the same layer as the source electrode 163 and the drain electrode 164 of the thin film transistor 160, and the second electrode pattern 140 is electrically connected to the power trace pattern 182 through, for example, a via structure penetrating the third insulating layer 1103, thereby optimizing the layout structure in the peripheral region 102 of the display substrate 10.

For example, in a direction parallel to the plate surface of the substrate 100, at least a portion (e.g., all portions) of the second electrode pattern 140 is electrically connected between the power trace pattern 182 and the plurality of pixel units 110, and the power trace pattern 182 provides the first voltage signal to at least a portion of the plurality of pixel units 110 through the second electrode pattern 140. Therefore, while the second electrode patterns 140 and the first electrode patterns 130 are used to form compensation capacitors to compensate for transmission loads on the signal lines 120 electrically connected to the first electrode patterns 130, the second electrode patterns 140 may also be used to transmit power voltage signals (i.e., first voltage signals) for display, so that the layout structure of the display substrate 10 may be further optimized, which is beneficial to the display substrate 10 to realize a narrow-frame design, and may also improve the stability of the display substrate 10.

For example, as shown in fig. 3, the second electrode pattern 140 may be electrically connected to a plurality of first power lines 183 in the display region 101 to transmit a first voltage signal provided by the first voltage source 181 to the pixel unit 110 through the first power lines 183. For example, the first power line 183 may be disposed at the same layer as the source electrode 163 and the drain electrode 164 of the thin film transistor 160, and the second electrode pattern 140 is electrically connected to the first power line 183 through, for example, a via structure penetrating the third insulating layer 1103.

For example, as shown in fig. 3 to 6, the peripheral region 102 of the display substrate 10 includes a plurality of first electrode patterns 130, and the plurality of first electrode patterns 130 are disposed at intervals. For example, in a direction parallel to the plate surface of the substrate base plate 100, the peripheral region 102 further includes a spacing pattern 190 located between two adjacent first electrode patterns 130 and insulated from the first electrode patterns 130, and the spacing pattern 190 may reduce or avoid signal interference between the adjacent first electrode patterns 130, so as to improve stability of the electrical signal transmitted on the first electrode patterns 130.

In some embodiments of the present disclosure, the spacing pattern 190 may be configured to receive a second voltage signal from a second voltage source different from the first voltage source, so that the spacing pattern 190 and the adjacent first electrode pattern 130 may form a capacitance in a plane parallel to the plate surface of the substrate 100, thereby further improving a compensation effect on a transmission load on the signal line 120 electrically connected to the first electrode pattern 130, and further improving stability and consistency of signal transmission effects of the plurality of signal lines 120 in the display area 101.

In some embodiments of the present disclosure, the spacing pattern 190 may also be electrically connected to the second electrode pattern 140 to receive the first voltage signal from the first voltage source 181, so that the layout structure in the peripheral region 102 of the display substrate 10 may be further optimized on the basis of forming the spacing pattern 190 and the adjacent first electrode pattern 130 into a capacitor in a plane parallel to the plate surface of the substrate 100, thereby facilitating the display substrate 10 to implement a narrow bezel design.

For example, as shown in fig. 3, the space pattern 190 may be electrically connected to the second electrode pattern 140 through the first power line 183. The spacer pattern 190 may be disposed at the same layer as the active layer 161 of the thin film transistor 160, and electrically connected to the first power line 183 through a via structure penetrating at least the first, second, and third insulating

layers

1101, 1102, and 1103, and further electrically connected to the second electrode pattern 140. Accordingly, the spacer pattern 190 and the active layer 161 of the thin film transistor 160 are formed in the same layer in the manufacturing process (for example, the same material layer is used for forming through the patterning process), so that the manufacturing process of the display substrate 10 can be further simplified, the manufacturing cost of the display substrate 10 can be reduced, and the display substrate 10 is advantageous for mass production and application.

In the embodiment of the present disclosure, the space pattern 190 extends in a linear type and has a long bar shape; in other embodiments of the present disclosure, the spacing pattern 190 may also extend in a curved shape, a broken line shape or other suitable contours, and the shape of the spacing pattern 190 may also be, for example, an oval shape, a square shape, a sawtooth shape or other suitable regular shape or irregular shape according to actual needs, which is not limited by the embodiments of the present disclosure.

For example, taking the elongated spacing pattern 190 shown in fig. 3-6 as an example, in the extending direction of the spacing pattern 190, the spacing pattern 190 includes a first end and a second end opposite to each other, and the first end is closer to the display area 101 than the second end. A first end of the interval pattern 190 may be electrically connected to the first power line 183, and further electrically connected to the second electrode pattern 140, for example, through a via structure penetrating at least the first, second, and third insulating

layers

1101, 1102, and 1103, thereby receiving a first voltage signal; the second end of the spacer pattern 190 may be in a suspended state and thus does not need to be provided with a corresponding via structure, thereby reducing vias required to be provided in the display substrate 10 and further simplifying the manufacturing process of the display substrate 10. Alternatively, in some other examples of the present disclosure, the first end and the second end of the spacing pattern 190 may be electrically connected to the first power line 183 or the second electrode pattern 140 through a via structure to simultaneously receive the first voltage signal, so as to improve stability of the first voltage signal transmitted on the spacing pattern 190, which is not limited by the embodiments of the present disclosure.

In some embodiments of the present disclosure, since the peripheral region 102 provided with the spacer pattern 190 at least partially surrounds the display region 101 and is disposed along the edge of the display region 101, by disposing the spacer pattern 190 in the same layer as the active layer 161 of the thin film transistor 160, excessive etching of the active layer of the display region 101 near the edge portion during the preparation process of the display substrate 10 may be reduced or avoided, so that the etching uniformity of the boundary position of the display region 101 may be improved, and a better etching effect may be achieved.

For example, as shown in fig. 3 to 6, the second electrode patterns 140 may be continuously disposed along the edge of the display region 101, and at least partially overlap and are spaced apart from the first electrode patterns 130 in a direction R1 perpendicular to the plate surface of the substrate 100, so as to improve the consistency and stability of the first voltage signal transmitted on the second electrode patterns 140, and thus improve the consistency and stability of the compensation capacitors respectively formed between the second electrode patterns 140 and the first electrode patterns 130, and further improve the signal transmission effect of the signal lines 120 electrically connected to the first electrode patterns 130. Meanwhile, the second electrode patterns 140 that are continuously disposed also help to simplify the manufacturing process of the display substrate 10 and reduce the manufacturing cost of the display substrate 10, thereby facilitating mass production and application of the display substrate 10.

For example, taking the specific example of the display substrate 10 shown in fig. 2A as an example, the second electrode patterns 140 may be continuously disposed along the edge of the display region 101 and have a step shape, that is, the electrode patterns at two upper and lower steps adjacent to each other are connected to each other, so as to form a whole second electrode pattern 140, thereby reducing the voltage drop when the first voltage signal is transmitted through the second electrode pattern 140, and further improving the brightness uniformity and consistency of the display screen.

For example, as shown in fig. 2A, the plurality of pixel units 110 includes a first column of pixel units 111 and a second column of pixel units 112, the number of pixel units 110 in the first column of pixel units 111 is less than the number of pixel units 110 in the second column of pixel units 112, and the signal line 120 electrically connected to the first column of pixel units 111 is electrically connected to one first electrode pattern 130, so that the transmission load of the signal line 120 electrically connected to the first column of pixel units 111 is compensated by the compensation capacitor formed between the first electrode pattern 130 and the second electrode pattern 140, and the signal transmission effect on the signal line 120 is improved, so that the signal transmission effect on the signal line 120 is substantially consistent with the signal transmission effect of other signal lines 120 (e.g., the signal line 120 electrically connected to the second column of pixel units 112).

For example, the signal line 120 electrically connected to the second column of pixel units 112 may be electrically connected to another first electrode pattern 130, and the compensation capacitance formed by the second electrode pattern 140 and one first electrode pattern 130 electrically connected to the signal line 120 electrically connected to the first column of pixel units 111 is larger than the compensation capacitance formed by the second electrode pattern 140 and another first electrode pattern 130 electrically connected to the signal line 120 electrically connected to the second column of pixel units 112. Thus, by compensating the transmission load of the signal line 120 electrically connected to the first column of pixel cells 111 and the transmission load of the signal line 120 electrically connected to the second column of pixel cells 112 with different compensation capacitances, respectively, it is possible to improve the consistency and stability between the signal transmission effect of the signal line 120 electrically connected to the first column of pixel cells 111 and the signal transmission effect of the signal line 120 electrically connected to the second column of pixel cells 112. Therefore, the consistency and stability of the signal transmission effect of the plurality of signal lines 120 in the display area 101 can be improved, the display effect of the provided display picture is further improved, and abnormal or bad display phenomena of the display picture are weakened or avoided.

For example, the plurality of pixel units 110 further include a third column of pixel units 113, and load compensation may be provided for the signal lines 120 electrically connected to the first column of pixel units 111 and the second column of pixel units 112 based on the transmission load of the signal lines 120 electrically connected to the third column of pixel units 113, so that the load of the signal lines 120 electrically connected to the first column of pixel units 111 and the second column of pixel units 112 and the load of the signal lines 120 electrically connected to the third column of pixel units 113 after compensation are substantially the same, so that the load of the signal lines 120 electrically connected to the columns of pixel units 110 in the display substrate 10 is substantially the same, thereby improving the uniformity of the signal transmission effect of each signal line 120 in the display area 101 and improving the display effect of the display screen.

For example, the lengths of the first and

second electrode patterns

130 and 140 in the column direction may be different, or the lengths of the first and

second electrode patterns

130 and 140 in the row direction may be different, for example, the lengths of the first and

second electrode patterns

130 and 140 in the column direction or the row direction may be designed to provide different load compensation. For example, taking the example of providing the data signal to each column of pixel units 110 in the display region 101 through the signal line 120, for a column including a smaller number of pixel units 110, a larger load compensation amount needs to be provided to the signal line 120 electrically connected to the column of pixel units 110, and therefore, the first electrode pattern 130 and the second electrode pattern 140 need to have a larger length in the column direction or the row direction, that is, the smaller the number of pixel units 110 included in a column, the larger the load compensation amount needs to be provided to the signal line 120 electrically connected to the column of pixel units 110. Thereby, the first electrode patterns 130 and the second electrode patterns 140 can be flexibly disposed in the peripheral region 102, thereby further optimizing the layout structure in the peripheral region 102 of the display substrate 10.

For example, when the transmission load on the signal line 120 electrically connected to the first electrode patterns 130 is compensated by the compensation capacitance formed between the first electrode patterns 130 and the second electrode patterns 140, according to different compensation amounts required, the first end or the second end of the signal line 120 may be electrically connected to one first electrode pattern 130 as shown in fig. 2A or fig. 2B, or the first end of the signal line 120 may be electrically connected to one first electrode pattern 130 and the second end may be electrically connected to another first electrode pattern 130 as shown in fig. 2C, that is, both ends of the signal line 120 may be electrically connected to two first electrode patterns 130, respectively, so as to increase the load compensation amount. Embodiments of the present disclosure are not limited in this regard.

In some embodiments of the present disclosure, the extending direction of at least a portion of the edge of the display area 101 of the display substrate 10 intersects with and is not perpendicular to the extending direction of the signal line 120, for example, the display substrate 10 may be designed to have different shapes or profiles according to the actual requirement of the user on the shape of the display substrate 10, and is not limited to a single square display substrate with a right angle.

For example, the display substrate provided by the embodiment of the present disclosure, for example, the display substrate 10 or the display substrate 20, may be an organic light emitting diode display substrate.

For example, the display substrate provided in the embodiments of the present disclosure may also be a substrate having a display function, such as a quantum dot light emitting diode display substrate, an electronic paper display substrate, or other types of display substrates, which is not limited in this respect.

Fig. 7 is an equivalent circuit diagram of a pixel driving circuit in a display substrate according to some embodiments of the disclosure, and fig. 8A to 8E are schematic diagrams of layers of the pixel driving circuit in the display substrate according to some embodiments of the disclosure. For example, the storage capacitor 170 shown in fig. 6 may be the storage capacitor Cst in the pixel driving circuit 7120 shown in fig. 7 and 8A, and the thin film transistor 160 shown in fig. 6 may be at least one of the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 in the pixel driving circuit 7120 shown in fig. 7 and 8A. It should be noted that the specific structure of the pixel driving circuit 7120 shown in fig. 7 and 8A is only an exemplary illustration, and the embodiments of the present disclosure include, but are not limited to, this.

In some embodiments, as shown in fig. 7, the pixel driving circuit 7120 includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7, a plurality of signal lines (e.g., including the signal line 120 in the above-described embodiment) connected to the plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst, and the plurality of signal lines include a gate line GL, a light emission control line EM, an initialization line RL, a data line DL, and a first power line VDD (e.g., the first power line 183 in the above-described embodiment). The gate lines GL may include a first gate line GLn and a second gate line GLn-1, for example, the first gate line GLn may be used to transmit a gate scan signal, and the second gate line GLn-1 may be used to transmit a reset signal. The emission control line EM may be used to transmit an emission control signal. Thus, the pixel drive circuit 7120 is the pixel drive circuit of 7T 1C.

For example, taking the signal line 120 in the above-described embodiment as the data line DL as an example, the transmission load of the data line DL electrically connected to the first electrode pattern 130 is compensated by the compensation capacitance Ccp formed between the first electrode pattern 130 and the second electrode pattern 140, thereby improving the compensation effect of the data signal transmitted on the data line DL.

For example, the first power line VDD may be directly electrically connected to the power trace pattern 182 in the above embodiment to receive the first voltage signal provided by the first voltage source 181, or may be electrically connected to the power trace pattern 182 by being electrically connected to the second trace pattern 140 in the above embodiment.

It should be noted that the embodiments of the present disclosure include, but are not limited to, that the pixel driving circuit 7120 may also adopt other types of circuit structures, such as a 7T2C structure or a 9T2C structure, and the embodiments of the present disclosure are not limited thereto.

For example, as shown in fig. 7, the first gate G1 of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4. The first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5. The first drain electrode D1 of the first thin film transistor T1 is electrically connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.

For example, as shown in fig. 7, the second gate electrode G2 of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive a gate scan signal, the second source electrode S2 of the second thin film transistor T2 is configured to be electrically connected to the data line DL to receive a data signal, and the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.

For example, as shown in fig. 7, the third gate G3 of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, the third source S3 of the third thin film transistor T3 is electrically connected to the first drain electrode D1 of the first thin film transistor T1, and the third drain D3 of the third thin film transistor T3 is electrically connected to the first gate G1 of the first thin film transistor T1.

For example, as shown in fig. 7, the fourth gate G4 of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, the fourth source S4 of the fourth thin film transistor T4 is configured to be electrically connected to the initialization line RL to receive an initialization signal, and the fourth drain D4 of the fourth thin film transistor T4 is electrically connected to the first gate G1 of the first thin film transistor T1.

For example, as shown in fig. 7, the fifth gate G5 of the fifth thin film transistor T5 is configured to be electrically connected to the emission control line EM to receive an emission control signal, the fifth source S5 of the fifth thin film transistor T5 is configured to be electrically connected to the first power line VDD to receive a first power signal, and the fifth drain D5 of the fifth thin film transistor T5 is electrically connected to the first source S1 of the first thin film transistor T1.

For example, as shown in fig. 7, the sixth gate G6 of the sixth thin film transistor T6 is configured to be electrically connected to the emission control line EM to receive an emission control signal, the sixth source S6 of the sixth thin film transistor T6 is electrically connected to the first drain D1 of the first thin film transistor T1, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (e.g., anode) of the light emitting element.

For example, as shown in fig. 7, the seventh gate G7 of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, the seventh source S7 of the seventh thin film transistor T7 is electrically connected to the first display electrode (e.g., anode) of the light emitting element, and the seventh drain D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive an initialization signal. For example, the seventh drain electrode D7 of the seventh thin film transistor T7 may be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.

For example, as shown in fig. 7, the storage capacitor Cst includes the first and second capacitor electrodes CE1 and CE2 (e.g., the first and

second capacitor electrodes

171 and 172 in the above-described embodiment). The second capacitor electrode CE2 is electrically connected to the first power line VDD, and the first capacitor electrode CE1 is electrically connected to the first gate G1 of the first thin film transistor T1 and the third drain D3 of the third thin film transistor T3.

For example, as shown in fig. 7, a second display electrode (e.g., a cathode) of the light emitting element is electrically connected to a second power supply line VSS.

One of the first power supply line VDD and the second power supply line VSS is a power supply line for supplying a high voltage, and the other is a power supply line for supplying a low voltage. In the embodiment shown in fig. 7, the first power line VDD (e.g., the first power line 183 electrically connected to the first voltage source 181) supplies a constant first voltage (i.e., the first voltage signal), which is a positive voltage; and the second power line VSS supplies a constant second voltage, which may be a negative voltage, etc. For example, in some examples, the second voltage may be a ground voltage.

It should be noted that, in some embodiments, the reset signal and the initialization signal may be the same signal.

It should be noted that, according to the characteristics of the transistors, the transistors may be divided into N-type transistors and P-type transistors, and for the sake of clarity, the transistors are exemplified as P-type transistors (for example, P-type MOS transistors) in the embodiments of the present disclosure, that is, in the description of the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the like may all be P-type transistors. However, the transistors of the embodiments of the present disclosure are not limited to P-type transistors, and one skilled in the art may also implement the functions of one or more transistors of the embodiments of the present disclosure by using N-type transistors (e.g., N-type MOS transistors) according to actual needs.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, and the like. The source and drain of the transistor may be symmetrical in structure, so that the source and drain may be physically indistinguishable, and all or part of the source and drain of the transistor may be interchanged as desired in embodiments of the present disclosure.

For example, fig. 8A is a schematic diagram showing a stacked positional relationship of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of the pixel driver circuit 7120.

Fig. 8B shows semiconductor layers of the pixel driving circuit 7120. As shown in fig. 8B, the semiconductor layer may be formed using semiconductor material patterning. The semiconductor layer may be used to form active layers of the first, second, third, fourth, fifth, sixth, and seventh thin film transistors T1, T2, T3, T4, T5, T6, and T7, which may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the semiconductor layer can be made of amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or the like. The source region and the drain region may be regions doped with n-type impurities or p-type impurities.

For example, the active layer 161 and the space pattern 190 in the above embodiments may be located in the above semiconductor layer.

In some embodiments of the present disclosure, a gate insulating layer (e.g., the second insulating layer 1102 in the above embodiments, not shown in fig. 8A to 8E) is formed on the above semiconductor layer to protect the above semiconductor layer.

Fig. 8C shows a first conductive layer of the pixel driving circuit 7120. For example, as shown in fig. 8C, a first conductive layer of the pixel driving circuit 7120 is provided over a gate insulating layer so as to be insulated from a semiconductor layer shown in fig. 8B. The first conductive layer may include the first capacitor electrode CE1, the first gate line GLn, the second gate line GLn-1, the emission control line EM, and the gates of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 of the storage capacitor Cst. As shown in fig. 8C, the gates of the second, fourth, sixth, and seventh thin film transistors T2, T4, T5, T6, and T7 may be portions where the first and second gate lines GLn and GLn-1 overlap the semiconductor layer, the third thin film transistor T3 may be a thin film transistor of a double gate structure, one gate of the third thin film transistor T3 may be a portion where the first gate line GLn overlaps the semiconductor layer, and the other gate of the third thin film transistor T3 may be a protrusion protruding from the first gate line GLn; the gate electrode of the first thin film transistor T1 may be the first capacitor electrode CE 1. The fourth thin film transistor T4 may be a thin film transistor of a double gate structure, where two gate electrodes are portions of the second gate line GLn-1 overlapping the semiconductor layer, respectively.

For example, the first electrode pattern 130, the gate electrode 162, and the first capacitor electrode 171 in the above embodiments may be located in the above first conductive layer.

In some embodiments of the present disclosure, a first interlayer insulating layer (e.g., the first insulating layer 1101 in the above embodiments, not shown in fig. 8A to 8E) is formed on the first conductive layer for protecting the first conductive layer.

Fig. 8D shows a second conductive layer of the pixel driving circuit 7120. For example, as shown in fig. 8D, the second conductive layer of the pixel driving circuit 7120 includes the second capacitive electrode CE2 of the storage capacitor Cst and the initialization line RL. The second capacitance electrode CE2 at least partially overlaps the first capacitance electrode CE1 to form a storage capacitance Cst.

For example, the second electrode pattern 140 and the second capacitor electrode 172 in the above embodiments may be located in the above second conductive layer.

In some embodiments, the second conductive layer may further include first light shielding portions 791 and second light shielding portions 792. The orthographic projection of the first light shielding portion 791 on the base substrate 710 covers the active layer of the second thin film transistor T2, the active layer between the drain electrode of the third thin film transistor T3 and the drain electrode of the fourth thin film transistor T4, thereby preventing external light from affecting the active layers of the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4. The orthographic projection of the second light shielding portion 792 on the base substrate 710 covers the active layer between the two gates of the third thin film transistor T3, thereby preventing external light from affecting the active layer of the third thin film transistor T3. The first light shielding portion 791 may be integrally configured with the second light shielding portion 792 of the adjacent pixel driving circuit, and electrically connected to the first power line VDD through a via hole penetrating the second interlayer insulating layer.

In some embodiments of the disclosure, a second interlayer insulating layer (e.g., the third insulating layer 1103 in the above embodiments, not shown in fig. 8A to 8E) is formed on the second conductive layer to protect the second conductive layer.

Fig. 8E shows a third conductive layer of the pixel driving circuit 7120. For example, as shown in fig. 8E, the third conductive layer of the pixel driving circuit 7120 includes a data line DL (e.g., the signal line 120 in the above-described embodiment) and a first power supply line VDD (e.g., the first power supply line 183 in the above-described embodiment). As shown in connection with fig. 8A and 8E, the data line DL is connected to the source region of the second thin film transistor T2 in the semiconductor layer through at least one via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power line VDD is connected to a source region of the semiconductor layer corresponding to the fifth thin film transistor T5 through at least one via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The first power supply line VDD is connected to the second capacitor electrode CE2 in the second conductive layer through at least one via hole in the second interlayer insulating layer.

For example, the power trace pattern 182, the signal line 120, the first power line 183, the source electrode 163, and the drain electrode 164 in the above embodiments may be located in the above third conductive layer.

For example, the third conductive layer further includes a first connection part CP1, a second connection part CP2, and a third connection part CP 3. One end of the first connection portion CP1 is connected to a drain region of the semiconductor layer corresponding to the third thin film transistor T3 through at least one via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and the other end of the first connection portion CP1 is connected to the gate electrode of the first thin film transistor T1 in the first conductive layer through at least one via hole in the first interlayer insulating layer and the second interlayer insulating layer. One end of the second connection part CP2 is connected to the initialization line RL through one via hole in the second interlayer insulating layer, and the other end of the second connection part CP2 is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer through at least one via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The third connection part CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer.

In some embodiments of the present disclosure, a protective layer (not shown in fig. 8A to 8E) is formed on the third conductive layer to protect the third conductive layer. A first display electrode (e.g., an anode) of a light emitting element in a pixel unit may be disposed on the protective layer.

At least one embodiment of the present disclosure also provides a display device including the display substrate according to any one of the embodiments of the present disclosure.

Fig. 9 is a schematic block diagram of a display device according to some embodiments of the present disclosure. For example, as shown in fig. 9, the display device 40 includes a display substrate 401, and the display substrate 401 may be a display substrate provided in any embodiment of the present disclosure, for example, the display substrate 10 or the display substrate 20 described above.

Fig. 10 is a schematic block diagram of another display device provided in some embodiments of the present disclosure. For example, as shown in fig. 10, the display device 50 includes a display substrate 501, and the display substrate 501 may be a display substrate provided in any embodiment of the present disclosure, for example, the display substrate 10 or the display substrate 20 described above.

For example, as shown in fig. 10, the display device 50 further includes a data driver 510, a gate driver 520, a timing controller 530, a voltage source 540, and the like. For example, the gate driver 520 may include the gate scan driving circuit 150 in the above-described embodiment regarding the display substrate 10, i.e., may be directly fabricated on the substrate through a semiconductor process; the voltage source 540 may include the first voltage source 181 in the embodiments described above with respect to the display substrate 10, and may be implemented, for example, as a power management circuit.

For example, in one example, a plurality of pixel cells P (e.g., pixel cells 110 in the embodiment described above with respect to display substrate 10) are arranged in an array in the display area of display substrate 501, each pixel cell P receiving a data signal provided by data driver 510 via data line DL and receiving a voltage signal provided by voltage source 540 via power line VDD. For example, in the case where the signal lines are data lines in the embodiment of the present disclosure, the data lines DL may include, for example, the signal lines 120 in the embodiment described above with respect to the display substrate 10. For example, the power supply line VDD may include the first power supply line 183 in the above-described embodiment with respect to the display substrate 10, for example.

For example, the data driver 510 converts digital image data RGB input from the timing controller 530 into data signals according to a data control signal DCS provided from the timing controller 530. For example, the data driver 510 converts the data signal into an analog voltage signal according to the data control signal DCS supplied from the timing controller 530, performs processing such as operational amplification on the analog voltage signal, and supplies the corresponding data signal to each pixel cell P through the data line DL. For example, the data driver 510 may be implemented as a semiconductor chip.

For example, the gate driver 520 is electrically connected to each pixel unit P through the scan line SL to supply a scan signal to each pixel unit P, respectively. For example, the gate driver 520 provides a gate signal according to a plurality of scan control signals GCS provided by the timing controller 530. For example, the gate driver 520 may be implemented as a semiconductor chip, or may be integrated in the display device 50 to form a GOA circuit, such as the gate scan driving circuit 150 in the above-described embodiment with respect to the display substrate 10.

For example, the timing controller 530 is used to process image data RGB input from the outside of the display device 50, supply the processed image data RGB to the data driver 510, and supply the data control signal DCS and the scan control signal GCS to the data driver 510 and the gate driver 520 to control the data driver 510 and the gate driver 520.

For example, the timing controller 530 processes externally input image data RGB to match the size and resolution of the display device 50 and then supplies the processed image data RGB to the data driver 510. The timing controller 530 generates the scan control signal GCS and the data control signal DCS using synchronization signals SYNC (e.g., a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from the outside of the display device 50. The timing controller 530 provides the data driver 510 and the gate driver 520 with the generated data control signal DCS and scan control signal GCS, respectively, for control of the data driver 510 and the gate driver 520.

The structures, functions, technical effects, and the like of the display device 40 and the display device 50 provided in the embodiment of the present disclosure can refer to the corresponding descriptions in the display substrate 10 or the display substrate 20 provided in the embodiment of the present disclosure, and are not described herein again.

For example, the display device 40 and the display device 50 provided by the embodiment of the present disclosure may be an organic light emitting diode display device. Alternatively, the display device 40 and the display device 50 provided in the embodiment of the present disclosure may also be a device having a display function, such as a quantum dot light emitting diode display device and an electronic paper display device, or another type of display device, and the embodiment of the present disclosure is not limited thereto.

For example, the display device 40 and the display device 50 provided in the embodiments of the present disclosure may be any product or component having a display function, such as a display substrate, a display panel, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator, and the embodiments of the present disclosure are not limited thereto.

The following points need to be explained:

(1) the drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to general designs.

(2) For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale. It will be understood that when an element such as a layer, film, region, or first substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display substrate having a display area and a peripheral area at least partially surrounding the display area, and comprising: a substrate base plate;

wherein the display region comprises a plurality of pixel units arranged on the substrate in an array manner and a plurality of signal lines respectively electrically connected with the pixel units,

the peripheral region includes at least one first electrode pattern electrically connected to at least one of the plurality of signal lines and includes a second electrode pattern,

the at least one first electrode pattern and the second electrode pattern are at least partially overlapped and arranged at intervals in an insulating mode in a direction perpendicular to the plate surface of the substrate base plate,

the peripheral region further includes a gate scan driving circuit configured to supply gate scan signals to the plurality of pixel units,

the at least one first electrode pattern and the second electrode pattern are located between the gate scan driving circuit and the display region in a direction parallel to a plate surface of the substrate base plate.

2. The display substrate of claim 1, wherein an orthographic projection of the at least one first electrode pattern on the substrate is within an orthographic projection of the second electrode pattern on the substrate.

3. A display substrate according to claim 1 or 2, wherein the second electrode pattern is located on a side of the at least one first electrode pattern remote from the substrate.

4. The display substrate of claim 3, wherein at least one of the plurality of pixel cells comprises a pixel driving circuit on the substrate, the pixel driving circuit comprising a thin film transistor and a storage capacitor;

the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode, and the storage capacitor comprises a first capacitor electrode and a second capacitor electrode opposite to the first capacitor electrode in the direction vertical to the plate surface of the substrate;

the source electrode and the drain electrode are positioned on one side of the active layer far away from the substrate base plate,

the first electrode pattern, the grid electrode and the first capacitor electrode are arranged on the same layer, and the second electrode pattern and the second capacitor electrode are arranged on the same layer.

5. The display substrate according to claim 4, wherein the plurality of signal lines are disposed at the same layer as the source and drain electrodes of the thin film transistor, and the at least one first electrode pattern is electrically connected to at least one of the plurality of signal lines through a via structure.

6. The display substrate of claim 4, wherein the second electrode pattern is configured to receive a first voltage signal from a first voltage source.

7. The display substrate of claim 6, wherein the peripheral region further comprises a power trace pattern,

the power trace pattern is electrically connected to the first voltage source, and the second electrode pattern is electrically connected to the power trace pattern to receive the first voltage signal via the power trace pattern.

8. The display substrate of claim 7, wherein the power trace pattern is disposed on the same layer as the source and drain electrodes of the thin film transistor,

the second electrode pattern is electrically connected with the power supply wiring pattern through a via structure.

9. The display substrate according to claim 7, wherein at least a part of the second electrode pattern is electrically connected between the power supply wiring pattern and the plurality of pixel units in a direction parallel to a plate surface of the substrate,

the power trace pattern provides the first voltage signal to at least some of the plurality of pixel cells through the second electrode pattern.

10. The display substrate of claim 6, wherein the at least one first electrode pattern comprises a plurality of first electrode patterns, the plurality of first electrode patterns being arranged at intervals;

the peripheral region further includes a space pattern between two adjacent first electrode patterns and insulated from the first electrode patterns.

11. The display substrate of claim 10, wherein the spacing pattern is configured to receive a second voltage signal from a second voltage source different from the first voltage source.

12. The display substrate of claim 10, wherein the spacing pattern is electrically connected with the second electrode pattern to receive the first voltage signal from the first voltage source.

13. The display substrate of claim 10, wherein the spacer pattern is disposed in a same layer as an active layer of the thin film transistor.

14. The display substrate according to claim 10, wherein the second electrode patterns are continuously disposed along an edge of the display area, and are respectively disposed at least partially overlapping and spaced apart from the plurality of first electrode patterns in a direction perpendicular to a plate surface of the substrate.

15. The display substrate according to claim 1 or 2, wherein an extending direction of at least a part of an edge of the display area intersects with and is not perpendicular to an extending direction of the plurality of signal lines.

16. The display substrate according to claim 1 or 2, wherein the display substrate further comprises a first insulating layer between the first electrode pattern and the second electrode pattern,

the material of the first insulating layer comprises silicon nitride or silicon oxynitride.

17. The display substrate according to claim 1 or 2, wherein the plurality of pixel units includes a first column of pixel units and a second column of pixel units, the number of pixel units in the first column of pixel units is less than the number of pixel units in the second column of pixel units, and a signal line electrically connected to the first column of pixel units is electrically connected to one first electrode pattern.

18. The display substrate of claim 17, wherein a signal line electrically connected to the second column of pixel cells is electrically connected to another first electrode pattern,

the second electrode pattern and the first electrode pattern electrically connected with the signal line electrically connected with the pixel unit of the first column form a compensation capacitance larger than that formed by the second electrode pattern and the other first electrode pattern electrically connected with the signal line electrically connected with the pixel unit of the second column.

19. The display substrate according to claim 1 or 2, wherein the first electrode pattern and the second electrode pattern have different lengths in a column direction, or

The first electrode patterns and the second electrode patterns are different in length in a row direction.

20. The display substrate according to claim 1 or 2, wherein the plurality of signal lines are scanning lines or data lines.

21. The display substrate according to claim 1 or 2, wherein the first end or the second end of at least one of the plurality of signal lines is electrically connected to one first electrode pattern, or

A first end of at least one of the plurality of signal lines is electrically connected to one of the first electrode patterns, and a second end of at least one of the plurality of signal lines is electrically connected to another one of the first electrode patterns.

22. A display device comprising the display substrate of any one of claims 1-21.