CN113870787A - GIP circuit for solving problem of incapability of action when Vth is negative value and driving method thereof - Google Patents
GIP circuit for solving problem of incapability of action when Vth is negative value and driving method thereof Download PDFInfo
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- CN113870787A CN113870787A CN202111151561.8A CN202111151561A CN113870787A CN 113870787 A CN113870787 A CN 113870787A CN 202111151561 A CN202111151561 A CN 202111151561A CN 113870787 A CN113870787 A CN 113870787A
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- 238000000034 method Methods 0.000 title claims abstract description 12
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 claims abstract description 54
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- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 claims abstract description 39
- 101710176144 Transcription cofactor vestigial-like protein 2 Proteins 0.000 claims abstract description 39
- 239000003990 capacitor Substances 0.000 claims abstract description 4
- 239000010409 thin film Substances 0.000 claims description 3
- 201000005569 Gout Diseases 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a GIP circuit for solving the problem that the Vth cannot be operated when the Vth is a negative value and a driving method thereof, wherein the circuit comprises transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13 and a capacitor C1; two groups of VGL signals of VGL _1 and VGL _2 are set to be connected with the GIP TFT, and the VGL _1 is connected with the VGL signals connected with the transistors T11, T13, T10, T11, T5 and T6; VGL _2 switches on the VGL signal to which transistors T2 and T12 are connected and causes VGL _1> VGL _ 2. The GIP circuit of the invention can still work normally when the Vth is a negative value.
Description
Technical Field
The invention relates to the technical field of panels, in particular to a GIP circuit for solving the problem that the Vth cannot act when being a negative value and a driving method thereof.
Background
With the development of the society, the touch display screen market products meet diversified demands, and products such as flat panels and the like have the development trend of being light, thin, low in power consumption and low in cost. For flat panels, to meet the requirements of low cost and low power consumption, a method of introducing MOX materials is generally used.
Because MOX has higher electron mobility than a-si, the MOX architecture can be designed to be smaller than the a-si architecture for both pixel and GIP devices under the same charging capability, and thus the MOX power consumption is smaller.
However, in the Vth characteristics, MOX is more negative than a silicon material, and the Vth of MOX material may be negative. As shown in fig. 1, in the case of GIP 13T1C 16pahse, G9 has a situation in which normal input is not achieved due to leakage of some elements of GIP current (fig. 2). Therefore, the invention provides a novel GIP circuit for solving the problem that the Gate cannot normally output when the Vth is a negative value.
Disclosure of Invention
The invention aims to provide a GIP circuit and a driving method thereof, which solve the problem that the Vth cannot be operated when the Vth is a negative value.
The technical scheme adopted by the invention is as follows:
a GIP circuit for solving the problem of incapability of action when Vth is a negative value comprises transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13 and a capacitor C1;
the gate of T1 is connected with gate line G (n-1), the drain of T1 is connected with Vfwd, and the source of T1 is connected with point Q;
the gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL _ 2;
the gate of T3 is connected to point P1, the drain of T3 is connected to point Q, and the source of T3 is connected to VGL _ 1;
the gate of T4 is connected to point Q, the drain of T4 is connected to CK, and the source of T4 is connected to gate line G (n);
the gate of T5 is connected to point P2, the drain of T5 is connected to gate line G (n), and the source of T5 is connected to VGL _ 1;
the gate of T6 is connected to point P1, the drain of T6 is connected to gate line G (n), and the source of T6 is connected to VGL _ 1;
the gate of T7 is connected to gate line G (n +1), the drain of T7 is connected to Vbwd, and the source of T7 is connected to point Q;
the grid and the drain of the T8 are respectively connected with V2, and the source of the T8 is connected with a point P1;
the gate of T9 is connected with V1, the drain of T9 is connected with point P1, and the source of T9 is connected with point P2;
the gate of T10 is connected with V1, the drain of T10 is connected with point P1, and the source of T10 is connected with VGL _ 1;
the gate of T11 is connected with V2, the drain of T11 is connected with point P2, and the source of T11 is connected with VGL _ 1;
the gate of T12 is connected to point Q, the drain of T12 is connected to point P2, and the source of T12 is connected to VGL _ 2;
the gate of T13 is connected to point P2, the drain of T13 is connected to point Q, and the source of T13 is connected to VGL _ 1;
one plate of C1 is connected to point Q, the other plate of C1 is connected to gate line G (n), and VGL _1> VGL _2 are satisfied.
Further, the GIP driving circuit array is disposed on the display panel and located at one side of the display panel.
Furthermore, a CK line, a V1 line, a V2 line, a Vfwd line, a Vbwd line, a VGL _2 line and a VGL _1 line are further arranged on the display panel, and the CK line, the V1 line, the V2 line, the Vfwd line, the Vbwd line, the VGL _2 line and the VGL _1 line are respectively connected with CK1, CK2, CK3, CK4, Vfwd, Vbwd, VGL _2 and VGL _1 lines in the GIP driving circuit.
Further, a CK line, a V1 line, a V2 line, a Vfwd line, a Vbwd line, a VGL _2 line, a VGL _1 line, and a CLR line are disposed at the GIP driving circuit side.
Further, the display panel is an OLED display panel or an LCD display panel.
Further, a driving IC is also included, and G (n-1), G (n), and G (n +1) are connected with the driving IC.
Further, the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, and T13 are all thin film transistors.
A driving method for solving the problem that a GIP circuit can not act when Vth is a negative value is applied to the GIP circuit which can not act when the Vth is a negative value, and the method comprises the following steps: two groups of VGL signals of VGL _1 and VGL _2 are set to be connected with the GIP TFT, and the VGL _1 is switched into the VGL signals connected with the transistors T11, T13, T10, T11, T5 and T6; VGL _2 switches on the VGL signal to which transistors T2 and T12 are connected and causes VGL _1> VGL _ 2.
By adopting the technical scheme, the invention aims at the situation that in the prior art, when the voltage Vth of the GIP TFT element is a negative value, the element is leaked, the original level of the voltage cannot be kept by the Q point due to the influence of the leakage, and the Gout cannot be normally output. The invention designs two groups of Vgl signals (only one group of Vgl _1 is designed in the original design), tightly closes the main leakage element, prevents the Q point from being influenced by leakage, and can still normally work when Vth is a negative value.
Drawings
The invention is described in further detail below with reference to the accompanying drawings and the detailed description;
FIG. 1 is a schematic diagram of a conventional T1C circuit structure;
FIG. 2 is a diagram of a prior art analog waveform without Gout output when Vth is negative;
FIG. 3 is a schematic diagram of a GIP circuit for solving the problem of the non-operation when Vth is negative according to the present invention;
FIG. 4 is a simulated waveform diagram of the normal output of Gout when Vth is negative according to the present invention;
FIG. 5 is a schematic diagram of the VgL _2 condition when Vth is a negative value and VgL _1= -10V, which satisfies the condition that Gout can normally output.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in one of fig. 3 to 5, the present invention discloses a GIP circuit for solving the problem of non-operation when Vth is negative, which includes transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13 and a capacitor C1;
the gate of T1 is connected with gate line G (n-1), the drain of T1 is connected with Vfwd, and the source of T1 is connected with point Q;
the gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL _ 2;
the gate of T3 is connected to point P1, the drain of T3 is connected to point Q, and the source of T3 is connected to VGL _ 1;
the gate of T4 is connected to point Q, the drain of T4 is connected to CK, and the source of T4 is connected to gate line G (n);
the gate of T5 is connected to point P2, the drain of T5 is connected to gate line G (n), and the source of T5 is connected to VGL _ 1;
the gate of T6 is connected to point P1, the drain of T6 is connected to gate line G (n), and the source of T6 is connected to VGL _ 1;
the gate of T7 is connected to gate line G (n +1), the drain of T7 is connected to Vbwd, and the source of T7 is connected to point Q;
the grid and the drain of the T8 are respectively connected with V2, and the source of the T8 is connected with a point P1;
the gate of T9 is connected with V1, the drain of T9 is connected with point P1, and the source of T9 is connected with point P2;
the gate of T10 is connected with V1, the drain of T10 is connected with point P1, and the source of T10 is connected with VGL _ 1;
the gate of T11 is connected with V2, the drain of T11 is connected with point P2, and the source of T11 is connected with VGL _ 1;
the gate of T12 is connected to point Q, the drain of T12 is connected to point P2, and the source of T12 is connected to VGL _ 2;
the gate of T13 is connected to point P2, the drain of T13 is connected to point Q, and the source of T13 is connected to VGL _ 1;
one plate of C1 is connected to point Q, the other plate of C1 is connected to gate line G (n), and VGL _1> VGL _2 are satisfied.
Further, the GIP driving circuit array is disposed on the display panel and located at one side of the display panel.
Furthermore, a CK line, a V1 line, a V2 line, a Vfwd line, a Vbwd line, a VGL _2 line and a VGL _1 line are further arranged on the display panel, and the CK line, the V1 line, the V2 line, the Vfwd line, the Vbwd line, the VGL _2 line and the VGL _1 line are respectively connected with CK1, CK2, CK3, CK4, Vfwd, Vbwd, VGL _2 and VGL _1 lines in the GIP driving circuit.
Further, a CK line, a V1 line, a V2 line, a Vfwd line, a Vbwd line, a VGL _2 line, a VGL _1 line, and a CLR line are disposed at the GIP driving circuit side.
Further, the display panel is an OLED display panel or an LCD display panel.
Further, a driving IC is also included, and G (n-1), G (n), and G (n +1) are connected with the driving IC.
Further, the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, and T13 are all thin film transistors.
A driving method for solving the problem that a GIP circuit can not act when Vth is a negative value is applied to the GIP circuit which can not act when the Vth is a negative value, and the method comprises the following steps: two groups of VGL signals of VGL _1 and VGL _2 are set to be connected with the GIP TFT, and the VGL _1 is switched into the VGL signals connected with the transistors T11, T13, T10, T11, T5 and T6; VGL _2 switches on the VGL signal to which transistors T2 and T12 are connected and causes VGL _1> VGL _ 2.
As shown in fig. 3 or 4, the present invention is described by taking a 13T1C 16phase circuit (fig. 3) as an example, when GIP Vth is negative, in order to prevent the Q point from being pulled down by T3/T13 Vgl, T3/T13 Vgs (P point voltage-Vgl _1) < Vth (normal time T3/T13 Vgs >0) is required to be satisfied, two sets of Vgl (only one set of Vgl _1 is required in the original design) are required to be provided to ensure that Gout can be output (fig. 4), and Vgl _1& Vgl _2 are connected to the GIP TFT as shown below.
(1) VgL _1 (VgL to which T1/T13/T10/T11/T5/T6 is connected)
(2) VgL _2 (VgL to which T2/T1 is connected). And VgL _1> VgL _2 must be satisfied.
As shown in fig. 5, it can be seen from the simulation that when VgL _1= -10V, Vgs of VgL _2= -12V-14V is >0, Gout can be normally output, and there is no abnormality.
When T2/T12 works, VgL _1= -10V, VgL _2= -12V to-14V are set, Vgs < Vth of T3/T13, T3/T13 does not work, and no electricity leakage occurs.
By adopting the technical scheme, the invention aims at the situation that in the prior art, when the voltage Vth of the GIP TFT element is a negative value, the element is leaked, the original level of the voltage cannot be kept by the Q point due to the influence of the leakage, and the Gout cannot be normally output. The invention designs two groups of Vgl signals (only one group of Vgl _1 is designed in the original design), tightly closes the main leakage element, prevents the Q point from being influenced by leakage, and can still normally work when Vth is a negative value.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (8)
1. A GIP circuit for solving the problem of non-operation when Vth is negative, characterized in that: the circuit comprises transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13 and a capacitor C1;
the gate of T1 is connected with gate line G (n-1), the drain of T1 is connected with Vfwd, and the source of T1 is connected with point Q;
the gate of T2 is connected to point Q, the drain of T2 is connected to point P1, and the source of T2 is connected to VGL _ 2;
the gate of T3 is connected to point P1, the drain of T3 is connected to point Q, and the source of T3 is connected to VGL _ 1;
the gate of T4 is connected to point Q, the drain of T4 is connected to CK, and the source of T4 is connected to gate line G (n);
the gate of T5 is connected to point P2, the drain of T5 is connected to gate line G (n), and the source of T5 is connected to VGL _ 1;
the gate of T6 is connected to point P1, the drain of T6 is connected to gate line G (n), and the source of T6 is connected to VGL _ 1;
the gate of T7 is connected to gate line G (n +1), the drain of T7 is connected to Vbwd, and the source of T7 is connected to point Q;
the grid and the drain of the T8 are respectively connected with V2, and the source of the T8 is connected with a point P1;
the gate of T9 is connected with V1, the drain of T9 is connected with point P1, and the source of T9 is connected with point P2;
the gate of T10 is connected with V1, the drain of T10 is connected with point P1, and the source of T10 is connected with VGL _ 1;
the gate of T11 is connected with V2, the drain of T11 is connected with point P2, and the source of T11 is connected with VGL _ 1;
the gate of T12 is connected to point Q, the drain of T12 is connected to point P2, and the source of T12 is connected to VGL _ 2;
the gate of T13 is connected to point P2, the drain of T13 is connected to point Q, and the source of T13 is connected to VGL _ 1;
one plate of C1 is connected to point Q, the other plate of C1 is connected to gate line G (n), and VGL _1> VGL _2 are satisfied.
2. The GIP circuit for solving the problem of the non-operation of Vth at negative value as claimed in claim 1, wherein: the GIP driving circuit array is arranged on the display panel and is positioned on one side of the display panel.
3. The GIP circuit for solving the problem of the non-operation when Vth is negative as claimed in claim 2, wherein: the display panel is also provided with a CK line, a V1 line, a V2 line, a Vfwd line, a Vbwd line, a VGL _2 line and a VGL _1 line, wherein the CK line, the V1 line, the V2 line, the Vfwd line, the Vbwd line, the VGL _2 line and the VGL _1 line are respectively connected with the CK1, the CK2, the CK3, the CK4, the Vfwd, the Vbwd, the VGL _2 and the VGL _1 line in the GIP driving circuit.
4. The GIP circuit for solving the problem of the non-operation of Vth at negative value as claimed in claim 1, wherein: the CK line, the V1 line, the V2 line, the Vfwd line, the Vbwd line, the VGL _2 line, the VGL _1 line, and the CLR line are disposed at the GIP driving circuit side.
5. The GIP circuit for solving the problem of the non-operation when Vth is negative as claimed in claim 2, wherein: the display panel is an OLED display panel or an LCD display panel.
6. The GIP circuit for solving the problem of the non-operation of Vth at negative value as claimed in claim 1, wherein: the driver IC is further included, and G (n-1), G (n), and G (n +1) are connected with the driver IC.
7. The GIP circuit for solving the problem of the non-operation of Vth at negative value as claimed in claim 1, wherein: the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, and T13 are all thin film transistors.
8. A method for driving a GIP circuit which can not operate when Vth is a negative value is applied to the GIP circuit which can not operate when the Vth is a negative value, and the method comprises the following steps: two groups of VGL signals of VGL _1 and VGL _2 are set to be connected with the GIP TFT, and the VGL _1 is switched into the VGL signals connected with the transistors T11, T13, T10, T11, T5 and T6; VGL _2 switches on the VGL signal to which transistors T2 and T12 are connected and causes VGL _1> VGL _ 2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111151561.8A CN113870787A (en) | 2021-09-29 | 2021-09-29 | GIP circuit for solving problem of incapability of action when Vth is negative value and driving method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111151561.8A CN113870787A (en) | 2021-09-29 | 2021-09-29 | GIP circuit for solving problem of incapability of action when Vth is negative value and driving method thereof |
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| CN112331149A (en) * | 2020-10-27 | 2021-02-05 | 福建华佳彩有限公司 | Grid circuit and driving method |
| CN112735322A (en) * | 2021-01-22 | 2021-04-30 | 福建华佳彩有限公司 | GIP circuit and driving method |
| WO2021109219A1 (en) * | 2019-12-05 | 2021-06-10 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit |
| CN112992094A (en) * | 2021-02-23 | 2021-06-18 | 福建华佳彩有限公司 | GIP circuit driving method and display device |
| CN113035109A (en) * | 2021-02-25 | 2021-06-25 | 福建华佳彩有限公司 | GIP driving circuit of embedded display screen and control method thereof |
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2021
- 2021-09-29 CN CN202111151561.8A patent/CN113870787A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102047973B1 (en) * | 2018-12-03 | 2019-12-02 | 성균관대학교산학협력단 | Gate Drive Circuit and Display Device including the same |
| WO2021109219A1 (en) * | 2019-12-05 | 2021-06-10 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit |
| CN112331149A (en) * | 2020-10-27 | 2021-02-05 | 福建华佳彩有限公司 | Grid circuit and driving method |
| CN112735322A (en) * | 2021-01-22 | 2021-04-30 | 福建华佳彩有限公司 | GIP circuit and driving method |
| CN112992094A (en) * | 2021-02-23 | 2021-06-18 | 福建华佳彩有限公司 | GIP circuit driving method and display device |
| CN113035109A (en) * | 2021-02-25 | 2021-06-25 | 福建华佳彩有限公司 | GIP driving circuit of embedded display screen and control method thereof |
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