CN113867518A - Processor low-power consumption blocking type time delay method, device and readable medium - Google Patents
Processor low-power consumption blocking type time delay method, device and readable medium Download PDFInfo
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- CN113867518A CN113867518A CN202111081449.1A CN202111081449A CN113867518A CN 113867518 A CN113867518 A CN 113867518A CN 202111081449 A CN202111081449 A CN 202111081449A CN 113867518 A CN113867518 A CN 113867518A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
Abstract
The invention relates to a blocking type time delay method, a blocking type time delay device and a technical scheme of a readable medium with low power consumption of a processor, which comprise the following steps: acquiring a first delay state of a processor, and determining the initial delay time, the delay length and the overtime time point of the first delay state; determining the residual delay time of the first delay state according to the current time, the delay length and the overtime time point; and starting a timer, keeping the processor in a first running state within the residual time delay time constant through the timer, and returning the processor to a second running state after the residual time delay time constant is ended. The invention has the beneficial effects that: the processor resource is saved, and the power consumption of the processor in the blocking type delay is reduced.
Description
Technical Field
The invention relates to the field of computers, in particular to a low-power-consumption blocking type time delay method and device of a processor and a readable medium.
Background
In the operating process of an operating system, many scenes need to be delayed, for example, when a clock is initialized in the system starting stage, the phase-locked loop needs to be delayed for stabilization, and when a display screen is initialized, a hardware signal needs to be delayed for stabilization. There are generally two implementations of latency: blocking delay and non-blocking delay. Blocking latency is when the processor waits in place without switching to other tasks. Many scenarios are not capable of task switching, such as a critical section that can be accessed by only one task during interrupt processing, an early stage of start-up in which a task scheduling function is not ready, and the like. The non-blocking type delay finger processor leaves the original task and is switched to other tasks to execute, if no other tasks exist, the idle task is executed, and the low power consumption state is entered; and when the time delay expires, switching back to the original task, and continuously executing the program after the time delay. Since the processor can run other tasks or enter a low power state during the delay, processor resources can be fully utilized or system power consumption can be reduced.
Generally, in the system operation, most scenarios use non-blocking delay, and only when the non-blocking scenario cannot be used, the blocking delay is used. The conventional method is shown in fig. 1, and the flow of the blocking type delay method includes: firstly, acquiring starting time and storing variables of the starting time; then adding the delay length to the start time to obtain the delayed overtime time; then, circularly judging whether the time delay is finished or not, namely continuously acquiring the current time of the current system, comparing the current time with the overtime, and finishing when the time delay exceeds the overtime.
In the traditional method, during the blocking type delay period, the processor is always operated at full speed, but the loop is only used for judging whether the delay is finished or not, and other things are not processed. Thus resulting in wasted processor resources and higher processor power consumption.
Disclosure of Invention
The present invention is directed to solve at least one of the problems in the prior art, and provides a low-power blocking type delay method, apparatus and readable medium for a processor, which reduces the power consumption of the processor during the delay.
The technical scheme of the invention comprises a blocking type time delay method with low power consumption of a processor, which is characterized by comprising the following steps: acquiring a first delay state of a processor, and determining the initial delay time, the delay length and the overtime time point of the first delay state; determining the residual delay time of the first delay state according to the current time, the delay length and the overtime time point; and starting a timer, keeping the processor in a first running state within the residual time delay time by the timer, and returning the processor to a second running state after the residual time delay time is over.
The processor low-power consumption blocking type time delay method comprises the following steps of: acquiring the starting time, and calculating the sum of the starting time and the delay length as the timeout time point; and after the timeout time point is determined, executing the delay processing of the next step.
The processor low-power consumption blocking type delay method, wherein the step of determining the residual delay of the first delay state according to the current time, the delay length and the overtime time point comprises the following steps: subtracting the starting time from the timeout time point to obtain the residual delay time; and if the residual time delay is often larger than a set threshold, executing the next step, wherein the set threshold can be adjusted in a self-defined manner.
The processor low-power consumption blocking type time delay method further comprises the following steps: if the residual delay is often smaller than the set threshold value, the processor is kept in a second delay state, and when the processor is in the second delay state, the current time and the timeout time point are monitored in a circulating mode until the current time is larger than or equal to the timeout time point, and then the processor exits from the second delay state.
The first operation state and the second operation state are respectively a low power consumption state and a non-low power consumption state, and the first operation state and the second operation state are switched through the timer.
The processor low-power blocking delay method, wherein the timer is configured as a high-precision timer.
The technical scheme of the invention comprises a processor low-power consumption blocking type time delay device which comprises a memory, a processor and a computer program which is stored in the memory and can run on the processor, and is characterized in that any one of the method steps is realized when the processor executes the computer program.
An aspect of the invention includes a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the method steps.
The invention has the beneficial effects that: the processor resource is saved, and the power consumption of the processor in the blocking type delay is reduced.
Drawings
The invention is further described below with reference to the accompanying drawings and examples;
fig. 1 is a time-delay flow chart of the prior art method.
Fig. 2 shows a flow diagram according to an embodiment of the invention.
FIG. 3 is a block-type delay for low power consumption of a processor according to an embodiment of the present invention.
Fig. 4 shows a diagram of an apparatus according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number.
In the description of the present invention, the consecutive reference numbers of the method steps are for convenience of examination and understanding, and the implementation order between the steps is adjusted without affecting the technical effect achieved by the technical solution of the present invention by combining the whole technical solution of the present invention and the logical relationship between the steps.
In the description of the present invention, unless otherwise explicitly defined, terms such as set, etc. should be broadly construed, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the detailed contents of the technical solutions.
Chinese-english control in this application:
start, start time;
now, the current time (of the operating system);
time _ delay, delay length;
expire, timeout time;
remaining, often remaining delay.
Fig. 2 shows a flow diagram according to an embodiment of the invention. The process of this embodiment includes the following steps:
s100, acquiring a first delay state of a processor, and determining the initial delay time, the delay length and the overtime time point of the first delay state; s200, determining the residual delay time of the first delay state frequently according to the current time, the delay length and the overtime time point; s300, starting a timer, keeping the processor in a first running state within the residual time delay time constant through the timer, and returning the processor to a second running state after the residual time delay time constant is ended. The first operation state and the second operation state are respectively a low power consumption state and a non-low power consumption state of the processor.
In order to ensure the stable and error-free implementation of the first delay state, a high-precision timer is generally adopted as the timer.
Fig. 3 shows a specific implementation of blocking type delay with low power consumption of a processor according to an embodiment of the present invention, where the process of this embodiment includes:
firstly, obtaining the initial time of the time delay, then adding the initial time to the time delay length to obtain the overtime time, and then entering a time delay main process, namely a first time delay process of the first embodiment.
Obtaining the current time of the system, subtracting the current time from the overtime time to obtain the residual delay time, and if the residual delay time is less than or equal to 0, indicating that the delay is due, ending the delay process; if the residual delay time is longer than the delay threshold, starting a high-precision timer, setting the interval as the residual delay time, switching the processor to a low-power-consumption mode, and waiting to be awakened by hardware interruption (such as interruption of a set timer) or an event; if the residual delay time is less than or equal to the delay threshold, similar to the traditional method, the current time is obtained in a circulating mode and judged until the delay is finished.
The setting of the delay threshold is mainly based on the following considerations: because the high-precision timer is started, the processor needs to consume the processor time when entering or exiting the low-power consumption mode, and the like, when the duration of the residual delay is so small that the high-precision timer is not enough to be started, and the like, the use of the timer may cause the delay to exceed the preset time, thereby causing inaccurate delay. A delay threshold is thus set and a high-precision timer is used only if the duration of the remaining delay is greater than the threshold.
Fig. 4 shows a diagram of an apparatus according to an embodiment of the invention. The apparatus comprises a memory 100 and a processor 200, wherein the processor 200 stores a computer program for performing: acquiring a first delay state of a processor, and determining the initial delay time, the delay length and the overtime time point of the first delay state; determining the residual delay time of the first delay state according to the current time, the delay length and the overtime time point; and starting a timer, keeping the processor in a first running state within the residual time delay time constant through the timer, and returning the processor to a second running state after the residual time delay time constant is ended.
It should be recognized that the method steps in embodiments of the present invention may be embodied or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The method may use standard programming techniques. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Further, the operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and/or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) collectively executed on one or more processors, by hardware, or combinations thereof. The computer program includes a plurality of instructions executable by one or more processors.
Further, the method may be implemented in any type of computing platform operatively connected to a suitable interface, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention also includes the computer itself when programmed according to the methods and techniques described herein.
A computer program can be applied to input data to perform the functions described herein to transform the input data to generate output data that is stored to non-volatile memory. The output information may also be applied to one or more output devices, such as consumers. In a preferred embodiment of the present invention, the transformed data represents physical and tangible objects, including particular visual depictions of physical and tangible objects produced on the consumer.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (8)
1. A low-power consumption blocking type time delay method of a processor is characterized by comprising the following steps:
acquiring a first delay state of a processor, and determining the initial delay time, the delay length and the overtime time point of the first delay state;
determining the residual delay time of the first delay state according to the current time, the delay length and the overtime time point;
and starting a timer, keeping the processor in a first running state within the residual time delay time by the timer, and returning the processor to a second running state after the residual time delay time is over.
2. The processor low-power consumption blocking type delay method according to claim 1, wherein the determining the delay starting time, the delay length and the timeout time point of the first delay state comprises:
acquiring the starting time, and calculating the sum of the starting time and the delay length as the timeout time point;
and after the timeout time point is determined, executing the delay processing of the next step.
3. The processor low-power blocking delay method of claim 1, wherein said determining the remaining delay of the first delay state according to the current time, the delay length and the timeout point in time comprises:
subtracting the starting time from the timeout time point to obtain the residual delay time;
and if the residual time delay is often larger than a set threshold, executing the next step, wherein the set threshold can be adjusted in a self-defined manner.
4. A processor low power blocking delay method as claimed in claim 3, further comprising:
if the residual delay is often smaller than the set threshold value, the processor is kept in a second delay state, and when the processor is in the second delay state, the current time and the timeout time point are monitored in a circulating mode until the current time is larger than or equal to the timeout time point, and then the processor exits from the second delay state.
5. The processor low-power blocking delay method according to claim 1, wherein the first operating state and the second operating state are a low-power state and a non-low-power state, respectively, and the first operating state and the second operating state are switched by the timer.
6. A low power consumption blocking delay method for a processor as recited in claim 1, wherein said timer is configured as a high precision timer.
7. A processor low power consumption blocking delay comprising a memory, a processor and a computer program stored in said memory and executable on said processor, wherein said processor implements the method steps of any of claims 1 to 6 when executing said computer program.
8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method steps of any one of claims 1 to 6.
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| CN202111081449.1A CN113867518A (en) | 2021-09-15 | 2021-09-15 | Processor low-power consumption blocking type time delay method, device and readable medium |
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| CN202111081449.1A CN113867518A (en) | 2021-09-15 | 2021-09-15 | Processor low-power consumption blocking type time delay method, device and readable medium |
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