CN113852373A - Assembly line domino structure successive approximation type analog-to-digital converter - Google Patents
Assembly line domino structure successive approximation type analog-to-digital converter Download PDFInfo
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Abstract
The invention provides a sequential approximation type analog-to-digital converter with a flow line domino structure, which comprises: the device comprises an n + 1-stage sub ADC, a plurality of residual error amplifiers and a preset adjusting module; the input end of the 1 st-stage sub ADC is connected with the signal input end and used for obtaining an input signal after sampling; the output ends of the sub-ADCs comprise first output ends, the first output ends are connected with the preset adjusting module and used for inputting the 5-bit quantization codes generated by each sub-ADC into the preset adjusting module, so that the preset adjusting module can splice and correct redundant bits of the quantization codes to obtain an analog-to-digital conversion result; the 1 st-nth stage sub-ADCs further comprise second output ends, and the second output ends are used for taking signals generated by the residual difference signals generated by the sub-ADCs after being amplified by the residual difference amplifiers as input signals and inputting the input signals to the next stage sub-ADC. The invention improves the conversion speed and precision of the SAR ADC, can correct offset voltage in real time in the working process of the comparator and prevents the performance of the sub-ADC from being influenced by offset accumulation.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a sequential approximation type analog-to-digital converter with a flow line domino structure.
Background
With the rapid development of integrated circuits, the performance requirements of portable electronic application fields such as wireless communication, image and video for ADCs (Analog to Digital converters) are increasing, and the design of high resolution, high conversion rate, low distortion and low power consumption has become a major challenge for the design of the ADC.
At present, the analog-to-digital converter mostly adopts a pipeline structure, and the compromise of the analog-to-digital converter on conversion speed, precision and power consumption is realized through the cascade connection of a plurality of sub-ADCs and a conversion mode of pipeline work. A SAR ADC (Successive Approximation analog-to-digital converter) is a common analog-to-digital converter, and in order to implement a high-speed SAR ADC, a time domain interleaving and pipeline structure is generally adopted in the related art. However, mismatch between multiple channels of the time-domain interleaved SAR ADC seriously affects the performance of the ADC, and the pipelined SAR ADC replaces the fully parallel ADC in the pipeline with the SAR ADC, which is limited by the speed of the conventional asynchronous SAR ADC.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a pipelined domino architecture successive approximation analog-to-digital converter. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a sequential approximation type analog-to-digital converter with a flow line domino structure, which comprises: the device comprises an n + 1-stage sub ADC, a plurality of residual error amplifiers and a preset adjusting module; wherein,
the sub-ADC comprises an input end and an output end, wherein the input end of the 1 st-stage sub-ADC is connected with the signal input end and is used for obtaining an input signal after sampling; the output end of the sub-ADC comprises a first output end, and the first output end is connected with the preset adjusting module and used for inputting the 5-bit quantization codes generated by the sub-ADC into the preset adjusting module, so that the preset adjusting module can splice and correct redundant bits of the 5-bit quantization codes generated by each sub-ADC to obtain an analog-to-digital conversion result;
the 1 st-nth-stage sub ADC also comprises a second output end, the second output end is connected to the next-stage sub ADC through the residual error amplifier, and the second output end is used for taking a signal generated by the sub ADC and amplified by the residual error amplifier as an input signal and inputting the input signal to the next-stage sub ADC.
In one embodiment of the present invention, the apparatus further comprises a first reference voltage signal terminal, a second reference voltage signal terminal and a third reference voltage signal terminal, wherein the signal input terminals comprise a first signal input terminal and a second signal input terminal;
the sub-ADC includes: the circuit comprises a first module, a second module, a calibration circuit and an output module, wherein the first module comprises a comparator: the circuit comprises preset logic circuits corresponding to A1-A5, a first type capacitor, a second type capacitor, a first type switch, a second type switch and A1-A5 respectively, wherein the first type switch comprises a plurality of first switch groups, the second type switch comprises a plurality of second switch groups, each first switch group comprises three first switches, and each second switch group comprises three second switches; wherein,
the first input end of each comparator is connected with the first signal input end, the second input end of each comparator is connected with the second signal input end, and the output end of each comparator is connected with a corresponding preset logic circuit; the first ends of the first-class capacitors are connected with the first signal input end, and the second ends of the first-class capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three first switches in the first switch group respectively;
and the first ends of the second type capacitors are connected with the second signal input end, and the second ends of the second type capacitors are respectively connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three second switches in the second switch group.
In an embodiment of the present invention, in the 1 st to nth stage sub-ADCs, the first type capacitor includes: cs 1-Cs 5, the second type of capacitor comprising: the capacitance ratio of Cs 6-Cs 10, Cs1, Cs2, Cs3, Cs4 and Cs5 is 16:8:4:2:1, and the capacitance ratio of Cs6, Cs7, Cs8, Cs9 and Cs10 is 16:8:4:2: 1.
In one embodiment of the present invention, the 1 st-stage sub-ADC further comprises a second module, the second module comprises a third type of capacitor, a fourth type of capacitor, a third type of switch and a fourth type of switch, the third type of switch comprises a plurality of third switch groups, the fourth type of switch comprises a plurality of fourth switch groups, each third switch group comprises three third switches, and each fourth switch group comprises three fourth switches; wherein,
the first ends of the third capacitors are connected with the first signal input end, and the second ends of the third capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three third switches in the third switch group respectively;
the first ends of the fourth capacitors are all connected with the second signal input end, and the second ends of the fourth capacitors are respectively connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three fourth switches in the fourth switch group.
In an embodiment of the present invention, in the 1 st-stage sub-ADC, the third type of capacitor includes: cs 11-Cs 15, the second type of capacitor comprising: the capacitance ratio of Cs 16-Cs 20, Cs11, Cs12, Cs13, Cs14 and Cs15 is 16:8:4:2:1, and the capacitance ratio of Cs16, Cs17, Cs18, Cs19 and Cs20 is 16:8:4:2: 1.
In an embodiment of the present invention, the sub-ADC further includes a calibration circuit and an output module, wherein the calibration circuit is configured to calibrate the offset voltages of a 1-a 5, and the output module is configured to store the 5-bit quantization codes generated by the sub-ADC.
In one embodiment of the invention, the power supply further comprises a power supply signal terminal; the comparator includes a first sub-module and a second sub-module, the first sub-module including a first transistor: M1-M7 and an inverter: b1, B2, the second submodule comprising a second transistor: M8-M14 and an inverter: B1-B4; wherein,
a source of M1 is connected with the power signal end, a drain of M2 is connected with the source of M2, and a gate of M4, a gate of M2 is connected with the second signal input end, a drain of M4 is connected with the drain of M4, a source of M8538 is grounded, a first node is included between the drain of M1 and the source of M2, a gate of M3 is connected with the second reference voltage signal end, a source of M3 is connected with the first node, and a drain of M4 is connected with the second node, a third node is included between the drain of M2, a source of M4 is grounded, a gate of M5 is connected with a clock signal, a drain of M6 is connected with the first reset signal, a drain of M6 is connected with the second node, and a source of M7 is connected with the second reset signal, a drain of M7 is connected with the second node, and a source of M4 is grounded; the input end of B1 is connected with the drain of M4, and the output end of B1 is connected with the input end of B2;
a source of the M8 is connected with the power signal end, a drain of the M8 is connected with a source of the M9, and a gate of the M12 is connected with a gate of the M11, a gate of the M9 is connected with the second signal input end, a drain of the M9 is connected with a drain of the M11, a source of the M11 is grounded, a fourth node is arranged between the drain of the M8 and the source of the M9, a gate of the M10 is connected with the second reference voltage signal end, a source of the M10 is connected with the fourth node, and a drain of the M11 is connected with the fifth node, a sixth node is arranged between the drain of the M11 and the drain of the M9, a source of the M11 is grounded, a gate of the M12 is connected with a clock signal, a drain of the M3556 is connected with the fifth node, and a source of the M13 is grounded, a gate of the M14 is connected with the second reset signal, a drain of the M3583 is connected with the fifth node, and a drain of the M3583 is connected with the fifth node; the input end of B3 is connected with the drain of M11, and the output end of B3 is connected with the input end of B4;
the third node is connected with the gate of M8, and the sixth node is connected with the gate of M1.
In one embodiment of the invention, M1, M2, M3, M8, M9 and M10 are P-type field effect transistors, and M4, M5, M6, M7, M11, M12, M13 and M14 are N-type super-effect transistors.
In one embodiment of the present invention, the calibration circuit includes a third transistor: M15-M25, a preset current source, and gate: c1 and C2, and inverter B5; wherein,
the gate of M15 is connected with the gate of M16, the source of M15 and the source of M16 are both connected with the power signal end, the drain of M15 is connected with the source of M17, the gate of M17 is grounded, the drain of M19 is connected, the source of M19 is connected with the drain of M21, the source of M21 is grounded, the drain of M16 is connected with the source of M18, the gate of M18 is connected with the first switch signal, the drain of M18 is connected with the drain of M20, a seventh node is arranged between the drain of M18 and the drain of M20, the seventh node is connected to the first reference voltage, the gate of M20 is connected to the second switching signal, the source is connected to the drain of M22, the source of M22 is grounded, the gate is connected to the predetermined current source, an eighth node is arranged between the preset current source and the gate of the M22, the gate of the M23 and the gate of the M21 are both connected with the eighth node, the drain of the M23 is connected with the preset current source, and the source of the M23 is grounded;
the first input end and the second input end of the comparator are connected through a first switch, the third input end is connected with the first reference voltage, the first output end is connected with the first input end of C1, the second output end is connected with the first input end of C2, the second input end of C1 and the second input end of C2 are both connected to enable signals, the grid of M24 is connected with the power signal end, the source of M24 and the source of M25 are connected to a ninth node, the ninth node is connected with the second switch signal, the drain of M24 and the drain of M25 are connected to a tenth node, the tenth node is connected with the output end of C1, the grid of M25 is grounded, and the output end of C2 is connected with the input end of an inverter B5.
Compared with the related art, the invention has the beneficial effects that:
the invention provides a sequential approximation type analog-to-digital converter with a flow line domino structure, which comprises: the device comprises an n + 1-stage sub ADC, a plurality of residual error amplifiers and a preset adjusting module; the sub-ADC comprises an input end and an output end, wherein the input end of the 1 st-stage sub-ADC is connected with the signal input end and is used for obtaining an input signal after sampling; the output end of each sub-ADC comprises a first output end, and the first output end is connected with the preset adjusting module and used for inputting the 5-bit quantization codes generated by the sub-ADCs into the preset adjusting module so that the adjusting module can splice and correct redundant bits of the 5-bit quantization codes generated by each sub-ADC to obtain an analog-to-digital conversion result; the 1 st-nth stage sub-ADCs further comprise second output ends, the second output ends are connected to the next stage sub-ADCs through residual difference amplifiers, and signals generated by residual difference signals generated by the sub-ADCs and amplified by the residual difference amplifiers are used as input signals and input to the next stage sub-ADCs. The invention adopts a multi-stage sub-ADC structure, improves the conversion speed and the precision of the SAR ADC, and can correct offset voltage in real time in the working process of the comparator because each sub-ADC comprises a calibration circuit, thereby preventing the performance of the sub-ADC from being reduced due to offset accumulation of the comparator.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a pipelined domino architecture successive approximation type analog-to-digital converter according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a1 st-stage sub-ADC according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of the 2 nd to n th-stage sub-ADCs provided in the embodiment of the present invention;
fig. 4 is a schematic structural diagram of an n +1 th sub-ADC provided in the embodiment of the present invention;
FIG. 5 is a schematic diagram of a comparator according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a latch of the comparator according to the embodiment of the present invention;
FIG. 7 is a schematic diagram of a calibration circuit according to an embodiment of the present invention;
fig. 8 is a timing diagram illustrating the operation of the 1 st-stage sub-ADC according to the embodiment of the present invention;
fig. 9 is a timing diagram illustrating the operation of the 2 nd sub-ADC according to the embodiment of the present invention;
fig. 10 is an operation timing diagram of the 3 rd-stage sub ADC according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Fig. 1 is a schematic structural diagram of a pipelined domino architecture successive approximation type analog-to-digital converter according to an embodiment of the present invention. Referring to fig. 1, the present invention provides a pipelined domino successive approximation type analog-to-digital converter 100, comprising: the n + 1-stage sub-ADC 10, the plurality of residual difference amplifiers 20 and the preset adjusting module 30; wherein,
the sub-ADC 10 comprises an input and an output, the input of the 1 st-stage sub-ADC 10 is connected to the signal input for obtaining an input signal after sampling; the output end of the sub-ADC 10 includes a first output end, and the first output end is connected to the preset adjustment module 30, and is used for inputting the 5-bit quantization code generated by the sub-ADC 10 to the preset adjustment module 30, so that the preset adjustment module 30 performs splicing and redundant bit correction on the 5-bit quantization code generated by each sub-ADC 10 to obtain an analog-to-digital conversion result;
the 1 st to nth stage sub-ADCs 10 further include a second output terminal, the second output terminal is connected to the next stage sub-ADC 10 through the residual amplifier 20, and is configured to use a signal, which is obtained by amplifying the residual signal generated by the sub-ADC 10 through the residual amplifier 20, as an input signal, and input the input signal to the next stage sub-ADC 10.
Fig. 2 is a schematic structural diagram of a1 st-stage sub-ADC according to an embodiment of the present invention, fig. 3 is a schematic structural diagram of 2 nd to n th-stage sub-ADCs according to an embodiment of the present invention, and fig. 4 is a schematic structural diagram of an n +1 th-stage sub-ADC according to an embodiment of the present invention. Referring to fig. 2-4, optionally, the pipeline domino successive approximation type analog-to-digital converter 100 further includes a first reference voltage signal terminal VREF, a second reference voltage signal terminal VCM, and a third reference voltage signal terminal GND, wherein the signal input terminals include a first signal input terminal VINAnd a second signal input terminal VIP；
The sub ADC10 includes: a first module 101, a second module 102, a calibration circuit 103 and an output module 104, the first module 101 comprising a comparator: a 1-a 5, a first type capacitor, a second type capacitor, a first type switch, a second type switch and a preset logic circuit corresponding to a 1-a 5 respectively, wherein the first type switch comprises a plurality of first switch groups SW1, the second type switch comprises a plurality of second switch groups SW2, each first switch group SW1 comprises three first switches, and each second switch group SW2 comprises three second switches; wherein,
a first input terminal and a first signal input terminal V of each comparatorINConnected to a second input terminal and a second signal input terminal VIPThe connection and output ends are connected with the corresponding preset logic circuit; the first ends of the first-class capacitors are connected with the first signal input end VINThe connection and the second end are respectively connected to a first reference voltage signal end VREF, a second reference voltage signal end VCM or a third reference voltage signal end GND through three first switches in the first switch group SW 1;
the first ends of the second type capacitors are connected with a second signal input end VIPThe connection and the second terminal are respectively connected to the first reference voltage signal terminal VREF, the second reference voltage signal terminal VCM or the third reference voltage signal terminal GND through three second switches in the second switch group SW 2.
It should be noted that in this embodiment, the structures of the sub-ADCs 10 in the 2 nd to n th-stage sub-ADCs 10 are the same, and the structure of the 1 st-stage sub-ADC 10 is different from the structure of the 2 nd to n th-stage sub-ADCs 10, specifically, the 1 st-stage sub-ADC 10 further includes the second module 102 in addition to the first module 101.
Optionally, as shown in fig. 2, the 1 st-stage sub-ADC 10 further includes a second module 102, the second module 102 includes a third type of capacitor, a fourth type of capacitor, a third type of switch including a plurality of third switch groups SW3, and a fourth type of switch including a plurality of fourth switch groups SW4, each third switch group SW3 includes three third switches, and each fourth switch group SW4 includes three fourth switches; wherein,
the first ends of the third type capacitors are connected with the first signal input end VINThe connection and the second end are respectively connected to the first reference voltage signal end VREF, the second reference voltage signal end VCM or the third reference voltage signal end GND through three third switches in the third switch group SW 3;
the first ends of the fourth type capacitors are connected with the second signal input end VIPThe connection and the second terminal are respectively connected to the first reference voltage signal terminal VREF, the second reference voltage signal terminal VCM or VCM through three fourth switches of the fourth switch set SW4The third reference voltage signal terminal GND.
Optionally, as shown in fig. 2 to 4, the sub-ADC 10 further includes a calibration circuit 103 and an output module 104, wherein the calibration circuit 103 is configured to calibrate the offset voltages of a1 to a5, and the output module 104 is configured to store the 5-bit quantization code generated by the sub-ADC 10.
Fig. 5 is a schematic structural diagram of a comparator according to an embodiment of the present invention. As shown in fig. 5, the pipelined domino successive approximation analog-to-digital converter 100 further includes a power signal terminal VDD; the comparator comprises a first sub-module 201 and a second sub-module 202, the first sub-module 201 comprising a first transistor: M1-M7 and an inverter: b1, B2, the second sub-module 202 includes a second transistor: M8-M14 and an inverter: B1-B4; wherein,
the source of M1 is connected to the power signal terminal VDD, the drain is connected to the source of M2, the gate is connected to the gate of M4, the gate of M2 is connected to the second signal input terminal VIPThe connection and the drain are connected with the drain of the M4, the source of the M4 is grounded, a first node N1 is arranged between the drain of the M1 and the source of the M2, the gate of the M3 is connected with the second reference voltage signal end VCM, the source is connected with the first node N1, the drain is connected with the second node N2, a third node N3 is arranged between the drain of the M4 and the drain of the M2, the source of the M4 is grounded, the gate of the M5 is connected with the clock signal, the drain is connected with the second node N2, and the source is grounded, the gate of the M6 is connected with the first reset signal, the drain is connected with the second node N2, and the source is grounded, the gate of the M7 is connected with the second reset signal, the drain is connected with the second node N2, and the source is grounded; the input end of B1 is connected with the drain of M4, and the output end of B1 is connected with the input end of B2;
the source of M8 is connected to the power signal terminal VDD, the drain is connected to the source of M9, the gate is connected to the gate of M11, the gate of M9 is connected to the second signal input terminal VIPThe connection, the drain and the drain of M11 are connected, the source of M11 is grounded, a fourth node is arranged between the drain of M8 and the source of M9, the gate of M10 is connected with the second reference voltage signal end VCM, the source is connected with the fourth node N4, the drain is connected with the fifth node N5, a sixth node N6 is arranged between the drain of M11 and the drain of M9, the source of M11 is grounded, the gate of M12 is connected with a clock signalThe drain is connected with the fifth node N5, the source is grounded, the grid of the M13 is connected with the first reset signal, the drain is connected with the fifth node N5, the source is grounded, the grid of the M14 is connected with the second reset signal, the drain is connected with the fifth node N5, and the source is grounded; the input end of B3 is connected with the drain of M11, and the output end of B3 is connected with the input end of B4;
the third node N3 is connected to the gate of M8, and the sixth node N6 is connected to the gate of M1.
Alternatively, M1, M2, M3, M8, M9 and M10 are P-type field effect transistors, and M4, M5, M6, M7, M11, M12, M13 and M14 are N-type super effect transistors.
In addition, in this embodiment, the comparators a1 to a5 further include latches as shown in fig. 6, for storing the quantization codes generated after the quantization is completed.
Fig. 7 is a schematic structural diagram of a calibration circuit according to an embodiment of the present invention. As shown in fig. 7, in the pipeline domino successive approximation analog-to-digital converter 100, the calibration circuit 103 includes a third transistor: M15-M25, a preset current source IC, and gate: c1 and C2, and inverter B5; wherein,
the gate of M15 is connected with the gate of M16, the source of M15 and the source of M16 are both connected with a power supply signal end VDD, the drain of M15 is connected with the source of M17, the gate of M17 is connected with the ground, the drain of M19, the source of M19 is connected with the drain of M21, the source of M21 is connected with the ground, the drain of M16 is connected with the source of M18, the gate of M18 is connected with a first switching signal SPS, the drain of M18 is connected with the drain of M20, a seventh node N7 is included between the drain of M18 and the drain of M20, a seventh node N7 is connected with a first reference voltage Vc, the gate of M20 is connected with a second switching signal SNS, the source is connected with the drain of M22, the source of M22 is connected with the ground, the grid is connected with a preset current source IC, an eighth node N8 is arranged between the preset current source IC and the grid of the M22, the grid of the M23 and the grid of the M21 are both connected with an eighth node N8, the drain of the M23 is connected with the preset current source IC, and the source is grounded;
a first input end and a second input end of the comparator are connected through a first switch, a third input end is connected with a first reference voltage Vc, a first output end is connected with a first input end of C1, a second output end is connected with a first input end of C2, a second input end of C1 and a second input end of C2 are connected to an enable signal EN, a gate of M24 is connected with a power signal end VDD, a source of M24 and a source of M25 are connected to a ninth node N9, the ninth node N9 is connected with a second switching signal SNS, a drain of M24 and a drain of M25 are connected to a tenth node N10, the tenth node N10 and an output end of C1 are connected, a gate of M25 is grounded, and an output end of C2 is connected with an input end of an inverter B5.
Optionally, in the 1 st to nth stage sub-ADCs, the first type capacitor includes: cs 1-Cs 5, and the second type of capacitor comprises: the capacitance ratio of Cs 6-Cs 10, Cs1, Cs2, Cs3, Cs4 and Cs5 is 16:8:4:2:1, and the capacitance ratio of Cs6, Cs7, Cs8, Cs9 and Cs10 is 16:8:4:2: 1.
For example, the pipelined domino architecture successive approximation analog-to-digital converter in this embodiment may include a 3-stage 5-bit sub-ADC. With continued reference to fig. 2, for a1 st stage 5-bit sub-ADC where CLKS1 is the first stage sampling clock signal, the sampling frequency may be 1GHz, i.e., the period is 1ns, where 250ps is used for sampling and 750ps is used for conversion, residual amplification and offset calibration within the period of 1 ns. Alternatively, the first reference voltage signal terminal VREF is 0.9mV, the second reference voltage signal terminal VCM is 450mV, and the input signal with Vpp being 1.8V may be quantized. The first module 101 and the second module 102 simultaneously couple to the first signal input terminal VINAnd a second signal input terminal VIPSampling is carried out, the comparator compares the voltages of the first type capacitor and the second type capacitor in the first module 101, and the comparison result is fed back to the preset logic circuit of the first module 101 and the second module 102.
It should be noted that, in the first type of capacitor, the second type of capacitor, the third type of capacitor, and the fourth type of capacitor, each capacitor is weighted by 16:8:4:2:1, and the unit capacitance of the third type capacitance and the fourth type capacitance in the second module 102 is greater than the unit capacitance of the first type capacitance and the second type capacitance in the first module 101, this design can make the small capacitance in the first module 101 realize faster quantization code conversion process, and the large capacitance in the second module 102 can ensure the accuracy of the residual level output after quantization is completed, and simultaneously meet the requirement of KT/C noise. In the conversion period, the residual error amplifier 20 works in a stable state in which the inputs are common mode signals, and after the conversion is completed, the capacitor arrays (i.e., the third type capacitor and the fourth type capacitor) of the second module 102 are connected to the input end of the residual error amplifier 20, so as to form a multiplying digital-to-analog converter MDAC circuit.
Fig. 8 is an operation timing diagram of the 1 st-stage sub-ADC according to the embodiment of the present invention. Referring to fig. 2 and 8, the operation principle of the 1 st-stage sub-ADC will be described with reference to the timing diagram, taking the example that the pipeline domino structure successive approximation type analog-to-digital converter includes the 3-stage 5-bit SAR sub-ADC as an example.
The stage 1 clock signal CLKS1 is sampled high, held low, CLKS1 is delayed to generate the clock signal CLKC5, CLKC5 of A1, and the first comparison is triggered by the high-low transition of CLKS 5.
The comparison result of the highest comparator A1 passes through a preset logic circuit to generate CLKC4, then the same process sequentially generates clock signals CLKC3, CLKC2 and CLKC1 of comparators A2, A3, A4 and A5, and the output of the last comparator A5 passes through a preset logic circuit to generate a control signal CLKC 0. The 5 comparators continuously perform binary search algorithm on the upper plate levels of the first type of capacitor and the second type of capacitor in the first module 101 at a higher speed, meanwhile, the comparison results of A1-A5 are also fed back to a preset logic circuit of the second module 102, the second module 102 generates the same successive approximation process along with the first module 101, and only the time for the third type of capacitor and the fourth type of capacitor to overturn to a stable level is longer, and the process is also a process for making difference between an analog input signal in the MDAC and the DAC in the pipeline. The control signal CLKC0 is inverted to generate the latch control signal CLK _ LOCK1, the comparison result is stored in the latch structure, no change occurs in the period, and the conversion period is finished.
The calibration RESET signal RESET _1 comes with a high level, the switch SV1 is turned on, and the first type of capacitor and the second type of capacitor in the first module 101 are shorted together, which generates the same level of the positive and negative input terminals of the comparator for the calibration process.
In the previous conversion process, the positive and negative input terminals of the residual error amplifier 20 are both connected to the common mode level, so as to ensure that the residual error amplifier 20 rapidly enters a stable dc bias state in the residual error amplification process. The common mode level control signal CLK _ VCM1 goes from high to low indicating the beginning of the residual amplification phase.
The multiplying dac control signal CLK _ MDAC1 arrives at approximately the same time as the high level of CLKs1 of the second stage, and the capacitor arrays (i.e., the third type of capacitors and the fourth type of capacitors) in the second block 102 are coupled to the input of the residual amplifier 20 to form the multiplying dac MDAC block in the pipeline ADC. The first type capacitor and the second type capacitor of the second stage 5bit SAR ADC10 are connected to the output end of the residual error amplifier 20 to become the load of the operational amplifier. The operational amplifier amplifies the difference signal of the analog input and the DAC on the capacitor plate by approximately 16 times through negative feedback and outputs the amplified difference signal to the capacitor array of the first-class capacitor and the second-class capacitor of the second stage. After the residual amplified signal is established, the second stage CLKS2 toggles the switch off prior to CLK _ MDAC1 in order to ensure that the residual amplified signal of the second stage sampling is not disturbed. To ensure that the input signal is in a dc biased state that affects the operational amplifier, CLK _ MDAC1 is turned off prior to the rising edge of the second stage CLKs 2.
During the process that the second module 102 participates in amplification, the upper plates of the first type capacitor and the second type capacitor in the first module 101 are short-circuited to the same level, then the comparator calibration RESET signal RESET _ c1 becomes low level, the calibration enable signal EN1 is triggered to be generated, during the short pulse time when EN1 is high level, two AND gates in the calibration logic do not shield CN1-5/CP1-5 signals any more, and the VC voltage is adjusted to compensate the offset voltage. (the pulse width of EN1 determines the charge-discharge time)
The quantized code D15-11 is output by the output control clock signal CLK _ D1.
The high level of CLKS1 comes to quickly trigger the EN1 signal to go low, masking the comparator output signal. The high level of CLKS1 quickly resets all comparators, leaving the capacitor array bottom plates of first block 101 and second block 102 connected to VCM, starting a new sampling cycle.
Further, when the pipeline domino successive approximation analog-to-digital converter includes 3 stages of 5-bit sub-ADCs, please continue to refer to fig. 3, for the 2 nd stage sub-ADC, CLKS2 is the first stage sampling clock signal, the frequency may be 1GHz, i.e. the period is 1ns, and similarly, within one period, 250ps is used for sampling, 750ps is used for conversion, residual amplification and offset calibration. VREF is 0.9mV, VCM is 450mV, Vpp is 1.8V input signal can be quantized, CLKS2 samples the residual amplified signal VOUTP2/VOUTN2 of the first stage high. The capacitance design of the second stage 5bit SAR needs to consider the load capacity, the conversion speed and the precision degree of the generated residual error of the residual error amplifier 20. In the first type of capacitor and the second type of capacitor, the ratio of the capacitors is 16:8:4:2: 1.
Fig. 9 is an operation timing diagram of the 2 nd-stage sub-ADC according to the embodiment of the present invention. Please refer to fig. 3 and fig. 9, further describe the working process of the 2 nd stage 5bit SAR sub-ADC:
CLKS2 sample high and hold low, and CLKS2 is also the highest comparator clock CLKC5 triggered by the high-going low for the first comparison.
The comparison result of the highest comparator A1 passes through a preset logic circuit to generate CLKC4, and then the same process sequentially generates clock signals CLKC3, CLKC2 and CLKC1 of comparators A2, A3, A4 and A5. The output of the last comparator a5 is passed through preset logic to generate the control signal CLKC 0. The comparators A1-A5 output 5-bit quantization codes in sequence, the quantization codes control the switching of a capacitor lower plate switch through a logic circuit to generate a successive approximation process, and the process is also a process of making a difference between an analog input signal in the multiplying digital-to-analog converter MDAC and the DAC in a production line. The CLKC0 is inverted to generate the second stage latch control signal CLK _ LOCK2, the comparison result is stored in the latch structure and no longer changed during this period, and the conversion period ends.
In the former conversion process, the positive and negative input ends of the operational amplifier are connected to the common mode level. And the operational amplifier is ensured to rapidly enter a stable direct current bias state in the residual error amplification process. The common mode control signal CLK _ VCM1 changes from high to low marking the beginning of the residual amplification stage
The multiplying digital-to-analog converter control signal CLK _ MDAC2 arrives at approximately the same time as the high level of the third stage clock signal CLKS3, and the second stage capacitor array is connected to the input of the operational amplifier to form an MDAC module in the pipeline ADC. And the capacitor array of the second-stage 5-bit SAR ADC is connected to the output end of the operational amplifier to become a load of the operational amplifier. The operational amplifier amplifies the difference signal of the analog input and the DAC on the capacitor plate by approximately 16 times through negative feedback and outputs the amplified difference signal to the capacitor array of the third stage. After the residual amplifying signal is established, in order to ensure that the residual amplifying signal of the third stage is not disturbed, the CLKS3 triggers the switch to turn off before the CLK _ MDAC2 triggers the switch. The residual amplification period ends.
Switch SV2 turns on after the falling edge of third stage clock signal CLKS3, the differential inputs of the second stage capacitor plates are shorted together, and the circuit enters a calibration cycle.
When the voltages of the capacitor plates are the same, the comparator calibration RESET signal RESET _ c2 triggers 5 comparators in the second stage to RESET quickly, and after the resetting is completed, a comparison result under the action of the offset voltage is output.
In the high level window of the calibration enable signal EN2, the output result of the comparator controls the current source to charge or discharge, thereby compensating the offset voltage.
The quantized code D10-6 is output by the output control clock signal CLK _ D2.
CLKS3 is a third stage sampling clock signal with a frequency of 1GHz and a period of 1ns, where about 250ps is used for sampling, the remaining 750ps is used for conversion, residual amplification, and offset calibration. VREF is 0.9mV, VCM is 450mV, Vpp is 1.8V input signal can be quantized, CLKS3 high samples the second stage residual amplified signal VOUTP2/VOUTN 2. Because the third-stage 5-bit SAR sub-ADC does not need to transfer residual difference, the capacitance value ratio of each capacitor in the first-class capacitor and the second-class capacitor is 8, 4, 2 and 1.
Fig. 10 is an operation timing diagram of the 3 rd-stage sub ADC according to the embodiment of the present invention. Referring to fig. 4 and 10, after the CLKS3 sampling is completed, the CLKC4, CLKC3, CLK2, and CLK1 respectively generate output comparison results.
The low level of the third stage latch control signal CLK _ LOCK3 arrives, the comparison result is latched, and the conversion cycle ends.
The third stage comparator calibration RESET signal RESET _ c3 high triggers a comparator RESET. The switch SV3 is conducted to trigger the upper plate of the differential capacitor to be short-circuited. RESET _ c3 is the comparison result of the output offset of low level.
And in a high-level pulse window of the third-stage calibration enable signal EN3, the comparison result controls the charging and discharging of the capacitor on the comparator, and the calibration is completed.
The quantized code D5-1 is output by the output control clock signal CLK _ D3.
The beneficial effects of the invention are that:
the invention provides a sequential approximation type analog-to-digital converter with a flow line domino structure, which comprises: the device comprises an n + 1-stage sub ADC, a plurality of residual error amplifiers and a preset adjusting module; the sub-ADC comprises an input end and an output end, wherein the input end of the 1 st-stage sub-ADC is connected with the signal input end and is used for obtaining an input signal after sampling; the output end of each sub-ADC comprises a first output end, and the first output end is connected with the preset adjusting module and used for inputting the 5-bit quantization codes generated by the sub-ADCs into the preset adjusting module so that the adjusting module can splice and correct redundant bits of the 5-bit quantization codes generated by each sub-ADC to obtain an analog-to-digital conversion result; the 1 st-nth stage sub-ADCs further comprise second output ends, the second output ends are connected to the next stage sub-ADCs through residual difference amplifiers, and signals generated by residual difference signals generated by the sub-ADCs and amplified by the residual difference amplifiers are used as input signals and input to the next stage sub-ADCs. The invention adopts a multi-stage sub-ADC structure, improves the conversion speed and the precision of the SAR ADC, and can correct offset voltage in real time in the working process of the comparator because each sub-ADC comprises a calibration circuit, thereby preventing the performance of the sub-ADC from being reduced due to offset accumulation of the comparator.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A pipelined domino architecture successive approximation analog-to-digital converter, comprising: the device comprises an n + 1-stage sub ADC, a plurality of residual error amplifiers and a preset adjusting module; wherein,
the sub-ADC comprises an input end and an output end, wherein the input end of the 1 st-stage sub-ADC is connected with the signal input end and is used for obtaining an input signal after sampling; the output end of the sub-ADC comprises a first output end, and the first output end is connected with the preset adjusting module and used for inputting the 5-bit quantization codes generated by the sub-ADC into the preset adjusting module, so that the preset adjusting module can splice and correct redundant bits of the 5-bit quantization codes generated by each sub-ADC to obtain an analog-to-digital conversion result;
the 1 st-nth-stage sub ADC also comprises a second output end, the second output end is connected to the next-stage sub ADC through the residual error amplifier, and the second output end is used for taking a signal generated by the sub ADC and amplified by the residual error amplifier as an input signal and inputting the input signal to the next-stage sub ADC.
2. The pipelined domino structure successive approximation analog-to-digital converter of claim 1, further comprising a first reference voltage signal terminal, a second reference voltage signal terminal, and a third reference voltage signal terminal, wherein the signal input terminals comprise a first signal input terminal and a second signal input terminal;
the sub-ADC includes: the circuit comprises a first module, a second module, a calibration circuit and an output module, wherein the first module comprises a comparator: the circuit comprises preset logic circuits corresponding to A1-A5, a first type capacitor, a second type capacitor, a first type switch, a second type switch and A1-A5 respectively, wherein the first type switch comprises a plurality of first switch groups, the second type switch comprises a plurality of second switch groups, each first switch group comprises three first switches, and each second switch group comprises three second switches; wherein,
the first input end of each comparator is connected with the first signal input end, the second input end of each comparator is connected with the second signal input end, and the output end of each comparator is connected with a corresponding preset logic circuit; the first ends of the first-class capacitors are connected with the first signal input end, and the second ends of the first-class capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three first switches in the first switch group respectively;
and the first ends of the second type capacitors are connected with the second signal input end, and the second ends of the second type capacitors are respectively connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three second switches in the second switch group.
3. The pipelined domino structure successive approximation type analog-to-digital converter of claim 2, wherein in the 1-nth stage sub-ADCs, the first type of capacitors comprise: cs 1-Cs 5, the second type of capacitor comprising: the capacitance ratio of Cs 6-Cs 10, Cs1, Cs2, Cs3, Cs4 and Cs5 is 16:8:4:2:1, and the capacitance ratio of Cs6, Cs7, Cs8, Cs9 and Cs10 is 16:8:4:2: 1.
4. The pipelined domino architecture successive approximation analog-to-digital converter of claim 2, wherein said 1 st stage sub-ADC further comprises a second module comprising a third type of capacitance, a fourth type of capacitance, a third type of switch, and a fourth type of switch, said third type of switch comprising a plurality of third switch sets, said fourth type of switch comprising a plurality of fourth switch sets, each of said third switch sets comprising three third switches, each of said fourth switch sets comprising three fourth switches; wherein,
the first ends of the third capacitors are connected with the first signal input end, and the second ends of the third capacitors are connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three third switches in the third switch group respectively;
the first ends of the fourth capacitors are all connected with the second signal input end, and the second ends of the fourth capacitors are respectively connected to the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end through three fourth switches in the fourth switch group.
5. The pipelined domino architecture successive approximation analog-to-digital converter of claim 4, wherein in a1 st stage sub-ADC, the third type of capacitance comprises: cs 11-Cs 15, the second type of capacitor comprising: the capacitance ratio of Cs 16-Cs 20, Cs11, Cs12, Cs13, Cs14 and Cs15 is 16:8:4:2:1, and the capacitance ratio of Cs16, Cs17, Cs18, Cs19 and Cs20 is 16:8:4:2: 1.
6. The pipelined domino architecture successive approximation analog-to-digital converter of claim 4, wherein the sub-ADC further comprises a calibration circuit for calibrating the offset voltages of A1-A5 and an output module for storing the 5-bit quantization code generated by the sub-ADC.
7. The pipelined domino structure successive approximation analog-to-digital converter of claim 1, further comprising a power supply signal terminal; the comparator includes a first sub-module and a second sub-module, the first sub-module including a first transistor: M1-M7 and an inverter: b1, B2, the second submodule comprising a second transistor: M8-M14 and an inverter: B1-B4; wherein,
a source of M1 is connected with the power signal end, a drain of M2 is connected with the source of M2, and a gate of M4, a gate of M2 is connected with the second signal input end, a drain of M4 is connected with the drain of M4, a source of M8538 is grounded, a first node is included between the drain of M1 and the source of M2, a gate of M3 is connected with the second reference voltage signal end, a source of M3 is connected with the first node, and a drain of M4 is connected with the second node, a third node is included between the drain of M2, a source of M4 is grounded, a gate of M5 is connected with a clock signal, a drain of M6 is connected with the first reset signal, a drain of M6 is connected with the second node, and a source of M7 is connected with the second reset signal, a drain of M7 is connected with the second node, and a source of M4 is grounded; the input end of B1 is connected with the drain of M4, and the output end of B1 is connected with the input end of B2;
a source of the M8 is connected with the power signal end, a drain of the M8 is connected with a source of the M9, and a gate of the M12 is connected with a gate of the M11, a gate of the M9 is connected with the second signal input end, a drain of the M9 is connected with a drain of the M11, a source of the M11 is grounded, a fourth node is arranged between the drain of the M8 and the source of the M9, a gate of the M10 is connected with the second reference voltage signal end, a source of the M10 is connected with the fourth node, and a drain of the M11 is connected with the fifth node, a sixth node is arranged between the drain of the M11 and the drain of the M9, a source of the M11 is grounded, a gate of the M12 is connected with a clock signal, a drain of the M3556 is connected with the fifth node, and a source of the M13 is grounded, a gate of the M14 is connected with the second reset signal, a drain of the M3583 is connected with the fifth node, and a drain of the M3583 is connected with the fifth node; the input end of B3 is connected with the drain of M11, and the output end of B3 is connected with the input end of B4;
the third node is connected with the gate of M8, and the sixth node is connected with the gate of M1.
8. The pipelined domino structure successive approximation type analog-to-digital converter of claim 7, wherein M1, M2, M3, M8, M9 and M10 are P-type field effect transistors, and M4, M5, M6, M7, M11, M12, M13 and M14 are N-type super effect transistors.
9. The pipelined domino architecture successive approximation analog-to-digital converter of claim 8, wherein said calibration circuit comprises a third transistor: M15-M25, a preset current source, and gate: c1 and C2, and inverter B5; wherein,
the gate of M15 is connected with the gate of M16, the source of M15 and the source of M16 are both connected with the power signal end, the drain of M15 is connected with the source of M17, the gate of M17 is grounded, the drain of M19 is connected, the source of M19 is connected with the drain of M21, the source of M21 is grounded, the drain of M16 is connected with the source of M18, the gate of M18 is connected with the first switch signal, the drain of M18 is connected with the drain of M20, a seventh node is arranged between the drain of M18 and the drain of M20, the seventh node is connected to the first reference voltage, the gate of M20 is connected to the second switching signal, the source is connected to the drain of M22, the source of M22 is grounded, the gate is connected to the predetermined current source, an eighth node is arranged between the preset current source and the gate of the M22, the gate of the M23 and the gate of the M21 are both connected with the eighth node, the drain of the M23 is connected with the preset current source, and the source of the M23 is grounded;
the first input end and the second input end of the comparator are connected through a first switch, the third input end is connected with the first reference voltage, the first output end is connected with the first input end of C1, the second output end is connected with the first input end of C2, the second input end of C1 and the second input end of C2 are both connected to enable signals, the grid of M24 is connected with the power signal end, the source of M24 and the source of M25 are connected to a ninth node, the ninth node is connected with the second switch signal, the drain of M24 and the drain of M25 are connected to a tenth node, the tenth node is connected with the output end of C1, the grid of M25 is grounded, and the output end of C2 is connected with the input end of an inverter B5.
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