CN113851565A - Patterned substrate, preparation method thereof and LED with patterned substrate - Google Patents
Patterned substrate, preparation method thereof and LED with patterned substrate Download PDFInfo
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- CN113851565A CN113851565A CN202111295833.1A CN202111295833A CN113851565A CN 113851565 A CN113851565 A CN 113851565A CN 202111295833 A CN202111295833 A CN 202111295833A CN 113851565 A CN113851565 A CN 113851565A
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- 239000000758 substrate Substances 0.000 title claims abstract description 77
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 19
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 5
- 238000000605 extraction Methods 0.000 abstract description 10
- 239000013078 crystal Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000149 argon plasma sintering Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a patterned substrate, a preparation method thereof and an LED with the patterned substrate. The preparation method comprises the step S1: providing a substrate; step S2: carrying out first etching on the substrate to obtain a first patterned substrate with a bulge of a first pattern; step S3: and performing second etching on the pedestal gap between the adjacent figures on the C surface between the first patterns of the first patterned substrate to obtain pits with second patterns, and forming a second patterned substrate with the first patterns and the second patterns. The reverse-patterned pits etched twice can prolong the growth time of the epitaxial layer on the C surface (the base gap between adjacent patterns), the stress is released, and the side walls of the reverse-patterned pits are non-polar surfaces, so that the dislocation density is reduced, and the lattice quality of the epitaxial layer grown on the reverse-patterned pits is improved; and moreover, light reflection can be increased, and the light extraction rate is improved, so that the external quantum efficiency is improved.
Description
Technical Field
The invention relates to a patterned substrate, a preparation method thereof and an LED with the patterned substrate, in particular to a patterned substrate with low growth dislocation density and high light extraction rate, a preparation method thereof and an LED with the patterned substrate.
Background
The patterned substrate is a substrate with a patterned surface formed on a planar substrate by using processes of a photomask, etching and the like, and on one hand, the patterned substrate can effectively reduce the dislocation density of an epitaxial structure layer, improve the crystal quality of an epitaxial material and further improve the internal quantum light emitting efficiency of the light emitting diode; on the other hand, the light scattering increased by the patterned structure improves the external quantum efficiency.
In the existing graphical substrate, as shown in fig. 1, a protrusion array 2 is grown on a substrate 1', and as shown by a dotted line frame a, the quality of an epitaxial layer lattice grown on a C surface (a pedestal gap between adjacent graphs) is poor; secondly, in order to obtain a good light extraction effect, a pattern with a large base and a large height is expected to be obtained, the C surface of the patterned substrate with the large base pattern is too small, the quality of the crystal lattice of the epitaxial layer grown on the patterned substrate with the large base pattern is further deteriorated, the scattering of light by the patterned substrate with the large base pattern is reduced, and the external quantum efficiency is reduced.
That is, in the current patterned substrate, there are two problems as follows:
1. in the existing patterned substrate, the quality of an epitaxial layer lattice grown on a C surface (a pedestal gap between adjacent patterns) is poor;
2. the quality of crystal lattices of an epitaxial layer grown on a C surface (a pedestal gap between adjacent patterns) of the patterned substrate with the large pedestal pattern is further deteriorated, the distance between the patterned substrates with the large pedestal pattern is reduced, the scattering of light is reduced, the light-emitting rate is low, and the external quantum efficiency is reduced.
Disclosure of Invention
The invention aims to solve the problems of poor crystal lattice quality and low light extraction efficiency of epitaxial layer growth.
To achieve one of the above objects, the present invention provides a patterned substrate.
The patterned substrate includes:
an array of bumps; and
an array of pits;
wherein the pit array is obtained by etching a base gap between adjacent patterns on the C surface of the bulge array.
As an optional technical solution, each surface of any one of the convex non-C-surfaces in the convex array is seamlessly and smoothly connected with each pit corresponding to the pit array.
As an optional technical solution, the protrusion arrays are arranged periodically and are pattern patterns with the same size.
As an optional technical solution, the pit pattern of the pit array is a hole pattern having an inverted triangular pyramid shape, an inverted pointed cone shape, an inverted polyhedral cone shape, or an inverted yurt shape.
As an optional technical solution, the pit pattern size, height and pitch of the pit array are the same.
As an optional technical scheme, the height of the pit array is not more than 2 μm.
The invention also provides a preparation method of the patterned substrate, which comprises the steps of
Step S1: providing a substrate;
step S2: carrying out first etching on the substrate to obtain a first patterned substrate with a bulge of a first pattern;
step S3: and performing second etching on the pedestal gap between the adjacent figures on the C surface between the first patterns of the first patterned substrate to obtain pits with second patterns, and forming a second patterned substrate with the first patterns and the second patterns.
Alternatively, in step S3, the depth of the pits in the second pattern is not greater than 2 μm.
As an optional technical solution, in the step S3, each surface of any one of the convex non-C-shaped surfaces in the convex array is seamlessly and smoothly connected with each concave pit corresponding to the concave pit array.
The invention also provides an LED which comprises the patterned substrate.
Compared with the prior art, the pit array is etched in the base gap between the adjacent patterns on the C surface of the raised array of the patterned substrate, the inverted patterned pits subjected to secondary etching can prolong the growth time of the epitaxial layer on the C surface (the base gap between the adjacent patterns), the thickness of the generated GaN layer is thick, the stress is released, the crystal lattice quality of the epitaxial layer grown on the inverted patterned pits is improved, the side wall of the inverted patterned pits is a non-polar surface, the dislocation generation can be reduced, the dislocation density is reduced, the crystal lattice quality of the epitaxial layer grown on the inverted patterned pits is improved, and particularly the crystal lattice quality of the SiO2 plated substrate is obviously improved; and the reverse-patterned pits of the secondary etching can increase light reflection and improve light extraction rate, so that the external quantum efficiency is improved, and the design of the reverse-patterned pits can also improve the lattice quality for the pattern substrate with large bottom width and high depth (the large bottom width and the high depth have better light extraction effect and light scattering is reduced).
Drawings
FIG. 1 is a schematic view of a prior art patterned substrate;
FIG. 2 is a schematic view of a patterned substrate of the present invention;
FIG. 3 is a schematic optical comparison of the patterned substrate of FIG. 2;
fig. 4 is a flow chart of the preparation of the patterned substrate of fig. 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to the detailed description of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
For convenience in explanation, the description herein uses terms indicating relative spatial positions, such as "upper," "lower," "rear," "front," and the like, to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
FIG. 2 is a schematic view of a patterned substrate according to the present invention, referring to FIG. 2. The patterned substrate 1 comprises a protrusion array 2 and a pit array 3, wherein the pit array 3 is obtained by etching a base gap between adjacent patterns on the C surfaces of the protrusion array 2, namely, each pit of the pit array 3 is positioned between the C surfaces of two protrusions of the protrusion array 2, and the pits and the protrusions are formed in a staggered mode. The patterned substrate 1 is, for example, an alumina substrate, and the bump array 2 is, for example, SiO2/Al2O3 bumps.
Thus, as shown in fig. 2, the C-plane at the dashed line box B is small, and the sidewall is non-polar, the reverse patterned pits of the secondary etching can increase the growth time of the epitaxial layer on the C-plane (the pedestal gap between adjacent patterns), the thickness of the generated GaN layer is thick, the stress is released, and the lattice quality of the epitaxial layer grown thereon is increased, and the sidewalls of the reverse patterned pits are non-polar surfaces, which can reduce the generation of dislocations, reduce the dislocation density, and improve the lattice quality of the epitaxial layer grown thereon, and especially for SiO 2-plated substrates, the lattice quality is improved significantly.
And, as shown in the optical path comparison diagram of fig. 3, the dotted line arrow represents the optical path proceeding diagram of the patterned substrate 1 of the present invention, the solid line arrow represents the optical path proceeding diagram of the substrate 1' in the prior art, and the solid line arrow reflects via the non-polar surface of the sidewall of the pit array 3, most of the light is reflected into the air via the N-GaN layer 4 → MQW layer 5 → P-GaN layer 6, while since photons escape into the air at an escape angle of 23 ° in GaN, in the prior art, many light is reflected via the C-surface of the substrate and then only propagates between the N-GaN layers, and cannot be reflected into the air. Namely, because the light escape angle in GaN is 23 degrees, the light reflection can be increased and the light extraction rate can be improved by the reverse-patterned pits (as shown in FIG. 3) of the secondary etching, thereby improving the external quantum efficiency, and the lattice quality can also be improved by the reverse-patterned pits for the pattern substrate with large bottom width and high depth (the substrate with large bottom width and high depth has a better light extraction effect and reduces light scattering).
In this embodiment, each surface of any one of the convex non-C-surfaces in the convex array 2 and each corresponding pit of the pit array 3 are seamlessly and smoothly connected, that is, a smooth curved surface is formed between the two, and no abrupt change in curvature is formed.
The raised arrays are periodically arranged and are pattern graphs with the same size, so that the etching control is convenient; the pit patterns of the pit array have the same size, height and pitch.
The pit pattern of the pit array 3 is a hole pattern having an inverted triangular pyramid shape, an inverted pointed pyramid shape, an inverted polyhedral pyramid shape, or an inverted mongolian yurt shape, and the height of the pit array 3 is not more than 2 μm.
As shown in fig. 4, the method for preparing the patterned substrate includes:
step S1: providing a substrate;
step S2: carrying out first etching on the substrate to obtain a first patterned substrate with a bulge of a first pattern;
step S3: and performing second etching on the pedestal gap between the adjacent figures on the C surface between the first patterns of the first patterned substrate to obtain pits with second patterns, and forming a second patterned substrate with the first patterns and the second patterns.
In step S3, the pits of the second pattern have a depth of not more than 2 μm.
In step S3, each surface of any one of the convex non-C-surfaces in the convex array is seamlessly and smoothly connected with each of the concave pits corresponding to the concave pit array.
The invention also provides an LED which comprises the patterned substrate.
In conclusion, the pit array is etched in the pedestal gap between the adjacent patterns on the C surface of the convex array of the patterned substrate, the inverted patterned pits subjected to secondary etching can prolong the growth time of the epitaxial layer on the C surface (the pedestal gap between the adjacent patterns), the thickness of the generated GaN layer is thick, the stress is released, the lattice quality of the epitaxial layer grown on the inverted patterned pits is improved, the side walls of the inverted patterned pits are nonpolar surfaces, the dislocation generation can be reduced, the dislocation density is reduced, the lattice quality of the epitaxial layer grown on the inverted patterned pits is improved, and particularly the lattice quality of the SiO2 plated substrate is obviously improved; and the reverse-patterned pits of the secondary etching can increase light reflection and improve light extraction rate, so that the external quantum efficiency is improved, and the design of the reverse-patterned pits can also improve the lattice quality for the pattern substrate with large bottom width and high depth (the large bottom width and the high depth have better light extraction effect and light scattering is reduced).
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A patterned substrate, comprising:
an array of bumps; and
an array of pits;
wherein the pit array is obtained by etching a base gap between adjacent patterns on the C surface of the bulge array.
2. The patterned substrate of claim 1, wherein each surface of any one of the array of protrusions other than the C-face seamlessly and smoothly interfaces with a respective one of the array of dimples.
3. The patterned substrate of claim 1, wherein the array of protrusions is arranged periodically and in a pattern of the same size.
4. The patterned substrate of claim 1, wherein the pit pattern of the pit array is a hole pattern having an inverted triangular pyramid shape, an inverted pyramidal cone shape, an inverted polyhedral cone shape, or an inverted yurt shape.
5. The patterned substrate of claim 1, wherein the pit pattern of the pit array is the same size, height, and pitch.
6. The patterned substrate of claim 1, wherein the array of pits is no greater than 2 μ ι η in height.
7. A method for preparing a patterned substrate comprises
Step S1: providing a substrate;
step S2: carrying out first etching on the substrate to obtain a first patterned substrate with a bulge of a first pattern;
step S3: and performing second etching on the pedestal gap between the adjacent figures on the C surface between the first patterns of the first patterned substrate to obtain pits with second patterns, and forming a second patterned substrate with the first patterns and the second patterns.
8. The method of claim 7, wherein in the step S3, the pits of the second pattern have a depth of not more than 2 μm.
9. The method according to claim 7, wherein in step S3, each surface of any one of the non-C-shaped protrusions in the protrusion array is seamlessly and smoothly connected with each corresponding pit in the pit array.
10. An LED comprising the patterned substrate of any of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111295833.1A CN113851565A (en) | 2021-11-03 | 2021-11-03 | Patterned substrate, preparation method thereof and LED with patterned substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111295833.1A CN113851565A (en) | 2021-11-03 | 2021-11-03 | Patterned substrate, preparation method thereof and LED with patterned substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113851565A true CN113851565A (en) | 2021-12-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111295833.1A Pending CN113851565A (en) | 2021-11-03 | 2021-11-03 | Patterned substrate, preparation method thereof and LED with patterned substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113851565A (en) |
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2021
- 2021-11-03 CN CN202111295833.1A patent/CN113851565A/en active Pending
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