CN113851173A

CN113851173A - Shift register unit, drive control circuit, display device and drive method

Info

Publication number: CN113851173A
Application number: CN202111120788.6A
Authority: CN
Inventors: 魏立恒; 杨慧娟; 王予; 李灵通; 舒晓青; 廖茂颖; 刘松; 陈天赐
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-09-24
Filing date: 2021-09-24
Publication date: 2021-12-28

Abstract

The present disclosure discloses a shift register unit, a driving control circuit, a display device and a driving method, wherein signals of a first node and a second node are controlled by the control circuit. The first transistor controls the connection and disconnection between the first node and the third node. And the second transistor is used for controlling the connection and disconnection between the control signal end and the first capacitor. And controlling the signal output end to output a signal through the output circuit. Through the mutual cooperation of the components, the stability of the signal output by the signal output end can be improved.

Description

Shift register unit, drive control circuit, display device and drive method

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving control circuit, a display device, and a driving method.

Background

With the rapid development of display technology, display devices are increasingly developed toward high integration and low cost. In the GOA (Gate Driver on Array) technology, a TFT (Thin Film Transistor) driving control circuit is integrated on an Array substrate of a display device to drive the display device. The drive control circuit is generally composed of a plurality of cascaded shift register units. However, the output of the shift register unit is unstable, which may cause display abnormality.

Disclosure of Invention

The shift register unit provided by the embodiment of the disclosure includes:

a control circuit configured to control signals of the first node and the second node according to a signal of an input signal terminal, a signal of a clock signal terminal, and a signal of a reference signal terminal;

a first transistor, a gate of which is electrically connected to the second node, a first pole of which is electrically connected to the first node, and a second pole of which is electrically connected to a third node;

a gate of the second transistor is electrically connected to the third node, and a first electrode of the second transistor is electrically connected to a control signal terminal;

a first electrode plate of the first capacitor is electrically connected with the second pole of the second transistor, and a second electrode plate of the first capacitor is electrically connected with a third node;

an output circuit configured to control a signal output terminal to output a signal in response to the signal of the third node and the signal of the second node.

In some examples, the clock signal terminals include a first clock signal terminal and a second clock signal terminal;

the reference signal terminal comprises a first reference signal terminal and a second reference signal terminal;

the control circuit includes:

an input circuit configured to supply a signal of the input signal terminal to the first node under control of a signal of the first clock signal terminal and to supply a signal of the first reference signal terminal to the fourth node under control of a signal of the first clock signal terminal;

a node control circuit configured to supply a signal of the first clock signal terminal to the fourth node under control of a signal of the first node; providing a signal of the second reference signal terminal to the first node under control of the signals of the fourth node and the second clock signal terminal; providing a signal of the second clock signal terminal to the fifth node under the control of a signal of the fourth node; conducting the fifth node and the second node under the control of a signal of the second clock signal terminal;

a noise reduction circuit configured to adjust a signal of the second node according to a signal of the second reference signal terminal.

In some examples, the noise reduction circuit includes: a third transistor;

a gate of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the second reference signal terminal, and a second electrode of the third transistor is electrically connected to the second node.

In some examples, the noise reduction circuit includes: a fourth transistor and a fifth transistor;

a gate of the fourth transistor is electrically connected to the third node, a first electrode of the fourth transistor is electrically connected to the second reference signal terminal, and a second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

a gate of the fifth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node.

In some examples, the input circuit includes: a sixth transistor and a seventh transistor;

a gate of the sixth transistor is electrically connected to the first clock signal terminal, a first electrode of the sixth transistor is electrically connected to the input signal terminal, and a second electrode of the sixth transistor is electrically connected to the first node;

a gate of the seventh transistor is electrically connected to the first clock signal terminal, a first electrode of the seventh transistor is electrically connected to the first reference signal terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node.

In some examples, the node control circuitry includes: an eighth transistor, a ninth transistor, a tenth transistor, a twelfth transistor, a thirteenth transistor, and a second capacitor;

a gate of the eighth transistor is electrically connected to the first node, a first electrode of the eighth transistor is electrically connected to the first clock signal terminal, and a second electrode of the eighth transistor is electrically connected to the fourth node;

a gate of the ninth transistor is electrically connected to the second clock signal terminal, a first electrode of the ninth transistor is electrically connected to the first node, and a second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor;

a gate of the tenth transistor is electrically connected to the fourth node, and a second pole of the tenth transistor is electrically connected to the second reference signal terminal;

a gate of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node;

a gate of the thirteenth transistor is electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor is electrically connected to the fifth node, and a second electrode of the thirteenth transistor is electrically connected to the second node;

the first electrode plate of the second capacitor is electrically connected with the gate of the twelfth transistor, and the second electrode plate of the second capacitor is electrically connected with the fifth node.

In some examples, the node control circuitry further comprises: an eleventh transistor;

a gate of the twelfth transistor is electrically connected to the fourth node through the eleventh transistor, and a gate of the eleventh transistor is electrically connected to the first reference signal terminal.

In some examples, the output circuit includes: a fourteenth transistor and a fifteenth transistor;

a gate of the fourteenth transistor is electrically connected to the third node, a first electrode of the fourteenth transistor is electrically connected to a first reference signal terminal, and a second electrode of the fourteenth transistor is electrically connected to the signal output terminal;

a gate of the fifteenth transistor is electrically connected to the second node, a first electrode of the fifteenth transistor is electrically connected to a second reference signal terminal, and a second electrode of the fifteenth transistor is electrically connected to the signal output terminal.

In some examples, further comprising: a fourth capacitor;

and a first electrode plate of the fourth capacitor is electrically connected with the first node, and a second electrode plate of the fourth capacitor is electrically connected with a second reference signal terminal.

In some examples, the control signal terminal and the input signal terminal are the same signal terminal.

The embodiment of the present disclosure further provides a driving control circuit, which includes a plurality of cascaded shift register units;

the input signal end of the first-stage shift register unit is electrically connected with the trigger signal end;

and each two adjacent stages of shift register units have the input signal end of the next stage of shift register unit electrically connected with the signal output end of the previous stage of shift register unit.

The embodiment of the disclosure also provides a display device comprising the drive control circuit.

In some examples, the display device includes a plurality of light emission control signal lines; the plurality of light-emitting control signal lines are correspondingly provided with the driving control circuit;

and one light-emitting control signal line is electrically connected with the signal output end of the first-stage shift register unit in the drive control circuit.

In some examples, the display device includes a plurality of scan lines; the plurality of scanning lines are correspondingly provided with the driving control circuit;

and one scanning line is electrically connected with the signal output end of the first-stage shift register unit in the drive control circuit.

The embodiment of the present disclosure further provides a driving method of the shift register unit, including:

in the first stage, a control circuit controls a signal of a first node and a signal of a second node according to a signal of an input signal end, a signal of a clock signal end and a signal of a reference signal end; the first transistor disconnects the first node from a third node; the second transistor conducts the control signal terminal and the first capacitor; the output circuit responds to the signal of the third node and controls the signal output end to output a signal;

in the second stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and a third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal;

in the third stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the input signal end, the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and a third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal;

in the fourth stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and a third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal;

in the fifth stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the input signal end, the signal of the clock signal end and the signal of the reference signal end; the first transistor is used for conducting the first node and the third node firstly and then disconnecting the first node and the third node; the second transistor conducts the control signal terminal and the first capacitor; the output circuit responds to the signal of the third node and controls the signal output end to output a signal.

In some examples, after the second stage and before the third stage, further comprising: at least one insertion phase; wherein the insertion phase comprises a first sub-insertion phase and a second sub-insertion phase;

in the first sub-insertion stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the input signal end, the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and a third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal;

in the second sub-insertion stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and a third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal.

The shift register unit, the driving control circuit, the display device and the driving method provided by the embodiment of the disclosure control signals of the first node and the second node through the control circuit. The first transistor controls the connection and disconnection between the first node and the third node. And the second transistor is used for controlling the connection and disconnection between the control signal end and the first capacitor. And controlling the signal output end to output a signal through the output circuit. Through the mutual cooperation of the components, the stability of the signal output by the signal output end can be improved.

Drawings

FIG. 1 is a diagram illustrating some structures of a shift register unit according to an embodiment of the present disclosure;

FIG. 2 is another schematic diagram of a shift register unit according to an embodiment of the present disclosure;

FIG. 3 is a diagram illustrating some specific structures of a shift register unit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another exemplary structure of a shift register unit according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram of some signals in an embodiment of the present disclosure;

FIG. 6 is a timing diagram of further signals in an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of some further embodiments of shift register units according to the present disclosure;

FIG. 8a is a timing diagram of some further signals in the disclosed embodiment;

FIG. 8b is a timing diagram of some further signals in the disclosed embodiment;

FIG. 9 is a schematic diagram of some further embodiments of shift register units according to the present disclosure;

FIG. 10 is a simulation of some of the simulations provided by the embodiments of the present disclosure;

FIG. 11 is a diagram of further simulation simulations provided by an embodiment of the present disclosure;

FIG. 12 is a flow chart of some driving methods of shift register cells in an embodiment of the present disclosure;

fig. 13 is some schematic structural diagrams of the driving control circuit in the embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. And the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

The shift register unit provided in the embodiment of the present disclosure, as shown in fig. 1, may include:

a control circuit 10 configured to control signals of the first node N1 and the second node N2 according to a signal of an input signal terminal IP, a signal of a clock signal terminal, and a signal of a reference signal terminal;

a first transistor M1, a gate of the first transistor M1 being electrically connected to the second node N2, a first pole of the first transistor M1 being electrically connected to the first node N1, a second pole of the first transistor M1 being electrically connected to the third node N3;

a second transistor M2, wherein a gate of the second transistor M2 is electrically connected to the third node N3, and a first pole of the second transistor M2 is electrically connected to the control signal terminal CS;

a first capacitor C1, a first electrode plate of the first capacitor C1 being electrically connected to the second electrode of the second transistor M2, a second electrode plate of the first capacitor C1 being electrically connected to the third node N3;

the output circuit 20 is configured to control the signal output terminal OP to output a signal in response to the signal of the third node N3 and the signal of the second node N2.

The shift register unit provided by the embodiment of the present disclosure controls signals of the first node N1 and the second node N2 through the control circuit 10. The conduction and the disconnection between the first node N1 and the third node N3 are controlled by the first transistor M1. The on and off between the control signal terminal CS and the first capacitor C1 is controlled by the second transistor M2. The signal output terminal OP outputs a signal through the output circuit 20. Through the mutual cooperation of the components, the stability of the signal output by the signal output end OP can be improved, and the pull-down delay time of the signal output end is reduced.

In particular implementation, in the embodiment of the present disclosure, when the first transistor M1 is in a conducting state, the first node N1 and the third node N3 may be turned on. When the first transistor M1 is in an off state, the first node N1 and the third node N3 may be turned off.

In practical implementation, in the embodiment of the present disclosure, when the second transistor M2 is in a conducting state, the control signal terminal CS and the first capacitor C1 may be conducted. When the second transistor M2 is in an off state, the control signal terminal CS and the first capacitor C1 may be disconnected.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 1, the clock signal terminals may include a first clock signal terminal CK1 and a second clock signal terminal CK 2. The reference signal terminals include a first reference signal terminal VREF1 and a second reference signal terminal VREF 2. The control circuit 10 is electrically connected to the first clock signal terminal CK1, the second clock signal terminal CK2, the first reference signal terminal VREF1, the second reference signal terminal VREF2, and the input signal terminal IP, respectively.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 2, the control circuit 10 may include:

an input circuit 11 configured to supply a signal of an input signal terminal IP to the first node N1 under the control of a signal of a first clock signal terminal CK1, and supply a signal of a first reference signal terminal VREF1 to the fourth node N4 under the control of a signal of a first clock signal terminal CK 1;

a node control circuit 12 configured to supply the signal of the first clock signal terminal CK1 to the fourth node N4 under the control of the signal of the first node N1; the signal of the second reference signal terminal VREF2 is provided to the first node N1 under the control of the signals of the fourth node N4 and the second clock signal terminal CK 2; the signal of the second clock signal terminal CK2 is supplied to the fifth node N5 under the control of the signal of the fourth node N4; the fifth node N5 is turned on with the second node N2 under the control of the signal of the second clock signal terminal CK 2;

and a noise reduction circuit 13 configured to adjust a signal of the second node N2 according to a signal of the second reference signal terminal VREF 2.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 3, the noise reduction circuit 13 may include: a third transistor M3; the gate of the third transistor M3 is electrically connected to the third node N3, the first pole of the third transistor M3 is electrically connected to the second reference signal terminal VREF2, and the second pole of the third transistor M3 is electrically connected to the second node N2.

In specific implementation, in the embodiment of the present disclosure, when the third transistor M3 is in a turned-on state, the second reference signal terminal VREF2 may be turned on with the second node N2. When the third transistor M3 is in a turn-off state, the second reference signal terminal VREF2 may be disconnected from the second node N2.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 3, the input circuit 11 may include: a sixth transistor M6 and a seventh transistor M7; the gate of the sixth transistor M6 is electrically connected to the first clock signal terminal CK1, the first pole of the sixth transistor M6 is electrically connected to the input signal terminal IP, and the second pole of the sixth transistor M6 is electrically connected to the first node N1. And, the gate of the seventh transistor M7 is electrically connected to the first clock signal terminal CK1, the first pole of the seventh transistor M7 is electrically connected to the first reference signal terminal VREF1, and the second pole of the seventh transistor M7 is electrically connected to the fourth node N4.

In practical implementation, in the embodiment of the present disclosure, when the sixth transistor M6 is in a conducting state, the input signal terminal IP may be conducted with the first node N1. When the sixth transistor M6 is in an off state, the input signal terminal IP may be disconnected from the first node N1.

In specific implementation, in the embodiment of the present disclosure, when the seventh transistor M7 is in a conducting state, the first reference signal terminal VREF1 may be conducted with the fourth node N4. When the seventh transistor M7 is in an off state, the first reference signal terminal VREF1 may be disconnected from the fourth node N4.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 3, the node control circuit 12 includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a second capacitor C2. The gate of the eighth transistor M8 is electrically connected to the first node N1, the first pole of the eighth transistor M8 is electrically connected to the first clock signal terminal CK1, and the second pole of the eighth transistor M8 is electrically connected to the fourth node N4. A gate of the ninth transistor M9 is electrically connected to the second clock signal terminal CK2, a first pole of the ninth transistor M9 is electrically connected to the first node N1, and a second pole of the ninth transistor M9 is electrically connected to the first pole of the tenth transistor M10. A gate of the tenth transistor M10 is electrically connected to the fourth node N4, and a second pole of the tenth transistor M10 is electrically connected to the second reference signal terminal VREF 2. A gate of the twelfth transistor M12 is electrically connected to the fourth node N4, a first pole of the twelfth transistor M12 is electrically connected to the second clock signal terminal CK2, and a second pole of the twelfth transistor M12 is electrically connected to the fifth node N5. A gate of the thirteenth transistor M13 is electrically connected to the second clock signal terminal CK2, a first pole of the thirteenth transistor M13 is electrically connected to the fifth node N5, and a second pole of the thirteenth transistor M13 is electrically connected to the second node N2. A first electrode plate of the second capacitor C2 is electrically connected to the gate of the twelfth transistor M12, and a second electrode plate of the second capacitor C2 is electrically connected to the fifth node N5.

In particular implementation, in the embodiment of the present disclosure, when the ninth transistor M9 is in a conducting state, the first node N1 may be electrically conducted with the first pole of the tenth transistor M10. When the ninth transistor M9 is in an off state, the first node N1 may be disconnected from the first pole of the tenth transistor M10.

In particular implementation, in the embodiment of the present disclosure, when the tenth transistor M10 is in a conducting state, the first pole of the tenth transistor M10 may be conducted with the second reference signal terminal VREF 2. When the tenth transistor M10 is in an off state, the first pole of the tenth transistor M10 may be disconnected from the second reference signal terminal VREF 2.

In practical implementation, in the embodiment of the present disclosure, when the twelfth transistor M12 is in a conducting state, the second clock signal terminal CK2 may be conducted with the fifth node N5. When the twelfth transistor M12 is in an off state, the second clock signal terminal CK2 may be disconnected from the fifth node N5.

In practical implementation, in the embodiment of the present disclosure, when the thirteenth transistor M13 is in a conducting state, the fifth node N5 and the second node N2 may be conducted. When the thirteenth transistor M13 is in an off state, the fifth node N5 may be disconnected from the second node N2.

In practical implementation, in the embodiment of the present disclosure, the voltage across the second capacitor C2 may be kept stable, so as to improve the stability of the voltage at the gate of the twelfth transistor M12 and the voltage at the fifth node N5.

In specific implementation, in this embodiment of the present disclosure, as shown in fig. 4, the node control circuit 12 further includes: an eleventh transistor M11; a gate of the twelfth transistor M12 is electrically connected to the fourth node N4 through the eleventh transistor M11, and a gate of the eleventh transistor M11 is electrically connected to the first reference signal terminal VREF 1. This may improve the stability of the voltage of the gate of the twelfth transistor M12 by the eleventh transistor M11.

In practical implementation, in the embodiment of the present disclosure, when the eleventh transistor M11 is in a conducting state, the fourth node N4 may be conducted with the gate of the twelfth transistor M12. When the eleventh transistor M11 is in an off state, the fourth node N4 may be disconnected from the gate of the twelfth transistor M12.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 3, the output circuit 20 may include: a fourteenth transistor M14 and a fifteenth transistor M15. A gate of the fourteenth transistor M14 is electrically connected to the third node N3, a first pole of the fourteenth transistor M14 is electrically connected to the first reference signal terminal VREF1, and a second pole of the fourteenth transistor M14 is electrically connected to the signal output terminal OP. And the gate of the fifteenth transistor M15 is electrically connected to the second node N2, the first pole of the fifteenth transistor M15 is electrically connected to the second reference signal terminal VREF2, and the second pole of the fifteenth transistor M15 is electrically connected to the signal output terminal OP.

In practical implementation, in the embodiment of the disclosure, when the fourteenth transistor M14 is in a conducting state, the first reference signal terminal VREF1 and the signal output terminal OP may be conducted. When the fourteenth transistor M14 is in an off state, the first reference signal terminal VREF1 may be disconnected from the signal output terminal OP.

In specific implementation, in the embodiment of the present disclosure, when the fifteenth transistor M15 is in a conducting state, the second reference signal terminal VREF2 may be conducted with the signal output terminal OP. When the fifteenth transistor M15 is in an off state, the second reference signal terminal VREF2 may be disconnected from the signal output terminal OP.

In specific implementation, in this embodiment of the disclosure, as shown in fig. 4, the shift register unit may further include: a fourth capacitor C4. A first electrode plate of the fourth capacitor C4 is electrically connected to the first node N1, and a second electrode plate of the fourth capacitor C4 is electrically connected to the second reference signal terminal VREF 2. This may improve the stability of the first node N1 through the fourth capacitor C4.

In a specific implementation, the first electrode of the transistor may serve as a source and the second electrode may serve as a drain, depending on a signal flowing direction; alternatively, the first pole serves as the drain thereof, and the second pole serves as the source thereof, which are not specifically distinguished herein.

It should be noted that the transistor mentioned in the above embodiments of the present disclosure may be a TFT, and may also be a Metal Oxide Semiconductor field effect transistor (MOS), which is not limited herein.

In order to simplify the manufacturing process, in the embodiment of the present disclosure, all the transistors may be P-type transistors as shown in fig. 3. Wherein the voltage difference V between the gate and the source of the P-type transistor_gsAnd its threshold voltage V_thSatisfies the relation V_gs<V_thIs turned on. For example, the first transistor M1 can be a P-type transistor, and the voltage difference V between the gate and the source of the first transistor M1_gs1And its threshold voltage V_th1The relationship between them satisfies the formula: v_gs1<V_th1Is turned on. Of course, in the embodiments of the present disclosure, the case where the transistor is a P-type transistor is merely described as an example, and the design principle of the case where the transistor is an N-type transistor is the same as that of the present disclosure, and the present disclosure also falls within the protection scope of the present disclosure. And, the voltage difference V between the gate and the source of the N-type transistor_gsAnd its threshold voltage V_thSatisfies the relation V_gs>V_thIs turned on. For example, the first transistor M1 can be an N-type transistor, and the voltage difference V between the gate and the source of the first transistor M1_gs1And its threshold voltage V_th1The relationship between them satisfies the formula: v_gs1>V_th1Is turned on.

In specific implementation, in the embodiment of the disclosure, when the active pulse signal of the input signal terminal IP is a high level signal, the signal of the first reference signal terminal VREF1 is a low level signal, and the signal of the second reference signal terminal VREF2 is a high level signal. Alternatively, in specific implementation, in the embodiment of the present disclosure, when the active pulse signal of the input signal terminal IP is a low-level signal, the signal of the first reference signal terminal VREF1 is a high-level signal, and the signal of the second reference signal terminal VREF2 is a low-level signal. It should be noted that, as shown in fig. 5, the active pulse signal at the input signal terminal IP refers to a high level signal input to the sixth transistor M6 within one frame time to control the eighth transistor M8 to be turned off, so that the shift register unit can operate.

Further, in the implementation, the P-type transistor is turned off by a high-level signal and turned on by a low-level signal. The N-type transistor is turned on under the action of a high-level signal and is turned off under the action of a low-level signal.

The above is merely to illustrate the specific structure of the shift register unit provided in the embodiment of the present disclosure, and in the specific implementation, the specific structure of each circuit is not limited to the structure provided in the embodiment of the present disclosure, and may be other structures known to those skilled in the art, and is not limited herein.

In some examples the signal of the overall control signal terminal CS may be the same as the signal of the input signal terminal IP. For example, as shown in fig. 5.

The following describes the operation process of the shift register unit provided in the embodiment of the present disclosure with reference to the signal timing diagram shown in fig. 5 by taking the shift register unit shown in fig. 4 as an example. In the following description, a high level signal is denoted by 1, a low level signal is denoted by 0, and it should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation process of the embodiment of the present disclosure, and are not voltages applied to the gates of the transistors in specific implementation.

Specifically, the first, second, third, fourth, and fifth phases T1, T2, T3, T4, and T5 in the signal timing diagram shown in fig. 5 are selected. It should be noted that the signal timing diagram shown in fig. 5 is only the operation process of one shift register unit in one frame time. The working processes of the shift register unit in other frames are respectively substantially the same as the working process in the frame, and are not described herein again.

Wherein IP represents the signal of the input signal terminal IP, CK1 represents the signal of the first clock signal terminal CK1, CK2 represents the signal of the second clock signal terminal CK2, OP represents the signal of the signal output terminal OP, and CS represents the signal of the control signal terminal CS.

In the first period T1, the signal ck1 is a low level signal, and controls both the sixth transistor M6 and the seventh transistor M7 to be turned on. The turned-on sixth transistor M6 may provide a high-level signal ip to the first node N1 to make the signal of the first node N1 a high-level signal, thereby controlling the eighth transistor M8 to be turned off. The turned-on seventh transistor M7 provides the low level signal of the first reference signal terminal VREF1 to the fourth node N4, so that the signal of the fourth node N4 is a low level signal, and the eleventh transistor M11 is turned on by the low level signal of the first reference signal terminal VREF1, so that the signal of the gate of the twelfth transistor M12 can be a low level signal to control the twelfth transistor M12 to be turned on. The thirteenth transistor M13 is turned off under the control of the high level signal of the second clock signal terminal CK 2. The second node N2 can be maintained as a high signal by the third capacitor C3, thereby controlling both the first transistor M1 and the fifteenth transistor M15 to be turned off. The second transistor M2 is turned on during a period of time from the beginning of the first phase, so that the high level signal of the control signal terminal CS is provided to the sixth node N6 (the sixth node N6 is connected between the second pole of the second transistor M2 and the first electrode plate of the first capacitor C1), so that the signal at the sixth node N6 is a high level signal. Due to the function of the first capacitor C1, the signal of the third node N3 can be pulled up from the low level signal to the high level signal, thereby controlling the third transistor M3 and the fourteenth transistor M14 to be turned off. Since both the fourteenth transistor M14 and the fifteenth transistor M15 are turned off, the output signal terminal maintains the low level signal output of the previous stage. For example, in practical applications, in the first phase T1, the third capacitor C3 may maintain the voltage of the high level signal at the second node N2 to be about 7V, so as to control the fifteenth transistor M15 to be turned off. The high level signal of about 7V of the control signal terminal CS is input to the sixth node N6, so that the voltage of the high level signal input to the sixth node N6 can be raised to about 7V, and due to the action of the second capacitor C2, the signal of the third node N3 can be raised from the low level signal to the high level signal of about 1V, thereby controlling the fourteenth transistor M14 to be turned off. Since the gate-source voltage Vgs2 of the second transistor M2 is Vg2-Vs2 is 1-7-6, Vgs2< Vth2 can be made, so that the second transistor M2 can be controlled to be turned on. Wherein Vth2 is the threshold voltage of the second transistor M2.

In the second stage T2, the signal ck1 is a high level signal, and controls both the sixth transistor M6 and the seventh transistor M7 to be turned off. Since the tenth transistor M10 is turned on and the ninth transistor M9 is turned on under the control of the low level signal of ck2, the high level signal of the second reference signal terminal VREF2 may be supplied to the first node N1, the signal of the first node N1 may be controlled to be the high level signal, and thus the eighth transistor M8 is controlled to be turned off. By the action of the second capacitor C2, the signal at the gate of the twelfth transistor M12 can be maintained as a low-level signal, so that the twelfth transistor M12 can be controlled to be turned on, and the thirteenth transistor M13 is controlled to be turned on by the low-level signal of the signal ck2, so that the low-level signal of the signal ck2 can be provided to the second node N2, so that the signal at the second node N2 is a low-level signal, so that the fifteenth transistor M15 and the first transistor M1 can be controlled to be turned on. The turned-on first transistor M1 may provide a high level signal of the first node N1 to the third node N3 to make the signal of the third node N3 a high level signal, thereby controlling the third transistor M3 and the fourteenth transistor M14 to be turned off. The turned-on fifteenth transistor M15 may provide the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal OP output by the signal output terminal OP is a high-level signal.

In the third stage T3, the signal ck1 is a low level signal, and controls both the sixth transistor M6 and the seventh transistor M7 to be turned on. The turned-on sixth transistor M6 provides the high level signal IP of the input signal terminal IP to the first node N1 to make the signal of the first node N1 be a high level signal, so that the eighth transistor M8 can be controlled to be turned off. The turned-on seventh transistor M7 provides the low level signal of the first reference signal terminal VREF1 to the fourth node N4, so that the signal of the fourth node N4 is a low level signal, and the eleventh transistor M11 is turned on by the low level signal of the first reference signal terminal VREF1, so that the signal of the gate of the twelfth transistor M12 can be a low level signal to control the twelfth transistor M12 to be turned on. The thirteenth transistor M13 is turned off under the control of the high level signal of the second clock signal terminal CK 2. The second node N2 can be kept at a low level signal by the third capacitor C3, thereby controlling the first transistor M1 and the fifteenth transistor M15 to be turned on. The turned-on first transistor M1 may provide a high level signal of the first node N1 to the third node N3 to make the signal of the third node N3 a high level signal, thereby controlling the third transistor M3 and the fourteenth transistor M14 to be turned off. The turned-on fifteenth transistor M15 may provide the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal OP output by the signal output terminal OP is a high-level signal.

In the fourth stage T4, the signal ck1 is a high level signal, and controls both the sixth transistor M6 and the seventh transistor M7 to be turned off. Due to the function of the fourth capacitor C4, the signal at the first node N1 can be controlled to be a high level signal, so that the eighth transistor M8 is controlled to be turned off. By the action of the second capacitor C2, the signal at the gate of the twelfth transistor M12 can be maintained as a low level signal, so that the twelfth transistor M12 and the tenth transistor M10 can be controlled to be turned on. The tenth transistor M10, which is turned on, and the ninth transistor M9, which is turned on by the low level signal of the signal ck2, may provide the high level signal of the second reference signal terminal VREF2 to the first node N1, so that the first node N1 may be further stabilized as a high level signal. Also, since the thirteenth transistor M13 is turned on by the control of the low level signal of the signal ck2, the low level signal of the signal ck2 may be supplied to the second node N2 to make the signal of the second node N2 a low level signal, so that the fifteenth transistor M15 and the first transistor M1 may be controlled to be turned on. The turned-on first transistor M1 may provide a high level signal of the first node N1 to the third node N3 to make the signal of the third node N3 a high level signal, thereby controlling the third transistor M3 and the fourteenth transistor M14 to be turned off. The turned-on fifteenth transistor M15 may provide the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal OP output by the signal output terminal OP is a high-level signal.

In the fifth stage T5, the signal ck1 is a low level signal, and controls both the sixth transistor M6 and the seventh transistor M7 to be turned on. The turned-on sixth transistor M6 may provide a low level signal IP of the input signal terminal IP to the first node N1, so that the signal at the first node N1 is a low level signal, thereby controlling the eighth transistor M8 to be turned on. The turned-on seventh transistor M7 provides the low-level signal of the first reference signal terminal VREF1 to the fourth node N4, so that the signal of the fourth node N4 is a low-level signal. The turned-on eighth transistor M8 may provide a low level signal of the signal ck1 to the fourth node N4 to further make the signal of the fourth node N4 a low level signal. And the eleventh transistor M11 is turned on by the low-level signal of the first reference signal terminal VREF1, so that the signal at the gate of the twelfth transistor M12 is a low-level signal to control the twelfth transistor M12 to be turned on. The thirteenth transistor M13 is turned off under the control of the high level signal of the second clock signal terminal CK 2. The signal of the third node N3 can be controlled to be a low level signal due to the effect of the first capacitor C1, so that the second transistor M2 can be controlled to be turned on to provide the low level signal of the control signal terminal CS to the sixth node N6, so that the signal of the sixth node N6 is a low level signal. Due to the first capacitor C1, the low level signal of the third node N3 may be further pulled low, thereby controlling the third transistor M3 and the fourteenth transistor M14 to be fully turned on as much as possible. The turned-on third transistor M3 provides the high level signal of the second reference signal terminal VREF2 to the second node N2, so that the signal of the second node N2 is a high level signal, thereby controlling both the first transistor M1 and the fifteenth transistor M15 to be turned off. The fourteenth transistor M14, which is turned on, may provide the low-level signal of the first reference signal terminal VREF1 to the signal output terminal OP, so that the signal OP at the signal output terminal OP is a low-level signal.

It should be noted that, in the fifth stage T5, when the signal IP input to the signal terminal IP is a low-level signal, the signal ck1 starts to change from a high-level signal to a low-level signal, the low level of the signal IP is input to the third node N3 from M1 (at this time, the first transistor M1 is not turned off), after the level of the third node N3 drops, the second transistor M2 is turned on, so that the low-level signal of the control signal terminal CS is input to the sixth node N6, so that the level of the sixth node N6 is switched to a low level, the level of the third node N3 is further pulled down in combination with the action of the first capacitor C1 (for example, the voltage of the third node N3 after being further pulled down is about-10.8V at this time), and the fourteenth transistor M14 can be kept turned on.

After the low level of the signal ip is inputted to the first node N1, the high level signal of the second reference signal terminal VREF2 is inputted to the second node N2, and the voltage of the second node N2 rises to the high level (for example, about 7V) after a period of time, so as to control the first transistor M1 and the fifteenth transistor M15 to be turned off, and at this time, the transition of the third node N3 is completed. That is, a local circuit path composed of the control signal terminal CS, the second transistor M2, the first capacitor C1 and the third node N3 is turned on. Thereafter, in a period in which the signal ip is a low level signal (e.g., voltage-7V), since the first transistor M1 is turned off, the low level signal inputted from the sixth transistor M6 does not affect the voltage of the third node N3. The third node N3 can be kept at a low level of-10.5V for a long time based on the local circuit path formed by the control signal terminal CS, the second transistor M2, the first capacitor C1 and the third node N3, so that the fourteenth transistor M14 can be kept continuously turned on when the signal IP at the input signal terminal IP is at a low level. Further, the signal output end OP can continuously output the low-level signal of the first reference signal end VREF1, thereby improving the output stability of the signal output end OP.

And, because in the fifth stage T5, the fourteenth transistor M14 may be fully turned on as much as possible, so that the high level signal of the signal output end OP may be pulled down by the low level signal of the first reference signal end VREF1 relatively quickly, and thus the high level signal of the signal output end OP may be changed into a low level signal relatively quickly, and further the pull-down delay time of the signal output end OP may be reduced. For example, the pull-down delay time of the signal output terminal OP can be reduced from 4.15 μ s to 0.62 μ s.

The embodiment of the present disclosure provides timing diagrams of signals of other shift register units, as shown in fig. 6, which are modified from the implementation manner in the foregoing embodiment. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In the disclosed embodiment, as shown in fig. 6, after the second stage T2 and before the third stage T3, it may further include: at least one insertion phase T0. For example, the duration of one insertion period T0 may be the duration of one clock cycle of the signal CK2 of the first clock signal terminal CK 2. For example, one insertion phase T0 may be included, two insertion phases T0 may be included, three insertion phases T0 may be included, or more insertion phases T0 may be included. Of course, in practical applications, the specific number of the insertion stages T0 may be determined according to the requirements of practical applications, and is not limited herein.

In the embodiment of the present disclosure, as shown in fig. 6, the insertion phase T0 may include a first sub-insertion phase T01 and a second sub-insertion phase T02. The following description will be made with reference to the shift register unit shown in fig. 4 with reference to the timing chart shown in fig. 6. In addition, only the working processes in the first sub-insertion stage T01 and the second sub-insertion stage T02 are described below, and the first stage T1, the second stage T2, the third stage T3, the fourth stage T4, and the fifth stage T5 are substantially the same as the above embodiments, and are not repeated herein.

In the first sub-insertion period T01, the signal ck1 is a low level signal, and controls both the sixth transistor M6 and the seventh transistor M7 to be turned on. The turned-on sixth transistor M6 provides the high level signal IP of the input signal terminal IP to the first node N1, so that the signal of the first node N1 is a high level signal, and thus the eighth transistor M8 and the third transistor M3 can be controlled to be turned off. The turned-on seventh transistor M7 provides the low level signal of the first reference signal terminal VREF1 to the fourth node N4, so that the signal of the fourth node N4 is a low level signal, and the eleventh transistor M11 is turned on by the low level signal of the first reference signal terminal VREF1, so that the signal of the gate of the twelfth transistor M12 can be a low level signal to control the twelfth transistor M12 to be turned on. The thirteenth transistor M13 is turned off under the control of the high level signal of the second clock signal terminal CK 2. The second node N2 can be kept at a low level signal by the third capacitor C3, thereby controlling the first transistor M1 and the fifteenth transistor M15 to be turned on. The turned-on first transistor M1 may provide a high level signal of the first node N1 to the third node N3 to make the signal of the third node N3 a high level signal, thereby controlling the fourteenth transistor M14 to be turned off. The turned-on fifteenth transistor M15 may provide the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal OP output by the signal output terminal OP is a high-level signal.

In the second sub-insertion period T02, the signal ck1 is a high level signal, and controls both the sixth transistor M6 and the seventh transistor M7 to be turned off. Due to the function of the fourth capacitor C4, the signal at the first node N1 can be controlled to be a high level signal, so that the eighth transistor M8 and the third transistor M3 are both controlled to be turned off. By the action of the second capacitor C2, the signal at the gate of the twelfth transistor M12 can be maintained as a low level signal, so that the twelfth transistor M12 and the tenth transistor M10 can be controlled to be turned on. The tenth transistor M10, which is turned on, and the ninth transistor M9, which is turned on by the low level signal of the signal ck2, may provide the high level signal of the second reference signal terminal VREF2 to the first node N1, so that the first node N1 may be further stabilized as a high level signal. Also, since the thirteenth transistor M13 is turned on by the control of the low level signal of the signal ck2, the low level signal of the signal ck2 may be supplied to the second node N2 to make the signal of the second node N2 a low level signal, so that the fifteenth transistor M15 and the first transistor M1 may be controlled to be turned on. The turned-on first transistor M1 may provide a high level signal of the first node N1 to the third node N3 to make the signal of the third node N3 a high level signal, thereby controlling the fourteenth transistor M14 to be turned off. The turned-on fifteenth transistor M15 may provide the high-level signal of the second reference signal terminal VREF2 to the signal output terminal OP, so that the signal OP output by the signal output terminal OP is a high-level signal.

The embodiment of the present disclosure provides a schematic structural diagram of another shift register unit, as shown in fig. 7, which is modified from the implementation manner in the foregoing embodiment. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In the embodiment of the present disclosure, as shown in fig. 7, the control signal terminal CS and the input signal terminal IP may be the same signal terminal. For example, the first pole of the second transistor M2 is directly electrically connected to the input signal terminal IP.

The corresponding signal timing diagram of the shift register unit shown in FIG. 7 is shown in FIG. 8 a. The specific operation processes of the first stage T1, the second stage T2, the third stage T3, the fourth stage T4 and the fifth stage T5 may be substantially the same as the operation process of the shift register unit shown in fig. 5, and are not described herein again.

The embodiment of the present disclosure provides timing diagrams of signals of other shift register units, as shown in fig. 8b, which are modified from the implementation manner in the above embodiment. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In the embodiment of the present disclosure, as shown in fig. 8b, the insertion phase T0 may include a first sub-insertion phase T01 and a second sub-insertion phase T02. The following description will be made with reference to the shift register unit shown in fig. 7, with reference to the timing chart shown in fig. 8 b. In addition, only the working processes in the first sub-insertion stage T01 and the second sub-insertion stage T02 are described below, and the first stage T1, the second stage T2, the third stage T3, the fourth stage T4, and the fifth stage T5 are substantially the same as the above embodiments, and are not repeated herein.

The embodiment of the present disclosure provides a schematic structural diagram of still other shift register units, as shown in fig. 9, which is modified from the implementation manner in the foregoing embodiment. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In the embodiment of the present disclosure, as shown in fig. 9, the noise reduction circuit 13 includes: a fourth transistor M4 and a fifth transistor M5; a gate of the fourth transistor M4 is electrically connected to the third node N3, a first pole of the fourth transistor M4 is electrically connected to the second reference signal terminal VREF2, and a second pole of the fourth transistor M4 is electrically connected to the first pole of the fifth transistor M5. A gate of the fifth transistor M5 is electrically connected to the first clock signal terminal CK1, and a second pole of the fifth transistor M5 is electrically connected to the second node N2.

The signal timing diagram of the shift register unit shown in fig. 9 can be as shown in fig. 8 a.

In the first stage T1, due to the effect of the second capacitor C2, the signal at the third node N3 can be raised from the low level signal to a high level signal of about 1V, so that the fourth transistor M4 can be controlled to be turned off. In addition, the rest of the working processes at this stage may be the same as the working processes of the shift register unit shown in fig. 5 at the first stage, which is not described herein in detail.

In the second stage T2, since the signal at the third node N3 is a high level signal, the fourth transistor M4 can be controlled to be turned off. In addition, the rest of the working processes at this stage may be the same as the working processes of the shift register unit shown in fig. 5 at the second stage, which is not described herein again. In this stage, since the fifth transistor M5 is provided and ck2 is at a high level, the fifth transistor M5 can be controlled to be turned off, so that the high level signal of the second reference signal terminal VREF2 can be prevented from affecting the signal of the second node N2, and the signal of the second node N2 can be stabilized as a low level signal.

In the third stage T3, since the signal at the third node N3 is a high level signal, the fourth transistor M4 can be controlled to be turned off. In addition, the rest of the working processes at this stage may be the same as the working processes of the shift register unit shown in fig. 5 at the third stage, which is not described herein in detail.

In the fourth stage T4, since the signal of the third node N3 is a high level signal, the fourth transistor M4 can be controlled to be turned off. In addition, the rest of the working processes at this stage may be the same as the working processes of the shift register unit in the fourth stage shown in fig. 5, which are not described herein in detail.

In the fifth stage T5, since the signal of the third node N3 is a low level signal, the fourth transistor M4 can be controlled to be turned on. Also, the fifth transistor M5 is turned on under the control of the low level signal of the signal ck1, so that the high level signal of the second reference signal terminal VREF2 can be supplied to the second node N2 through the turned-on fourth transistor M4 and fifth transistor M5, so that the signal of the second node N2 is a high level signal. In addition, the rest of the working processes at this stage may be the same as the working processes of the shift register unit in the fifth stage shown in fig. 5, which are not described herein in detail.

The signal timing diagram corresponding to the shift register unit shown in fig. 9 can also be as shown in fig. 8b, which is not described herein again.

The embodiment of the present disclosure further provides a driving method of a shift register unit, as shown in fig. 12, the driving method may include:

s10, in the first stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the input signal end, the signal of the clock signal end and the signal of the reference signal end; the first transistor disconnects the first node from the third node; the second transistor conducts the control signal end and the first capacitor; the output circuit responds to the signal of the third node and controls the signal output end to output a signal;

s20, in the second stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and the third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal;

s30, in the third stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the input signal end, the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and the third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal;

s40, in the fourth stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and the third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal;

s50, in the fifth stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the input signal end, the signal of the clock signal end and the signal of the reference signal end; the first transistor is used for conducting the first node and the third node firstly and then disconnecting the first node and the third node; the second transistor conducts the control signal end and the first capacitor; the output circuit controls the signal output terminal to output a signal in response to a signal of the third node.

In the embodiment of the present disclosure, after the second stage and before the third stage, the method further includes: at least one insertion phase; wherein, the insertion stage comprises a first sub-insertion stage and a second sub-insertion stage;

in the first sub-insertion stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the input signal end, the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and the third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal;

in the second sub-insertion stage, the control circuit controls the signal of the first node and the signal of the second node according to the signal of the clock signal end and the signal of the reference signal end; the first transistor conducts the first node and the third node; the second transistor disconnects the control signal terminal from the first capacitor; the output circuit responds to the signal of the second node and controls the signal output end to output a signal.

The driving principle and the specific implementation of the driving method are the same as those of the shift register unit in the above embodiments, and therefore, the driving method can be implemented by referring to the specific implementation of the shift register unit in the above embodiments, and is not described herein again.

Based on the structure of the shift register unit and the driving method thereof in the embodiments of the present disclosure, the signal of the third node N3 of the shift register unit in the embodiments of the present disclosure is subjected to analog simulation, and the signal output by the signal output terminal OP is subjected to analog simulation. And, based on the structure of the shift register unit and the driving method thereof in the related art, the signal of the third node N3 of the shift register unit in the related art is simulated, and the signal output from the signal output terminal OP is simulated. A simulation diagram for simulating the signal of the third node N3 is shown in fig. 10. A simulation diagram for performing simulation on the signal at the signal output terminal OP is shown in fig. 11. In fig. 10 and 11, the abscissa represents time, and the ordinate represents voltage. L11 represents the signal variation curve of the simulation of the signal at the signal output terminal OP of the shift register unit in the prior art, and L12 represents the signal variation curve of the simulation of the signal at the signal output terminal OP of the shift register unit in the embodiment of the present disclosure. L21 represents a signal variation curve for simulating the signal of the third node N3 of the shift register unit in the prior art, and L22 represents a signal variation curve for simulating the signal of the third node N3 of the shift register unit in the embodiment of the present disclosure. As can be seen from fig. 10 and 11, compared to the shift register cell in the prior art, the embodiment of the present disclosure may make the voltage of the low level of the third node N3 lower than the voltage of the low level of the third node N3 of the shift register cell in the prior art at the time T0 (i.e., at the time in the fifth phase T5) by providing the second transistor M2 and the first capacitor. In the embodiment of the present disclosure, the low level of the third node N3 is lower at time t0, and the fourteenth transistor M14 can be turned on as much as possible, so that the fourteenth transistor M14 can output the low level signal of the first reference signal terminal to the signal output terminal OP in time, thereby shortening the time for the signal output terminal OP to switch from the high level to the low level.

The embodiment of the present disclosure further provides a driving control circuit, as shown in fig. 13, including a plurality of cascaded shift register units SR (1), SR (2) … SR (N-1), SR (N) … SR (N-1), SR (N) (N shift registers, N is greater than or equal to 1 and less than or equal to N, N is an integer); wherein,

an input signal end IP of the first-stage shift register unit is electrically connected with a trigger signal end STV;

and each two adjacent shift register units have the input signal end IP of the next shift register unit electrically connected with the signal output end OP of the previous shift register unit.

Specifically, the specific structure of each shift register unit in the driving control circuit is identical to the shift register unit in the present disclosure in function and structure, and repeated descriptions are omitted. The driving control circuit may be configured in a liquid crystal display panel or an electroluminescence display panel, and is not limited herein.

Specifically, in the driving control circuit provided in the embodiment of the present disclosure, as shown in fig. 13, the first reference signal terminals VREF1 of the shift register units sr (n) of each stage are coupled to the same dc signal terminal vdd, and the second reference signal terminals VREF2 of the shift register units sr (n) of each stage are coupled to the same dc signal terminal vss.

Specifically, in the above-described drive control circuit provided in the embodiment of the present disclosure, as shown in fig. 13, the first clock signal terminal CK1 of the 2k-1 th stage shift register unit and the second clock signal terminal CK2 of the 2 k-th stage shift register unit are both coupled to the same clock terminal, i.e., the first clock terminal CK 1; the second clock signal terminal CK2 of the 2k-1 stage shift register unit and the first clock signal terminal CK1 of the 2k stage shift register unit are both coupled to the same clock terminal, i.e., the second clock terminal CK 2; wherein k is a positive integer.

The embodiment of the disclosure also provides a display device, which comprises the drive control circuit provided by the embodiment of the disclosure. The principle of the display device to solve the problem is similar to the aforementioned driving control circuit, so the implementation of the display device can be referred to the implementation of the aforementioned driving control circuit, and the repeated parts are not described herein again.

In specific implementation, in the embodiment of the present disclosure, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

In one embodiment, the display device may include a plurality of pixel units, a plurality of gate lines and data lines, and each pixel unit may include a plurality of sub-pixels, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The display device provided in the embodiments of the present disclosure may be an organic light emitting display device, or may also be a liquid crystal display device, and is not limited herein.

In the disclosed embodiment, the display device includes a plurality of scan lines; the plurality of scanning lines are also correspondingly provided with a driving control circuit; one scanning line is electrically connected with the signal output end of the first-stage shift register unit in the drive control circuit. For example, when the display device provided by the embodiment of the present disclosure is a liquid crystal display device, the TFT in the sub-pixel may be electrically connected to a scan line, and the driving control circuit may be used as a gate driving circuit, and the gate driving circuit is electrically connected to the scan line and is applied to provide a gate scanning signal to the TFT in the sub-pixel. Note that the TFT in the sub-pixel may be an N-type transistor or a P-type transistor, and is not limited herein.

In the disclosed embodiment, the display device includes a plurality of light emission control signal lines and a plurality of scan lines; the plurality of light-emitting control signal lines are correspondingly provided with a drive control circuit; and one light-emitting control signal line is electrically connected with the signal output end of the first-stage shift register unit in the drive control circuit. The plurality of scanning lines are also correspondingly provided with a driving control circuit; one scanning line is electrically connected with the signal output end of the first-stage shift register unit in the drive control circuit. For example, in an organic light emitting display device, a plurality of organic light emitting diodes and pixel circuits connected to the respective organic light emitting diodes are generally provided. A light emission control transistor for controlling light emission of the organic light emitting diode and a scan control transistor for controlling input of a data signal are provided in a general pixel circuit. In a specific implementation, when the display device provided in the embodiment of the present disclosure is an organic light emitting display device, the light emitting control transistor may be electrically connected to the light emitting control signal line, and the scan control transistor may be electrically connected to the scan line, where the organic light emitting display device may include one of the driving control circuits provided in the embodiment of the present disclosure, the driving control circuit may be used as a light emitting driving circuit, and the light emitting driving circuit is electrically connected to the light emitting control transistor and is used for providing a light emitting control signal of the light emitting control transistor; alternatively, the driving control circuit can also be used as a gate driving circuit, and the gate driving circuit is electrically connected with the scanning line and is used for providing a gate scanning signal of the scanning control transistor. Of course, the organic light emitting display device may also include two of the above-mentioned driving control circuits provided in the embodiments of the present disclosure, wherein one of the driving control circuits may be used as a light emitting driving circuit, electrically connected to the light emitting control transistor, and used for providing a light emitting control signal of the light emitting control transistor; the other driving control circuit is used as a gate driving circuit, electrically connected to the scan line, and used for providing a gate scan signal of the scan control transistor, which is not limited herein.

It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations as well.

Claims

1. A shift register cell, comprising:

2. The shift register cell of claim 1, wherein the clock signal terminals comprise a first clock signal terminal and a second clock signal terminal;

the control circuit includes:

3. The shift register cell of claim 2, wherein the noise reduction circuit comprises: a third transistor;

4. The shift register cell of claim 2, wherein the noise reduction circuit comprises: a fourth transistor and a fifth transistor;

5. The shift register cell of claim 2, wherein the input circuit comprises: a sixth transistor and a seventh transistor;

6. The shift register cell of claim 2, wherein the node control circuit comprises: an eighth transistor, a ninth transistor, a tenth transistor, a twelfth transistor, a thirteenth transistor, and a second capacitor;

7. The shift register cell of claim 6, wherein the node control circuit further comprises: an eleventh transistor;

8. The shift register cell of any one of claims 1-7, wherein the output circuit comprises: a fourteenth transistor and a fifteenth transistor;

9. The shift register cell of any one of claims 1-7, further comprising: a fourth capacitor;

10. The shift register cell of any one of claims 1-7, wherein the control signal terminal and the input signal terminal are the same signal terminal.

11. A drive control circuit comprising a plurality of shift register cells according to any one of claims 1 to 10 in cascade;

12. A display device characterized by comprising the drive control circuit according to claim 11.

13. The display device according to claim 12, wherein the display device includes a plurality of light emission control signal lines; the plurality of light-emitting control signal lines are correspondingly provided with the driving control circuit;

14. The display device according to claim 12, wherein the display device includes a plurality of scan lines; the plurality of scanning lines are correspondingly provided with the driving control circuit;

15. A method of driving a shift register cell according to any one of claims 1 to 10, comprising:

16. The driving method as set forth in claim 15, further comprising, after the second stage and before the third stage: at least one insertion phase; wherein the insertion phase comprises a first sub-insertion phase and a second sub-insertion phase;