CN113838852B - Semiconductor memory device and method of forming the same - Google Patents
Semiconductor memory device and method of forming the same Download PDFInfo
- Publication number
- CN113838852B CN113838852B CN202111327962.4A CN202111327962A CN113838852B CN 113838852 B CN113838852 B CN 113838852B CN 202111327962 A CN202111327962 A CN 202111327962A CN 113838852 B CN113838852 B CN 113838852B
- Authority
- CN
- China
- Prior art keywords
- layer
- spacer
- storage node
- bit line
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 51
- 125000006850 spacer group Chemical group 0.000 claims abstract description 124
- 239000011800 void material Substances 0.000 claims abstract description 69
- 238000003860 storage Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000003990 capacitor Substances 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims description 97
- 238000005530 etching Methods 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims 3
- 239000010410 layer Substances 0.000 description 266
- 230000008569 process Effects 0.000 description 22
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 239000002355 dual-layer Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 239000010936 titanium Substances 0.000 description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 230000004931 aggregating effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium(II) oxide Chemical compound [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a semiconductor memory device and a forming method thereof. Bit lines are disposed on the substrate spaced apart from each other. The plugs are disposed on the substrate and alternate with the bit lines. The spacer structure is arranged on the substrate and positioned between the bit line and the plug, wherein the spacer structure comprises a first spacer layer, a first spacer and a second spacer layer, the first spacer and the second spacer layer are sequentially stacked between the side wall of the bit line and the plug, and the bottommost surface of the first spacer layer is not equal to the bottommost surface of the second spacer layer. Thus, two void layers can be formed between the bit line and the storage node plug to effectively improve the delay between the resistor and the capacitor.
Description
Technical Field
The present invention relates to a semiconductor memory device and a method for forming the same, and more particularly, to a semiconductor memory device having a void layer and a method for forming the same.
Background
With the trend toward miniaturization of various electronic products, the design of semiconductor memory devices must meet the requirements of high integration and high density. For the DRAM (dynamic random access memory, DRAM) with recessed gate structure, the current trend is that it has gradually replaced the DRAM with planar gate structure because it can obtain longer carrier channel length in the same semiconductor substrate to reduce the leakage of capacitor structure.
In general, a dram with a recessed gate structure is formed by aggregating a large number of memory cells (memory cells) to form an array region for storing information, and each memory cell may be formed by a transistor element in series with a capacitor element for receiving voltage information from Word Lines (WL) and Bit Lines (BL). In response to product requirements, the density of memory cells in the array region must be increased continuously, which results in increased difficulty and complexity in the related manufacturing process and design. Therefore, the prior art needs to be further improved to effectively improve the performance and reliability of the related memory device.
Disclosure of Invention
One object of the present invention is to provide a semiconductor memory device in which two void layers are formed between bit lines and memory node plugs, thereby effectively improving the delay between resistors and capacitors.
An object of the present invention is to provide a method of forming a semiconductor memory device, which removes a material layer formed between a bit line and a storage node plug using a storage node pad as a mask to form two void layers between the bit line and the storage node plug. Therefore, the invention can effectively form a double-layer gap layer between each bit line and each storage node plug on the premise of simplifying the manufacturing process, and improve the delay condition between the resistor and the capacitor.
In order to achieve the above object, one embodiment of the present invention provides a semiconductor memory device including a substrate, a plurality of bit lines, a plurality of plugs, and a spacer structure. The bit lines are disposed on the substrate spaced apart from each other. The plugs are disposed on the substrate and alternately disposed with the bit lines. The spacer structure is arranged on the substrate and located between the bit line and the plug, wherein the spacer structure comprises a first gap layer, a first spacer and a second gap layer, the first spacer and the second gap layer are sequentially stacked between the side wall of the bit line and the plug, and the bottommost surface of the first gap layer is not equal to the bottommost surface of the second gap layer.
In order to achieve the above object, one embodiment of the present invention provides a method for forming a semiconductor device, which includes the following steps. Providing a substrate; and forming a plurality of bit lines on the substrate, the bit lines being disposed apart from each other. A plurality of plugs are formed on the substrate, and the bit lines and the plugs are alternately arranged. And forming a spacer structure on the substrate and between the bit line and the plug, wherein the spacer structure comprises a first spacer layer, a first spacer and a second spacer layer, and the first spacer layer, the first spacer and the second spacer layer are sequentially stacked on the side wall of the bit line, wherein the bottommost surface of the first spacer layer is not equal to the bottommost surface of the second spacer layer.
Drawings
Fig. 1 to 7 are schematic views illustrating steps of a method for forming a semiconductor device according to a first embodiment of the present invention, wherein:
FIG. 1 is a schematic top view of a semiconductor memory device after forming bit lines and plugs;
FIG. 2 is a schematic cross-sectional view of FIG. 1 along the line A-A';
FIG. 3 is a schematic cross-sectional view of a semiconductor memory device after forming a storage node pad;
FIG. 4 is a schematic cross-sectional view of a semiconductor memory device after an etching process;
FIG. 5 is a schematic cross-sectional view of a semiconductor memory device after forming an insulating layer;
FIG. 6 is another cross-sectional view of a semiconductor memory device after forming an insulating layer;
FIG. 7 is a schematic cross-sectional view of a semiconductor memory device after forming a stacked structure;
FIG. 8 is a schematic cross-sectional view of a semiconductor memory device after forming a bottom electrode layer; and
fig. 9 is a schematic cross-sectional view of a semiconductor memory device after forming a top electrode layer.
Fig. 10 is a schematic cross-sectional view of a semiconductor memory device according to another embodiment of the present invention.
Fig. 11 to 12 are schematic views illustrating steps of a method for forming a semiconductor memory device according to a second embodiment of the present invention, wherein:
FIG. 11 is a schematic cross-sectional view of a semiconductor memory device after forming bit lines and plugs; and
fig. 12 is a schematic cross-sectional view of a semiconductor memory device after an insulating layer is formed.
Fig. 13 to 14 are schematic views illustrating steps of a method for forming a semiconductor memory device according to a third embodiment of the present invention, wherein:
FIG. 13 is a schematic cross-sectional view of a semiconductor memory device after forming bit lines and plugs; and
fig. 14 is a schematic cross-sectional view of a semiconductor memory device after forming an insulating layer.
Fig. 15 is a schematic cross-sectional view of a semiconductor memory device according to a fourth embodiment of the present invention.
Wherein reference numerals are as follows:
100. 200, 300, 400, 500 semiconductor memory device
101. Insulating region
103. Active region
110. Substrate and method for manufacturing the same
110a top surface
130. Dielectric layer
131. Oxide layer
133. Nitride layer
135. Oxide layer
140. Word line
160. 260, 460, 560 bit lines
160a bit line contact
161. Semiconductor layer
163. Barrier layer
165. Metal layer
167. Cover layer
170. 270, 370 spacer structure
171. A first material layer
171a cavity
171b first void layer
173. First spacer
175. A second material layer
175a cavity
175b second void layer
180. Plug-in connector
181. Storage node bonding pad
183. Patterning mask
185. Insulating layer
185a cavity
185b cavity
190. Supporting layer structure
191. A first supporting layer
192. An opening
193. A second supporting layer
195. Third supporting layer
197. Fourth supporting layer
210. Capacitor structure
210a capacitor
211. Bottom electrode layer
213. Capacitor dielectric layer
213a cavity
215. Top electrode layer
271a second spacer
271b second void layer
371. Second spacer
373. A first material layer
373a first gap layer
375. First spacer
377. A second material layer
377a second void layer
469. Protective layer
b1, b2 bottommost surfaces
D1 Direction of
h1, h2 height
Width t1, t2, t3
P1 etching manufacturing process
width w1, w2
Detailed Description
The following description of the preferred embodiments of the present invention will be presented to enable those skilled in the art to which the invention pertains and to further illustrate the invention and its advantages. Those of skill in the art will be able to make substitutions, rearrangements, and combinations of features from several different embodiments to accomplish other embodiments without departing from the spirit of the invention by referring to the following examples.
Referring to fig. 1 to 9, which are schematic views illustrating steps of a method for forming a semiconductor memory device 100 according to a first embodiment of the present invention, fig. 1 is a schematic top view of the semiconductor memory device 100 in a forming stage, and fig. 2 to 9 are schematic cross-sectional views of the semiconductor memory device 100 in the forming stage. The semiconductor memory device 100 of the present embodiment is, for example, a dynamic random access memory (dynamic random access memory, DRAM) device, which includes at least one transistor device (not shown) and at least one capacitor device (not shown) as the smallest component cell (memory cell) in the DRAM array and receives voltage information from the bit line 160 and the word line 140.
The semiconductor memory device 100 includes a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., siC, siGe, etc.), or a silicon-on-insulator (SOI) substrate, etc., at least one insulating region 101, such as a shallow trench isolation (shallow trench isolation, STI), is formed in the substrate 110, and a plurality of Active Areas (AA) 103 are defined on the substrate 110. In this embodiment, the active regions 103 extend in parallel to each other along the same direction D1, wherein the direction D1 is, for example, intersecting and not perpendicular to the y-direction or the x-direction, as shown in fig. 1, but not limited thereto. The insulating region 101 is formed, for example, by etching a plurality of trenches (not shown) in the substrate 110, and then filling an insulating material (such as silicon oxide or silicon oxynitride) into the trenches.
The substrate 110 may further have a plurality of buried gates (not shown) formed therein, for example, extending parallel to each other along the y-direction and crossing the active region 103, thereby forming a Buried Word Line (BWL) 140 of the semiconductor memory device 100. A plurality of bit lines 160 are formed on the substrate 110, for example, extending parallel to each other in the x-direction perpendicular to the buried word lines 140, so as to simultaneously cross the active regions 103 and the buried word lines 140 within the substrate 110. Bit lines 160 are formed on dielectric layer 130 of substrate 110, respectively, and each bit line 160 includes, for example, a semiconductor layer 161, a barrier layer 163, a metal layer 165, and a cap layer 167, which are stacked in sequence. A portion of the bit line 160 is further extended into the substrate 110 below to form a Bit Line Contact (BLC) 160a. In the present embodiment, the bit line contacts 160a are, for example, integrally formed with the semiconductor layer 161 of each bit line 160 and directly contact the substrate 110, as shown in fig. 2. On the other hand, in an embodiment, the dielectric layer 130 preferably has a composite layer structure, for example, but not limited to, an oxide-nitride-oxide (ONO) structure including an oxide layer 131-nitride layer 133-oxide layer 135.
As shown in fig. 2, a first material layer 171, a first spacer 173, and a second material layer 175 are sequentially formed on the sidewalls of each bit line 160. In one embodiment, the first material layer 171, the first spacers 173 and the second material layer 175 are formed by different deposition and etching processes, respectively, such that the first material layer 171, the first spacers 173 and the second material layer 175 can each have a long shape and respectively include different insulating materials. For example, a first material layer 171 may be formed by integrally depositing a silicon nitride material layer, a silicon carbon nitride material layer (not shown) or other low-k dielectric material layer (such as SiBCN or SiOCN) on the bit lines 160 and the substrate 110, covering the top surface, the sidewalls and the top surface of the dielectric layer 130 of each bit line 160, and performing an etching back process to partially remove the silicon nitride material layer or the silicon carbon nitride material layer to form the first material layer 171 (including silicon nitride or silicon carbon nitride material); then, a first spacer 173 is formed by integrally depositing a silicon oxide layer (not shown) to cover the top surface of each bit line 160, the spacers 171, and the top surface 110a of the substrate 110, and performing another etching back process to partially remove the silicon oxide layer to form the first spacers 173 (comprising silicon oxide); then, a second material layer 175 is formed by integrally depositing a silicon nitride material layer (not shown) on the bit lines 160 and the substrate 110, covering the top surface and the sidewalls of each bit line 160 and the top surface of the dielectric layer 130, and performing an etching back process to partially remove the silicon nitride material layer to form the second material layer 175 (including silicon nitride material), but not limited thereto. As such, the first material layer 171, the first spacers 173, and the second material layer 175 may have top surfaces that are flush with each other, as shown in fig. 2. In addition, before the first material layer 171 is formed, a patterning process of the dielectric layer 130 may be optionally performed, so that the subsequently formed first material layer 171, the first spacers 173 and the second material layer 175 may be directly formed on the top surface of the substrate 110. Then, the formation of the plurality of plugs 180 on the substrate 110 may be continued such that each plug 180 may be alternately disposed with each bit line 160 in the y-direction, and thus, the plugs 180 may form storage node plugs (storage node contact, SNC) of the semiconductor memory device 100 and directly contact the underlying substrate 110 (i.e., the active region 103) and/or the insulating region 101, as shown in fig. 2. In one embodiment, the plug 180 includes a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), but is not limited thereto. In this arrangement, the first material layer 171, the first spacers 173, and the second material layer 175 may be sequentially stacked between the plugs 180 and the bit lines 160 to electrically isolate the plugs 180 from each of the bit lines 160.
Next, as shown in fig. 3, a plurality of storage node pads (SN pads) 181 are formed on the plugs 180 and the bit lines 160 to contact the storage node plugs (i.e., plugs 180) below, respectively. The storage node pad 181 also includes a low resistance metal material such as aluminum, titanium, copper or tungsten, for example, but not limited to, a material different from the plug 180. In one embodiment, the storage node pad 181 is formed, for example, by forming a conductive material layer (including low-resistance metal such as aluminum, titanium, copper or tungsten) on the plug 180 and the bit line 160, forming a plurality of patterned masks 183 over the conductive material layer, and then performing an etching process through the patterned masks 183 to pattern the conductive material layer to form the storage node pad 181. It should be noted that, in the present embodiment, each storage node pad 181 only partially overlaps each plug 180 below, but not completely overlaps each plug 180, as shown in fig. 3, so that the space of the manufacturing process of the storage node pad 181 can be increased as much as possible while maintaining good electrical connection between the storage node pad 181 and the plug 180. Preferably, in another embodiment, the storage node pad and the plug 180 may be formed integrally and may comprise the same material, so that the storage node pad and the plug 180 may be formed simultaneously, but not limited thereto.
Then, as shown in fig. 4, the patterned mask 183 is completely removed, and then an etchant is introduced into the etching process P1 by using the storage node pad 181 as a blocking mask to completely remove the cap layer 167 (including silicon nitride material), the first material layer 171 (including silicon nitride or silicon carbonitride material) and the second material layer 175 (including silicon nitride material). Wherein the etchant preferably comprises hot phosphoric acid, but not limited thereto. Thus, after the etching process P1 is performed, each bit line 260 only remains the remaining metal layer 165, the barrier layer 163 and the semiconductor layer 161, and only the first spacer 173 is remained between the plug 180 and the bit line 260, such that the cavities 171a and 175a are formed between the first spacer 173 and the bit line 260, respectively.
As shown in fig. 5, an insulating layer 185 is formed over the plugs 180 and the bit lines 260, closing the cavities 171a, 175a on both sides of the first spacers 173, and forming a first void layer 171b and a second void layer 175b. It should be noted that the first void layer 171b is located between the first spacer 173 and the bit line 260, and has a relatively small height h1 above the substrate 110, and the second void layer 175b is located between the first spacer 173 and the plug 180, and has a relatively large height h2 above the substrate 110, in other words, the topmost surfaces of the first void layer 171b and the second void layer 175b are not equal in height, so that the second void layer 175b may directly contact the storage node pad 181, and the first void layer 171b may not directly contact the storage node pad 181, as shown in fig. 5. On the other hand, a portion of the first void layer 171b also extends downward on both sides of the bit line contact 160a, which extends into the substrate 110 and is located below the first spacer 173, and thus has a bottom-most surface b1 lower than the top surface of the substrate 110, such that the bottom-most surface b1 of the portion of the first void layer 171b is lower than the bottom-most surface b2 of the second void layer 175b, which are not equal in height, as shown in fig. 5. Moreover, since the first void layer 171b and the second void layer 175b are formed by the removed cavities 171a and 175a of the first material layer 171 and the second material layer 175, respectively, the first void layer 171b and the second void layer 175b may have substantially the same width t1 in the y direction, and the first void layer 171b of the portion (i.e., the portion located in the substrate 110) may have a larger width t3 (t 3 > t 1) and may directly contact the substrate 110 and the bottom surface of the first spacer 173. Thus, the first spacer layer 171b, the first spacer 173, and the second spacer 175b are sequentially stacked between the plug 180 and the bit line 260 to form the spacer structure 170. In addition, it should be noted that the insulating layer 185 is formed over the bit line 260, the spacer structure 170, the plug 180 and the storage node pad 181 in a conformal manner, so that the remaining space after the removal of the cap layer 167 can be partially filled with the space directly contacting the top surface of the metal layer 165, the sidewall of the first spacer 173 and the top surface of the second spacer 175b, and a half open cavity 185a is formed over the bit line 260 (the metal layer 165), wherein the width w1 of the bottom surface of the half open cavity 185a is larger than the width w2 of the bit line 260, as shown in fig. 5, but not limited thereto. In another embodiment, the requirement of the actual manufacturing process may be selected in sequence, so that the insulation layer completely fills the remaining space (not shown) after the cap layer 167 is removed, or the insulation layer 185 may also be formed to surround a closed cavity 185b above the bit line 260, as shown in fig. 6.
Subsequently, as shown in fig. 7, a capacitor structure 210 may also continue to be formed over the substrate 110 to directly contact and electrically connect to the underlying storage node pad 181. In one embodiment, the fabrication process of the capacitor structure 210 includes, but is not limited to, the following steps. First, a support layer structure 190, for example comprising at least one oxide layer and at least one nitride layer alternately stacked, is formed over the substrate 110. In the present embodiment, the support layer structure 190 includes, for example, a first support layer 191 (e.g., including silicon oxide), a second support layer 193 (e.g., including silicon nitride or silicon carbonitride), a third support layer 195 (e.g., including silicon oxide), and a fourth support layer 197 (e.g., including silicon nitride or silicon carbonitride, etc., but not limited thereto), which are sequentially stacked from bottom to top, wherein the first support layer 191 further fills the semi-open cavity 185a surrounded by the insulating layer 185, as shown in fig. 7, preferably, the first support layer 191 and the third support layer 195 may have a relatively large thickness, for example, about 5 times to 10 times or more than the other support layers (the second support layer 193 or the fourth support layer 197), but not limited thereto, the thickness of the support layer structure 190 may be about 1600 angstroms (angstroms) to about 2000 angstroms, but it should be understood by those skilled in the art that the specific stacking number of the oxide layers (e.g., the first support layer 191 or the third support layer 195) and the nitride layers (e.g., the second support layer 193 or the fourth support layer 197) is not limited to the foregoing, but may be adjusted according to practical requirements, such as 3 layers, 4 layers, or other numbers, etc., then, a plurality of openings 192 are formed in the support layer structure 190, sequentially penetrating the fourth support layer 197, the third support layer 195, the second support layer 193, and the first support layer 191, and being located on the underlying storage node pads 181, so that the insulating layers 185 covering the respective storage node pads 181 may be exposed from the respective openings 192, as shown in fig. 7.
As shown in fig. 8, the exposed insulating layer 185 is removed from the opening 192, and then a bottom electrode layer 211 is formed to entirely cover the top surface of the support layer structure 190 and the surface of the opening 192. The bottom electrode layer 211 is made of low-resistance metal such as aluminum, titanium, copper or tungsten, preferably titanium, but not limited thereto. Then, as shown in fig. 9, after the bottom electrode layer 211 is formed, an etching process is performed through a mask layer (not shown), so as to completely remove the oxide layer (such as the first supporting layer 191 or the third supporting layer 195) in the supporting layer structure 190, and further form the capacitor dielectric layer 213 and the top electrode layer 215 on the bottom electrode layer 211 in sequence, wherein the capacitor dielectric layer 213 and the top electrode layer 215 may be further filled between the remaining second supporting layer 193 and the fourth supporting layer 197, and between the remaining second supporting layer 193 and the insulating layer 185. It should be noted that the capacitor dielectric layer 213 may be further filled into the semi-open cavity 185a, and a closed cavity 213a is formed around the bit line 260, as shown in fig. 9, and the capacitor dielectric layer 213 filled into the semi-open cavity 185a may have a bottom surface lower than the bottom surface of the storage node pad 181. Thus, the manufacturing process of the capacitor structure 210 is completed, which includes the bottom electrode layer 211, the capacitor dielectric layer 213 and the top electrode layer 215 sequentially stacked, so as to form a plurality of vertically extending capacitors 210a, respectively corresponding to the storage node pads 181 located below, as the Storage Nodes (SN) of the semiconductor memory device 100. In one embodiment, the capacitor dielectric layer 213 comprises a high-k dielectric material selected from hafnium oxide (HfO) 2 ) Hafnium silicon oxide (HfSiO) 4 ) Hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO 2 ) Titanium oxide (TiO) 2 ) And zirconiA-Alumina-zirconia (ZAZ), preferably comprising zirconiA-Alumina-zirconia; the top electrode layer 215 is made of low-resistance metal such as aluminum, titanium, copper or tungsten, preferably titanium, but not soAnd (5) limiting.
According to the method of forming the semiconductor memory device 100 of the first embodiment of the present invention, the spacer structure 170 including the double-layered void layers 171b and 175b is formed by removing the first material layer 171 and the second material layer 175 formed between the bit line 160 and the storage node plug (i.e., plug 180) using the storage node pad 181 as a mask. Accordingly, the storage node is electrically connected to the transistor device in the substrate 110 through the storage node pad 181 and the storage node plug (i.e. plug 180), and the dual-layer void layers 171b and 175b of the spacer structure 170 can effectively improve the delay between the resistor and the capacitor, thereby improving the overall performance of the semiconductor memory device 100. In this embodiment, the top surfaces of the first void layer 171b and the second void layer 175b are not equal in height and have substantially the same width t1, so as to be disposed on two sides of the first spacer 173 respectively and further electrically isolate the bit line 160 and the storage node plug (i.e. plug 180).
In addition, it should be readily understood by those skilled in the art that other aspects of the present invention are possible in forming the semiconductor memory device and the method for forming the same, and are not limited to the foregoing, so as to meet the actual product requirements. For example, in another embodiment, the etching conditions of the etching process P1 may be further adjusted according to the actual product requirement to completely remove the cap layer 167 (including silicon nitride material) and the second material layer 175 (including silicon nitride material) with the same material, and partially remove the first material layer 171 (including silicon carbonitride material) with similar material. Thus, after the etching process P1 is performed, the cavity 175a after the second material layer 175 is removed may still form the second void layer 175b, the cavity (not shown) after the first material layer 171 is partially removed may form the first void layer 271b, and the remaining first material layer 171 may form the second void wall 271a (including silicon carbonitride material) between the first void layer 271b and the bit line 260, as shown in fig. 10. Alternatively, the first material layer may comprise a composite layer structure (not shown, for example, comprising a low-k dielectric material such as SICN, siBCN or SiOCN and a silicon oxide material stacked in sequence), and then the low-k dielectric material is at least partially or completely removed during the etching process P1 to form the first void layer, and the remaining silicon oxide material may form the second void. The topmost surfaces of the first void layer 271b (having a height h 1) and the second void layer 175b (having a height h 2) are also not equally high, and the first void layer 271b obviously has a relatively small thickness t2, and the second void layer 175b has a relatively large thickness t1. With this arrangement, the semiconductor memory device 200 of the present embodiment may also include the spacer structure 270 with the dual-layer spacer layers 271b and 175b, wherein the second spacer 271a (including silicon carbonitride), the first spacer 271b, the first spacer 173 and the second spacer 175b are sequentially stacked between the plug 180 and the bit line 260, so that the delay between the resistor and the capacitor can be effectively improved, and the overall performance of the semiconductor memory device 200 can be improved.
Further embodiments or variations of the semiconductor memory device and the method of forming the same in the present invention will be described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present invention are labeled with like reference numerals to facilitate cross-reference between the various embodiments.
Referring to fig. 11 to 12, a step diagram of a method for forming a semiconductor memory device 300 according to a second embodiment of the invention is shown. The steps for forming the semiconductor memory device 300 in this embodiment are substantially the same as those for forming the semiconductor memory device 100 in the first embodiment, and are not repeated here. The main difference between this embodiment and the first embodiment is that the spacer structure 370 of the semiconductor memory device 300 includes the second spacer 371, the first spacer 373a, the first spacer 375 and the second spacer 377a stacked in sequence.
In detail, referring to fig. 11, a second spacer 371, a first material layer 373, a first spacer 375 and a second material layer 377 are sequentially formed on the sidewalls of the bit line 160 (including the semiconductor layer 161, the barrier layer 163, the metal layer 165 and the cap layer 167 which are sequentially stacked), wherein the second spacer 371, the first material layer 373, the first spacer 375 and the second material layer 377 are formed by different deposition and etching processes, respectively, and may be elongated and include different insulating materials, respectively. In the present embodiment, the manufacturing process of the second spacer 371, the first material layer 373, the first spacer 375 and the second material layer 377 is substantially the same as that of the first material layer 171, the first spacer 173 and the second material layer 175 in the previous embodiment, preferably, the second spacer 371 may comprise silicon carbonitride material, the first material layer 373 and the second material layer 377 may comprise silicon nitride material, and the first spacer 375 may comprise silicon oxide material, but not limited thereto.
Thereafter, the steps may be sequentially performed as shown in fig. 3 to 5 in the previous embodiment, so as to form the spacer structure 370 including the dual-layer spacer 373a and 377a. As shown in fig. 12, the first void layer 373a and the second void layer 377a are disposed on two sides of the first spacer 375. It should be noted that the first void layer 373a is located between the first void 375 and the second void 371, and the first void 373a and the second void 371 have a relatively smaller height h1 above the substrate 110, and the second void 377a is located between the first void 375 and the plug 180, and has a relatively larger height h2 above the substrate 110, in other words, the top surfaces of the first void 373a and the second void 377a are also not equal in height, as shown in fig. 12. On the other hand, since the first void layer 373a and the second void layer 377a are formed by the cavities (not shown) of the first material layer 373 and the second material layer 377 after being removed, the first void layer 373a and the second void layer 377a may have substantially the same width t1 in the y direction.
Thus, the method of forming the semiconductor memory device 300 according to the second embodiment of the present invention can also form the spacer structure 370 including the dual-layer spacer 373a, 377a. Accordingly, the storage node is electrically connected to the transistor device in the substrate 110 through the storage node pad 181 and the storage node plug (i.e. plug 180), and the dual-layer void layers 373a, 377a of the spacer structure 370 can effectively improve the delay between the resistor and the capacitor, thereby improving the overall performance of the semiconductor memory device 300. In addition, in the present embodiment, the spacer structure 370 is formed by alternately stacking the dual-layer spacer layers 373a and 377a and the dual-layer spacers 371 and 375, which can further improve the structural support of the spacer structure 370 and protect the sidewall of the metal layer 165 from the etching process P1 after improving the delay problem between the resistor and the capacitor. Thus, the semiconductor memory device 300 can achieve both device performance and structural integrity.
Referring to fig. 13 to 14, schematic steps of a method for forming a semiconductor memory device 400 according to a third embodiment of the invention are shown. The steps for forming the semiconductor memory device 400 in this embodiment are substantially the same as those for forming the semiconductor memory device 100 in the first embodiment, and are not repeated here. The main difference between this embodiment and the first embodiment is that after the etching process P1 is performed, each bit line 560 includes, for example, the semiconductor layer 161, the barrier layer 163, the metal layer 165 and the protection layer 469 stacked in sequence.
In detail, referring to fig. 13, the bit line 460 further includes a protection layer 469 disposed between the metal layer 165 and the cap layer 167 to protect the metal layer 165. In an embodiment, the protection layer 469 includes the same material as the first material layer 171, such as silicon carbonitride, but is not limited thereto. Thereafter, the steps may be sequentially performed as shown in fig. 3 to 5 in the previous embodiment, to form the spacer structure 170 including the dual-layer void layers 171b and 175b. On the other hand, as shown in fig. 14, after the etching process P1 is performed, the cap layer 167 (including silicon nitride material) on top of the bit line 460 is completely removed, and only the protection layer 469 (including silicon carbonitride material), the metal layer 165, the barrier layer 163 and the semiconductor layer 161, which are sequentially stacked from top to bottom, remain to form the bit line 560.
Thus, the method of forming the semiconductor memory device 400 according to the third embodiment of the present invention can also form the spacer structure 170 including the dual-layer void layers 171b and 175b. Meanwhile, in the present embodiment, since the protection layer 469 is additionally disposed, the top surface of the metal layer 165 is protected from the etching process P1. Thus, the semiconductor memory device 400 can also achieve the advantages of device performance and structural integrity.
Referring to fig. 15, a schematic diagram of a semiconductor memory device 500 according to a fourth embodiment of the invention is shown. The semiconductor memory device 500 in this embodiment is substantially the same as the semiconductor memory device 300 in the second embodiment, and the description thereof is omitted herein. The main difference between this embodiment and the second embodiment is that after the etching process P1 is performed, each bit line 560 includes the semiconductor layer 161, the barrier layer 163, the metal layer 165 and the protection layer 469 sequentially stacked. The material of the protection layer 469 is preferably the same as that of the second spacer 371, for example, but not limited to, silicon carbonitride. In other words, the top surface and the sidewall of the metal layer 165 of the present embodiment are protected by the protection layer 469 and the second spacer 371, respectively, so as not to be affected by the etching process P1.
Thus, the semiconductor memory device 500 according to the fourth embodiment of the present invention also has the spacer structure 370 formed by alternately stacking the dual-layer spacer layers 373a and 377a and the dual-layer spacers 371 and 375, which can further improve the structural support of the spacer structure 370 after improving the problem of delay between the resistor and the capacitor. Meanwhile, the second spacer 371 and the protection layer 469 can protect the sidewall and the top surface of the metal layer 165 from the etching process P1, respectively. Thus, the semiconductor memory device 500 can provide advantages such as device performance and structural integrity.
In summary, the present invention uses the storage node pad as a mask to remove the material layer formed between the bit line and the storage node plug, thereby forming a spacer structure comprising a dual-layer void layer. Therefore, the storage node can be electrically connected with the transistor component in the substrate through the storage node bonding pad and the storage node plug, and the delay condition between the resistor and the capacitor is effectively improved through the double-layer gap layer of the gap wall structure, so that the overall performance of the semiconductor storage device is improved. In addition, the invention can form a spacer structure formed by alternately stacking double-layer spacer layers and double-layer spacers between the bit lines and the storage node plugs, thereby achieving the advantages of both device performance and structural integrity of the semiconductor memory device.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (17)
1. A semiconductor memory device, comprising:
a substrate;
a plurality of bit lines disposed on the substrate to be spaced apart from each other;
a plurality of plugs disposed on the substrate and alternately disposed with the bit lines; and
the spacer structure is arranged on the substrate and positioned between the bit line and the plug, wherein the spacer structure comprises a first gap layer, a first spacer and a second gap layer, and the first gap layer, the first spacer and the second gap layer are sequentially stacked between the side wall of the bit line and the plug;
a plurality of storage node pads disposed on the plugs and the bit lines and respectively contacting the plugs; the storage node bonding pads are partially overlapped with the plugs below and used as a blocking mask for etching a cover layer contacted with the storage node bonding pads and material layers at two sides of the first gap wall so as to form the first gap layer and the second gap layer; the first void layer does not directly contact the storage node pad;
wherein, the bottommost surface of the first void layer is not equal to the bottommost surface of the second void layer.
2. The semiconductor memory device according to claim 1, wherein the second void layer is in direct contact with the storage node pad.
3. The semiconductor memory device according to claim 1, further comprising:
the capacitors are arranged on the storage node bonding pad and are respectively opposite to the storage node bonding pad, each capacitor comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer which are sequentially stacked, wherein the bottommost surface of the capacitor dielectric layer is lower than the bottom surface of the storage node bonding pad.
4. The semiconductor memory device of claim 3, wherein a portion of the capacitor dielectric layer over the bit line surrounds a cavity.
5. The semiconductor memory device according to claim 1, further comprising:
the insulating layer is arranged on the bit line, the plug and the spacer structure, and a cavity is formed by surrounding a part of the insulating layer on the bit line.
6. The semiconductor memory device according to claim 5, wherein each of the bit lines includes a semiconductor layer, a barrier layer, and a metal layer stacked in this order, the insulating layer being in direct contact with the metal layer.
7. The semiconductor memory device according to claim 5, wherein a width of a bottom surface of the cavity is larger than a width of the bit line.
8. A method of forming a semiconductor memory device, comprising:
providing a substrate;
forming a plurality of bit lines on the substrate, the bit lines being disposed apart from each other;
forming a plurality of plugs on the substrate, wherein the bit lines and the plugs are alternately arranged; and
forming a spacer structure on the substrate and between the bit line and the plug, wherein the spacer structure comprises a first spacer layer, a first spacer and a second spacer layer, and the first spacer layer, the first spacer and the second spacer layer are sequentially stacked on the side wall of the bit line;
forming a plurality of storage node pads on the plugs and the bit lines, the storage node pads respectively contacting the plugs; the storage node bonding pads are partially overlapped with the plugs below and used as a blocking mask for etching a cover layer contacted with the storage node bonding pads and material layers at two sides of the first gap wall so as to form the first gap layer and the second gap layer; the first void layer does not directly contact the storage node pad;
wherein, the bottommost surface of the first void layer is not equal to the bottommost surface of the second void layer.
9. The method of claim 8, wherein the spacer structure further comprises a second spacer disposed between the first spacer and the bit line, the second spacer having a thickness less than a thickness of the first spacer.
10. The method of claim 8, wherein forming the spacer structure further comprises:
sequentially forming a first material layer, a first spacer and a second material layer on the side wall of the bit line;
removing the first material layer to form the first void layer; and
removing the second material layer forms the second void layer.
11. The method of claim 10, wherein the first material layer and the second material layer each comprise a same material, the material being different from the material of the first spacer.
12. The method of claim 9, wherein forming the spacer structure further comprises:
sequentially forming a first material layer, a first spacer and a second material layer on the side wall of the bit line;
partially removing the first material layer to form the second gap wall and the first gap layer; and
removing the second material layer forms the second void layer.
13. The method of claim 9, wherein the second spacer and the first spacer comprise different materials.
14. The method of claim 10, wherein the first material layer and the second material layer each comprise a different material.
15. The method of claim 14, wherein the first void layer and the second void layer are formed after the storage node pad is formed.
16. The method of forming a semiconductor memory device according to claim 14, further comprising:
and forming an insulating layer on the storage node bonding pad and the bit line, wherein a cavity is formed by the part of the insulating layer on the bit line.
17. The method of claim 9, wherein each bit line further comprises a passivation layer and a metal layer, the passivation layer is formed over the metal layer, and the passivation layer is made of a material similar to the material of the second spacer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111327962.4A CN113838852B (en) | 2021-11-10 | 2021-11-10 | Semiconductor memory device and method of forming the same |
| CN202311667336.9A CN117677189A (en) | 2021-11-10 | 2021-11-10 | Semiconductor memory device and method of forming the same |
| US17/573,597 US11930631B2 (en) | 2021-11-10 | 2022-01-11 | Semiconductor memory device and method of fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111327962.4A CN113838852B (en) | 2021-11-10 | 2021-11-10 | Semiconductor memory device and method of forming the same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311667336.9A Division CN117677189A (en) | 2021-11-10 | 2021-11-10 | Semiconductor memory device and method of forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113838852A CN113838852A (en) | 2021-12-24 |
| CN113838852B true CN113838852B (en) | 2024-01-23 |
Family
ID=78971061
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311667336.9A Pending CN117677189A (en) | 2021-11-10 | 2021-11-10 | Semiconductor memory device and method of forming the same |
| CN202111327962.4A Active CN113838852B (en) | 2021-11-10 | 2021-11-10 | Semiconductor memory device and method of forming the same |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311667336.9A Pending CN117677189A (en) | 2021-11-10 | 2021-11-10 | Semiconductor memory device and method of forming the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN117677189A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150137224A (en) * | 2014-05-28 | 2015-12-09 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap and method for fabricating the same |
| CN105280608A (en) * | 2014-07-25 | 2016-01-27 | 爱思开海力士有限公司 | Semiconductor device with air gaps and method for fabricating the same |
| US9356073B1 (en) * | 2015-01-19 | 2016-05-31 | SK Hynix Inc. | Semiconductor device including air gaps and method of fabricating the same |
| CN108346660A (en) * | 2017-01-24 | 2018-07-31 | 联华电子股份有限公司 | Semiconductor element and forming method thereof |
| CN110707083A (en) * | 2018-08-23 | 2020-01-17 | 联华电子股份有限公司 | Semiconductor memory device and method of forming the same |
| CN113437070A (en) * | 2021-07-09 | 2021-09-24 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102235120B1 (en) * | 2015-06-30 | 2021-04-02 | 삼성전자주식회사 | Semiconductor device and method for method for fabricating the same |
-
2021
- 2021-11-10 CN CN202311667336.9A patent/CN117677189A/en active Pending
- 2021-11-10 CN CN202111327962.4A patent/CN113838852B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150137224A (en) * | 2014-05-28 | 2015-12-09 | 에스케이하이닉스 주식회사 | Semiconductor device with air gap and method for fabricating the same |
| CN105280608A (en) * | 2014-07-25 | 2016-01-27 | 爱思开海力士有限公司 | Semiconductor device with air gaps and method for fabricating the same |
| US9356073B1 (en) * | 2015-01-19 | 2016-05-31 | SK Hynix Inc. | Semiconductor device including air gaps and method of fabricating the same |
| CN108346660A (en) * | 2017-01-24 | 2018-07-31 | 联华电子股份有限公司 | Semiconductor element and forming method thereof |
| CN110707083A (en) * | 2018-08-23 | 2020-01-17 | 联华电子股份有限公司 | Semiconductor memory device and method of forming the same |
| CN113437070A (en) * | 2021-07-09 | 2021-09-24 | 福建省晋华集成电路有限公司 | Semiconductor device and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117677189A (en) | 2024-03-08 |
| CN113838852A (en) | 2021-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2021109595A1 (en) | Memory and forming method therefor | |
| CN110061001B (en) | Semiconductor element and manufacturing method thereof | |
| US11765886B2 (en) | Semiconductor memory device | |
| US6977197B2 (en) | Semiconductor devices having DRAM cells and methods of fabricating the same | |
| CN114121962A (en) | Dynamic random access memory device and forming method thereof | |
| KR100439034B1 (en) | Bitline of semiconductor device with leakage current protection and method for forming the same | |
| WO2024012085A1 (en) | Semiconductor structure and preparation method for semiconductor structure | |
| US11910595B2 (en) | Semiconductor memory device | |
| CN215299254U (en) | Semiconductor device with a plurality of transistors | |
| CN113838852B (en) | Semiconductor memory device and method of forming the same | |
| US20210202371A1 (en) | Semiconductor device and method of fabricating the same | |
| CN216435901U (en) | Semiconductor memory device with a plurality of memory cells | |
| US11930631B2 (en) | Semiconductor memory device and method of fabricating the same | |
| CN218920890U (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| CN216563127U (en) | Semiconductor memory device with a plurality of memory cells | |
| CN219437502U (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| CN216818341U (en) | Semiconductor memory device with a plurality of memory cells | |
| CN215933602U (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN113793850B (en) | Semiconductor memory device and method of forming the same | |
| CN218941671U (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| CN113764419B (en) | Semiconductor device and method for forming the same | |
| CN215933603U (en) | Semiconductor memory device with a plurality of memory cells | |
| US12004340B2 (en) | Semiconductor memory device and method for forming the same | |
| CN113594098B (en) | Semiconductor device and method for manufacturing the same | |
| US20230171948A1 (en) | Semiconductor memory device and method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |