CN113836858A - Chip layout method - Google Patents
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- CN113836858A CN113836858A CN202111070232.0A CN202111070232A CN113836858A CN 113836858 A CN113836858 A CN 113836858A CN 202111070232 A CN202111070232 A CN 202111070232A CN 113836858 A CN113836858 A CN 113836858A
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- 238000013507 mapping Methods 0.000 claims abstract description 15
- 238000005457 optimization Methods 0.000 claims abstract description 5
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3947—Routing global
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a chip layout method, which comprises the steps of establishing a top-level coordinate system according to distribution planning of programmable logic device chip wiring resources; classifying all resources of the programmable logic device chip, and establishing a sub-coordinate system for each type of resources; establishing a mapping from the sub-coordinate system to the top coordinate system; coordinates of all resources in the sub-coordinate system are independent variables, density loss, line length loss and time sequence loss are objective functions, the relation and gradient of each objective function and the independent variables are calculated, and proper resource coordinates are obtained through optimization solution; the resources are placed to the corresponding coordinates. By the technical scheme, the invention ensures the convenience of the layout of the chip resources of the programmable logic device, facilitates the modeling in the global layout stage, accelerates the placement of the chip resources and improves the software performance.
Description
Technical Field
The invention belongs to the technical field of chips, relates to a layout technology of a programmable logic device chip integrated circuit software tool, and particularly relates to a chip layout method.
Background
In modern digital circuit design, the circuit design process is more and more complicated, and the programmable logic device chip simplifies the design process of the digital circuit due to the programmable function, so the digital circuit chip is widely applied.
The resources of the programmable logic device chip mainly include CLM resources, DRM resources, I/O resources, clock resources and the like, in the prior art, the resources are placed in a coordinate system for layout planning, because each type of resources has completely different distribution rules, the layout difficulty and the placement difficulty of the resources are increased when the layout is carried out in the same coordinate system, the design requirements of users cannot be met, and the software performance is limited.
Disclosure of Invention
The invention provides a chip layout method, which plans reasonable coordinates for different resources, provides convenience for resource layout, facilitates modeling in the global layout stage, accelerates the placement of resources and improves the software performance.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a chip layout method, which comprises the following steps:
establishing a top-level coordinate system according to the distribution planning of the programmable logic device chip wiring resources;
establishing a sub-coordinate system: dividing all resources of the programmable logic device chip into n classes, wherein n is a natural number, and establishing a sub-coordinate system for each class of resources;
further, the programmable logic device chip resources are classified, wherein the CLM resources are classified into one type, the DRM resources are classified into one type, the I/O resources are classified into one type, and the clock resources are classified into one type, so that a sub-coordinate system is established for each type of resources.
Establishing a mapping from the sub-coordinate system to the top coordinate system;
further, a mapping from the sub-coordinate system to the top coordinate system is established, i.e. a coordinate functional relationship between the sub-coordinate system and the top coordinate system is established.
And (3) carrying out global layout: coordinates of all resources in the sub-coordinate system are independent variables, density loss, line length loss and time sequence loss are objective functions, the relation and gradient of each objective function and the independent variables are calculated, and proper resource coordinates are obtained through optimization solution;
further, the relationship of the line length loss to the independent variable is:
c_wl＝f(g(x0))
wherein c _ wl represents the line length loss, f (g (x0)) represents the functional relation between the line length loss and the independent variable, x0 represents any independent variable in the calculation of the line length loss, and g (x0) represents the functional relation of the line length loss mapped from the sub-coordinate system to the top-level coordinate system.
Further, the gradient of the wire length loss is:
wherein,
the linear loss gradient is shown, x0 shows any independent variable in linear loss calculation, g (x0) shows the functional relation of linear loss from a sub coordinate system to a top coordinate system, g '(x 0) shows the derivative of a function g (x0), and f' (g (x0)) shows the derivative of a linear loss c _ wl function.
Further, the relationship of the timing loss to the argument is:
c_wl1＝f(g(x1))
where c _ wl1 represents the timing loss, f (g (x1)) represents the functional relationship between the timing loss and the argument, x1 represents any argument in the timing loss calculation, and g (x1) represents the functional relationship in the timing loss that maps from the child coordinate system to the top coordinate system.
Further, the gradient of the timing loss is:
wherein,
represents the time loss gradient, x1 represents any independent variable in time loss calculation, and g (x1) represents the secondary coordinate in line length lossIs a functional relationship mapped to the top coordinate system, g '(x 1) represents the derivative of the function g (x1), and f' (g (x1)) represents the derivative of the timing loss c _ wl1 function.
Resource placement is carried out: the resources are placed to the corresponding coordinates.
Further, in the resource placement process, when a resource is placed in the corresponding coordinate, after the proper coordinate of the resource is obtained through calculation, a target point is selected by using the sub-coordinate system corresponding to the resource, and the placement is tried from near to far from the target point until the placement is successful.
The invention has the beneficial effects that:
the invention provides a chip layout method, which comprises the steps of establishing a top-level coordinate system in a programmable logic device chip according to resource division, classifying all resources of the programmable logic device chip, establishing a sub-coordinate system according to the resources, and calculating top-level coordinates corresponding to the sub-coordinates of the resources through a function relation of mapping between the sub-coordinate system and the top-level coordinate system to obtain the most appropriate resource placement coordinate placement resources. The convenience and the rationality of resource layout are realized, the modeling in the global layout stage is facilitated, the placement of resources is accelerated, and the software performance is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a diagram of a mapping relationship between a sub-coordinate system and a top-level coordinate system;
FIG. 2 is a diagram of an acquisition method for x-coordinate mapping, using CLM resources as an example;
FIG. 3 is a resource placement diagram in different coordinate systems.
Detailed Description
A chip layout method according to an embodiment of the present invention is described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a chip layout method, which comprises the following specific scheme:
establishing a top-level coordinate system in a programmable logic device chip, and establishing the top-level coordinate system according to distribution planning of chip wiring resources in order to ensure the accuracy of line length and time sequence after resources are mapped to the top-level coordinate system;
establishing a sub-coordinate system: dividing all resources of a chip into n classes, wherein n is a natural number, and establishing a sub-coordinate system for each class of resources; in the scheme, the programmable logic device chip resources are classified, wherein the CLM resources are classified into one type, the DRM resources are classified into one type, the I/O resources are classified into one type, the clock resources are classified into one type, a sub-coordinate system is established for each type of resources, and the corresponding resources in each sub-coordinate system are closely arranged on the coordinate system.
Establishing a mapping from the sub-coordinate system to the top coordinate system; that is, a coordinate function relationship between the sub-coordinate system and the top-level coordinate system is established, for example, fig. 1 is a mapping relationship diagram of the sub-coordinate system and the top-level coordinate system, and the x coordinate and the y coordinate of the top-level coordinate system can be obtained after the x coordinate and the y coordinate of the sub-coordinate system are mapped.
Fig. 2 illustrates an example of CLM resources, and an x-coordinate mapping obtaining method, as shown in fig. 2, the CLM sub-coordinate system x0 includes sequential numbers 0, 1, 2, and 3, the top coordinate system x1 includes CLM resources and DRM resources, and has sequence numbers 0, 1, 2, 3, 4, and 5, the sequence number 0 of the sub-coordinate system x0 is mapped to the sequence number 0 of the top-level coordinate system x1, the sequence number 1 of the sub-coordinate system x0 is mapped to the sequence number 1 of the top-level coordinate system x1, the sequence number 2 of the sub-coordinate system x0 is mapped to the sequence number 3 of the top-level coordinate system x1, and the sequence number 3 of the sub-coordinate system x0 is mapped to the sequence number 5 of the top-level coordinate system x 1.
And (3) carrying out global layout: the coordinates of all resources in the sub-coordinate system are independent variables, the density loss, the line length loss and the time sequence loss are objective functions, the relation and the gradient of each objective function and the independent variable are calculated, the proper resource coordinates are obtained by using optimization solution, and the sub-coordinates and the top-level coordinates of the resources can be obtained because of the mapping function relation between the sub-coordinate system and the top-level coordinate system.
The calculation of the density loss and the calculation of the optimization solution are common techniques in the field, and are not described herein; only the calculation of the line length loss and the timing loss is described in detail below.
The wire length loss is calculated as follows:
setting the function relation between the top layer coordinate system and the sub-coordinate system of the line length loss as follows:
x10＝g(x0)
wherein x0 represents any one independent variable in the calculation of the line length loss, x10 represents the coordinate of the independent variable after the top coordinate system is mapped, and g (x0) represents the functional relation of the line length loss mapped from the sub coordinate system to the top coordinate system.
The top layer coordinate system truly reflects the line length, so the relationship between the line length loss and the top layer coordinate is
c_wl＝f(x10)
I.e. the relationship of the line length loss to the independent variable is
c_wl＝f(g(x0))
Wherein c _ wl represents the line length loss, f (g (x0)) represents the functional relation between the line length loss and the independent variable, x0 represents any independent variable in the calculation of the line length loss, and g (x0) represents the functional relation of the line length loss mapped from the sub-coordinate system to the top-level coordinate system.
Further, the gradient of the wire length loss is:
wherein,
represents the gradient of the line length loss, x0 represents any independent variable in the calculation of the line length loss, and g (x0) represents the sub-coordinate system in the line length lossMapping to the functional relationship of the top coordinate system, g '(x 0) represents the derivative of the function g (x0), and f' (g (x0)) represents the derivative of the line length loss c _ wl function.
The timing loss is calculated as follows:
setting the function relation between the time loss top-level coordinate system and the sub-coordinate system as follows:
x11＝g(x1)
where x1 represents any argument in the time loss calculation, x11 represents the coordinates of the argument after mapping in the top coordinate system, and g (x0) represents the functional relationship of the time loss mapping from the child coordinate system to the top coordinate system.
The top coordinate system truly reflects the timing, so the timing loss is related to the top coordinate
c_wl＝f(x11)
The relationship of chronological loss to the argument is:
c_wl1＝f(g(x1))
where c _ wl1 represents the timing loss, f (g (x1)) represents the functional relationship between the timing loss and the argument, x1 represents any argument in the timing loss calculation, and g (x1) represents the functional relationship in the timing loss that maps from the child coordinate system to the top coordinate system.
Further, the gradient of the timing loss is:
wherein,
the time loss gradient is shown, x1 represents any independent variable in time loss calculation, g (x1) represents a functional relation of line length loss from a sub coordinate system to a top coordinate system, g '(x 1) represents a derivative of a function g (x1), and f' (g (x1)) represents a derivative of a time loss c _ wl1 function.
And (3) carrying out resource placement treatment: placing the resources to corresponding coordinates, and after obtaining appropriate placing coordinates of the resources through calculation, placing the resources, wherein the placing of the resources is failed, in order to improve the success rate of the placing of the resources, the resources can be placed by using a corresponding sub-coordinate system, and under the appropriate coordinates of the resources, a target point is selected, and the placing is tried from near to far until the placing is successful.
Fig. 3 is a resource placement diagram in different coordinate systems, as shown in fig. 3, in the top coordinate system, there are both CLM resource placement points and DRM resource placement points, when a CLM resource is placed, the placement is interfered by the surrounding DRM resource placement points, and the placement efficiency is reduced.
The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the present invention is not to be considered as limited to these descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as the protection scope of the invention.
Claims (6)
1. A method for chip layout, comprising:
establishing a top-level coordinate system according to the distribution planning of the programmable logic device chip wiring resources;
establishing a sub-coordinate system: dividing all resources of the programmable logic device chip into n classes, wherein n is a natural number, and establishing a sub-coordinate system for each class of resources;
establishing a mapping from the sub-coordinate system to the top coordinate system;
and (3) carrying out global layout: coordinates of all resources in the sub-coordinate system are independent variables, density loss, line length loss and time sequence loss are objective functions, the relation and gradient of each objective function and the independent variables are calculated, and proper resource coordinates are obtained through optimization solution;
resource placement is carried out: the resources are placed to the corresponding coordinates.
2. The chip layout method according to claim 1, wherein in the step of establishing the sub-coordinate system, the programmable logic device chip resources are classified, wherein the CLM resources are of one type, the DRM resources are of one type, the I/O resources are of one type, and the clock resources are of one type, and a sub-coordinate system is established for each type of resources.
3. The chip layout method according to claim 1, wherein the mapping from the sub-coordinate system to the top-level coordinate system is established, i.e. a coordinate function relationship between the sub-coordinate system and the top-level coordinate system is established.
4. The chip layout method according to claim 1, wherein in the performing global layout step,
the relationship of the line length loss to the independent variable is:
c_wl＝f(g(x0))
wherein c _ wl represents the line length loss, f (g (x0)) represents the functional relation between the line length loss and the independent variable, x0 represents any independent variable in the calculation of the line length loss, and g (x0) represents the functional relation of the line length loss mapped from the sub-coordinate system to the top-level coordinate system;
the gradient of the line length loss is:
wherein,
the linear loss gradient is shown, x0 shows any independent variable in linear loss calculation, g (x0) shows the functional relation of linear loss from a sub coordinate system to a top coordinate system, g '(x 0) shows the derivative of a function g (x0), and f' (g (x0)) shows the derivative of a linear loss c _ wl function.
5. The chip layout method according to claim 1, wherein in the performing global layout step,
the relationship of the timing loss to the argument is:
c_wl1＝f(g(x1))
wherein c _ wl1 represents the timing loss, f (g (x1)) represents the functional relationship between the timing loss and the independent variable, x1 represents any independent variable in the calculation of the timing loss, and g (x1) represents the functional relationship of the mapping from the sub-coordinate system to the top-level coordinate system in the timing loss;
the gradient of the timing loss is
Wherein,
the time loss gradient is shown, x1 represents any independent variable in time loss calculation, g (x1) represents a functional relation of line length loss from a sub coordinate system to a top coordinate system, g '(x 1) represents a derivative of a function g (x1), and f' (g (x1)) represents a derivative of a time loss c _ wl1 function.
6. The chip layout method according to claim 1, wherein the step of performing resource placement specifically comprises:
when a resource is placed in the corresponding coordinate, after the proper coordinate of the resource is obtained through calculation, a target point is selected by using the sub-coordinate system corresponding to the resource, and the placing is tried from near to far from the target point until the placing is successful.
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| CN202111070232.0A CN113836858B (en) | 2021-09-13 | Chip layout method |
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| CN202111070232.0A CN113836858B (en) | 2021-09-13 | Chip layout method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114781300A (en) * | 2022-06-21 | 2022-07-22 | 上海国微思尔芯技术股份有限公司 | Editable logic array wiring method, device, equipment and storage medium |
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