CN113823622A - Chip packaging device and electronic equipment - Google Patents
Chip packaging device and electronic equipment Download PDFInfo
- Publication number
- CN113823622A CN113823622A CN202010562083.9A CN202010562083A CN113823622A CN 113823622 A CN113823622 A CN 113823622A CN 202010562083 A CN202010562083 A CN 202010562083A CN 113823622 A CN113823622 A CN 113823622A
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- bonding layer
- adhesive
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The application provides a chip package device and electronic equipment, relates to chip package technical field, can improve chip package structure's EMI shielding effect. The chip packaging device comprises a substrate and a chip arranged on the substrate; the chip packaging device also comprises a solder mask layer and a packaging structure; the packaging structure is connected with the substrate in the area around the chip through the first bonding layer; the solder mask is positioned on the surface of one side of the substrate, which is provided with the chip, and a hollow area is arranged in the connection area of the packaging structure and the substrate; the first bonding layer adopts conductive adhesive; or the first adhesive layer is made of non-conductive adhesive with dielectric constant greater than or equal to 7 and loss factor greater than or equal to 0.02.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to a chip packaging device and electronic equipment.
Background
In the chip package structure, a chip (die) may generate electromagnetic interference (EMI), and if the chip (die) is not shielded from the EMI, various EMI problems and a problem of excessive Radiation Emission (RE) test of a product may be caused. Especially, as the integration level and the speed of the chip are increased year by year, the external radiation of the chip is increased, so that the improvement of the EMI shielding effect on the chip also becomes a hot spot of current concern.
Disclosure of Invention
The application provides a chip packaging device and electronic equipment, which can improve the shielding effect of a chip packaging structure on EMI.
The application provides a chip packaging device, which comprises a substrate and a chip arranged on the substrate; the chip packaging device also comprises a solder mask layer and a packaging structure; the packaging structure is connected with the substrate in the area around the chip through a first bonding layer; the solder mask is positioned on the surface of one side of the substrate, which is provided with the chip, and a hollow area is formed in the connection area of the packaging structure and the substrate by the solder mask; the first bonding layer adopts conductive adhesive; or the first adhesive layer is made of non-conductive glue with a dielectric constant larger than or equal to 7 and a loss factor larger than or equal to 0.02.
In the chip packaging device, on one hand, the solder resist of the low DK material is partially or completely removed in the connection area of the packaging structure and the substrate by windowing (i.e. arranging the hollow area) in the solder resist layer; on the other hand, non-conductive adhesive (DK is more than or equal to 7, DF is more than or equal to 0.02) is adopted between the packaging structure and the substrate, so that the coupling plane capacitance density between the packaging structure and the substrate can be greatly improved, the connection impedance between the packaging structure and the substrate is reduced, and the cavity resonance is inhibited; or the packaging structure is directly connected to the substrate in a conductive adhesive mode to form a shielding cavity; thereby, the cavity shielding effect between the packaging structure and the substrate is improved, and the problems of electromagnetic interference and the like are effectively solved.
In some possible implementations, the chip package device further includes a heat spreader device; the packaging structure comprises a chip packaging cover; the chip packaging cover is connected with the substrate in the area around the chip through the first bonding layer, and the first bonding layer is non-conductive glue with a dielectric constant larger than or equal to 7 and a loss factor larger than or equal to 0.02; the chip packaging cover is connected with the surface of one side, away from the substrate, of the chip through first heat-conducting glue; and the heat dissipation device is connected with the surface of one side of the chip packaging cover, which is far away from the chip, through second heat conduction glue.
In this case, by windowing (i.e., providing a hollow-out region) in a connection region where the solder resist layer is located between the chip package cover and the substrate, a part or all of the solder resist of the low DK material located in the connection region is removed; non-conductive adhesive (DK is more than or equal to 7, DF is more than or equal to 0.02) is adopted between the chip packaging cover and the substrate, so that the coupling plane capacitance density between the chip packaging cover and the substrate can be greatly improved, the connection impedance between the chip packaging cover and the substrate is reduced, and the cavity resonance is inhibited; or the chip packaging cover is directly connected to the substrate in a conductive adhesive mode to form a shielding cavity; thereby, the cavity shielding effect between the chip packaging cover and the substrate is improved, and the problems of electromagnetic interference and the like are effectively solved.
In some possible implementations, the chip package device further includes a heat spreader device; the packaging structure comprises a chip packaging ring; the chip packaging ring is connected with the substrate in the area around the chip through the first bonding layer; the heat dissipation device is connected with the surface of one side, away from the substrate, of the chip through a third heat conduction adhesive, and the heat dissipation device is connected with the surface of one side, away from the substrate, of the chip packaging ring through a second bonding layer; the second bonding layer adopts conductive adhesive; or the second adhesive layer is made of non-conductive glue with the dielectric constant being greater than or equal to 7 and the loss factor being greater than or equal to 0.02.
In this case, by windowing (i.e., providing a hollow area) in a connection area where the solder resist layer is located between the chip package ring and the substrate, a part or all of the solder resist of the low DK material located in the connection area is removed; and non-conductive adhesive (DK is more than or equal to 7, DF is more than or equal to 0.02) is adopted between the chip package and the substrate and between the chip package and the heat dissipation device, so that the connection impedance between the heat dissipation device and the substrate is reduced, the cavity shielding effect between the heat dissipation device and the substrate is improved, and the problems of electromagnetic interference and the like are effectively solved.
In some possible implementation manners, the first adhesive layer and the second adhesive layer both use conductive glue; the low-impedance grounding connection between the heat dissipation device and the chip packaging ring to the substrate can be guaranteed, a relatively finished shielding cavity is formed, and the cavity shielding effect between the chip packaging ring and the substrate is improved to the greatest extent.
In some possible implementation manners, the first adhesive layer and the second adhesive layer both adopt non-conductive glue with dielectric constant greater than or equal to 7 and loss factor greater than or equal to 0.02; on one hand, the coupling plane capacitance density between the chip packaging ring and the substrate can be greatly improved, the connection impedance between the chip packaging ring and the substrate is reduced, cavity resonance is inhibited, and the cavity shielding effect between the chip packaging ring and the substrate is further improved; on the other hand, compared with the situation that the shielding effect is reduced due to the fact that the conductive adhesive is prone to cracking, layering, electrochemical corrosion and the like caused by aging in the long-time use process, the stability of the shielding effect between the chip packaging ring and the substrate can be effectively guaranteed by the aid of the non-conductive adhesive.
In some possible implementations, forming the second tie layer is elastic; so as to absorb the tolerance generated in the thickness direction (i.e. the thickness direction of the chip packaging device) during the bonding process of the heat sink device and the chip packaging ring through the second bonding layer.
In some possible implementations, the second adhesive layer includes a flexible material therein.
In some possible implementations, an elastic member is disposed in the second adhesive layer.
In some possible implementations, the first bonding layer has a thickness of less than or equal to 0.1 mm. Under the condition, the coupling plane capacitance density between the chip packaging structure and the substrate can be further improved, so that the plane parasitic inductance between the chip packaging structure and the substrate is reduced, the connection impedance is reduced, and the improvement of the cavity shielding effect between the chip packaging structure and the substrate is further facilitated.
In some possible implementations, the conductive paste used in the first adhesive layer includes at least one of conductive silver paste, nickel-carbon paste, and silver-copper paste.
In some possible implementations, the non-conductive adhesive used in the first adhesive layer includes at least one of silicone-based and epoxy-based non-conductive adhesives filled with a high dielectric constant material.
In some possible implementations, the conductive adhesive used in the second adhesive layer includes at least one of conductive foam and conductive silicone rubber.
In some possible implementation manners, the non-conductive adhesive used in the second bonding layer includes at least one of a foaming-type non-conductive adhesive and a rubber-type non-conductive adhesive filled with a high dielectric constant absorbing powder.
In some possible implementations, the first bonding layer is a closed loop bonding pattern.
In some possible implementation manners, the first adhesive layer is formed by arranging a plurality of adhesive patterns at intervals, and the distance between two adjacent adhesive patterns is less than or equal to one tenth of the minimum wavelength of the electromagnetic wave in the shielding frequency band; so as to avoid the gap field leakage between two adjacent bonding patterns.
In some possible implementations, the hollowed-out area is a continuous annular hollowed-out pattern.
In some possible implementation manners, the hollowed-out area comprises a plurality of hollowed-out patterns arranged at intervals.
Embodiments of the present application further provide an electronic device, which includes a printed circuit board and a chip-packaging device as in any one of the foregoing possible implementation manners, where the chip-packaging device is connected to the printed circuit board.
Drawings
Fig. 1 is a schematic structural diagram of a chip package device according to an embodiment of the present disclosure;
FIG. 2 is a cross-sectional schematic view of the chip-packaged device of FIG. 1;
fig. 3 is a schematic structural diagram of a solder mask layer in a chip package device according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a solder mask layer in a chip package device according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a chip package device according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a chip package device according to an embodiment of the present disclosure;
fig. 7 is a top view of the chip package device shown in fig. 6;
fig. 8 is a schematic structural diagram of a chip package device according to an embodiment of the present disclosure.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description examples and claims of this application and in the drawings are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor order. Furthermore, the terms "comprises" and "comprising," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a list of steps or elements.
The embodiment of the application provides electronic equipment. The electronic equipment can be electronic products such as a mobile phone, a tablet computer, a notebook computer, a vehicle-mounted computer, an intelligent watch, an intelligent bracelet and the like. The embodiment of the present application does not specifically limit the specific form of the electronic device.
The electronic device includes a Printed Circuit Board (PCB) and a chip package device connected to the PCB.
The chip packaging device provided by the embodiment of the application has a high EMI shielding effect, and can effectively solve various electromagnetic interference problems; the specific arrangement structure of the chip package device provided by the embodiment of the present application is further described below.
For a chip package device, the package method can be divided into two types: one is a package method using a chip package cover (lid) (i.e., a lid package method); the other is to shorten the heat conduction path and reduce the thermal resistance, and a packaging mode (i.e. a lidless packaging mode) without a chip packaging cover is adopted; the following describes a chip-packaged device in two packaging modes by specific examples.
Example one
The present embodiment provides a chip package device, which adopts a lid package manner, as shown in fig. 1 and fig. 2 (a schematic cross-sectional view of fig. 1), the chip package device includes a substrate 1 and a chip 2 disposed on the substrate 1. It is understood that the chip 2 and the substrate 1 may be connected by flip chip bonding, and certainly, may also be connected by wire bonding, which is not limited in the present application, and fig. 2 is only schematically illustrated by taking the flip chip connection between the chip 2 and the substrate 1 as an example.
On the basis, as shown in fig. 2, the chip package device further includes a chip package cover (lid)4 (i.e., a package structure, which is mostly made of a metal material). The chip package cover 4 is connected to the upper surface of the chip 2 (i.e., the surface facing away from the substrate 1) by a first thermally conductive adhesive 61, and the chip package cover 4 is connected to the substrate 1 by a first adhesive layer 51 in the area around the chip 2, where the first adhesive may be a conductive adhesive, or a non-conductive adhesive with a dielectric constant (DK) greater than or equal to 7 and a Dissipation Factor (DF) greater than or equal to 0.02; the non-conductive adhesive referred to hereinafter is a non-conductive adhesive satisfying DK not less than 7 and DF not less than 0.02.
Further, the substrate 1 is provided with a solder resist layer 3 on a surface on a side where the chip is provided, and the solder resist layer 3 is provided with a hollow area 31 in a connection area of the chip package cover 4 and the substrate 1 (refer to fig. 4 and 5). The solder resist layer 3 may be a green oil solder resist layer, but is not limited thereto, and may be a solder resist layer of another color or the like.
It is understood that the solder resist layer 3 is generally made of a low dielectric constant (DK) material (e.g., acrylic oligomer) which is coated as a protective layer on the upper surface of the substrate 1 in the area where soldering is not required to function as a protection of the substrate. Because the solder mask 3 adopts low DK material to can make the coupling plane capacitance density between chip package lid 4 and the base plate 1 reduce, and then make chip package lid 4 and base plate 1's impedance of being connected higher, lead to the not high problem of shielding efficiency to EMI.
For the conductive adhesive used between the chip package cover 4 and the substrate 1, since the connection impedance of the conductive adhesive itself is very small and the conductive adhesive is generally doped with a large proportion of metal conductive particles, an effective shielding cavity can be formed between the chip package cover 4 and the substrate 1.
For the non-conductive adhesive (DK is more than or equal to 7, DF is more than or equal to 0.02) between the chip packaging cover 4 and the substrate 1, the coupling plane capacitance density between the chip packaging cover and the substrate can be greatly improved, the connection impedance between the chip packaging cover and the substrate is reduced, part of harmonic waves generated in the cavity can be absorbed to inhibit the cavity resonance, and the cavity shielding effect between the chip packaging cover and the substrate is further improved.
In summary, in the chip package device provided in this embodiment, on one hand, a window is opened (i.e., a hollow area is disposed) in a connection area where the solder resist layer is located between the chip package cover and the substrate, so as to remove a part or all of the solder resist layer of the low DK material located in the connection area; on the other hand, non-conductive adhesive (DK is more than or equal to 7, DF is more than or equal to 0.02) is adopted between the chip packaging cover and the substrate, so that the coupling plane capacitance density between the chip packaging cover and the substrate can be greatly improved, the connection impedance between the chip packaging cover and the substrate is reduced, and cavity resonance is inhibited; or the chip packaging cover is directly connected to the substrate in a conductive adhesive mode to form a shielding cavity; thereby, the cavity shielding effect between the chip packaging cover and the substrate is improved, and the problems of electromagnetic interference and the like are effectively solved.
As shown in fig. 3, in some of the chip package devices provided in this embodiment, a heat dissipation device 7 may be further provided, and the heat dissipation device 7 is connected to the upper surface (i.e., the surface facing away from the substrate 1) of the chip package cover 4 through a second thermal conductive adhesive 62, so that the heat dissipated by the chip 2 can be transferred to the chip package cover 4 through the first thermal conductive adhesive 61, and then transferred from the chip package cover 4 to the heat dissipation device 7 through the second thermal conductive adhesive 62 for heat dissipation.
The components of the first heat-conducting glue 61 and the second heat-conducting glue 62 may be the same or different, and the application does not specifically limit this, and the arrangement may be selected according to the needs. Illustratively, the first thermal conductive paste 61 and the second thermal conductive paste 62 may both be interface thermal material (TIM).
It should be noted that, in this embodiment, the specific shape of the hollow-out area 31 on the solder resist layer 3 is not changed; for example, as shown in fig. 4, in some possible implementations, the hollow-out area 31 may be a continuous annular hollow-out pattern, that is, the solder mask layer 3 is provided with a ring of continuous annular hollow-out pattern in a connection region located around the chip 2 along the chip package cover 4 and the substrate 1. For another example, as shown in fig. 5, in some possible implementations, the hollow-out area 31 may include a plurality of hollow-out patterns arranged at intervals; namely, a plurality of hollow patterns are dispersedly arranged at intervals along the connection region of the chip packaging cover 4 and the substrate 1 around the chip 2; of course, the shape of the hollow pattern can be selected and set according to actual requirements, which is not limited in this application, and the hollow pattern can be, for example, a circle, a square, or the like.
In addition, in the present embodiment, the specific composition of the non-conductive adhesive or the conductive adhesive used for the first adhesive layer 51 is not limited.
For example, in some possible implementations, the conductive paste used in the first adhesive layer 51 may be at least one of conductive silver paste, nickel-carbon paste, and silver-copper paste.
Illustratively, in some embodiments, the first adhesive layer 51 may be made of conductive silver paste; in some embodiments, the first adhesive layer 51 may also be silver copper paste; in some embodiments, the first adhesive layer 5 may also use a mixture of nickel carbon glue and silver copper glue.
For another example, in some possible implementations, the non-conductive adhesive used for the first adhesive layer 51 may be at least one of silicone-based and epoxy-based non-conductive adhesives filled with a high DK material.
Illustratively, in some embodiments, the first adhesive layer 51 may employ a silicone-based nonconductive adhesive filled with a high DK material; in some embodiments, the first adhesive layer 51 may employ an epoxy-based non-conductive adhesive filled with a high DK material; in some embodiments, the first adhesive layer 51 may employ a mixture of a silicone-based nonconductive adhesive filled with a high DK material and an epoxy-based nonconductive adhesive filled with a high DK material.
The first adhesive layer 51 will be described below by taking as an example a case where the first adhesive layer 51 is made of a non-conductive adhesive.
In some possible implementations, the thickness of the first adhesive layer 51 may be set to be less than or equal to 0.1mm (i.e. less than or equal to 0.1mm) on the premise of ensuring the adhesive effect between the chip package cover and the substrate; that is to say, adopt the non-conductive glue to form thinner tie coat between chip package lid and base plate, coupling plane capacitance density between promotion chip package lid and the base plate that can be further to make the parasitic inductance in plane between chip package lid and the base plate increase, connection impedance reduces, and then more be favorable to the promotion of cavity shielding effect between chip package lid and the base plate.
In addition, the shape of the first adhesive layer 51 is not limited to a large amount in this embodiment, and may be set as needed in practice.
For example, in some possible implementations, the first adhesive layer 51 may be a closed loop adhesive pattern; that is, a closed continuous loop of the bonding pattern is provided at the connection region around the chip 2 along the chip package cover 4 and the substrate 1.
For another example, in some possible implementations, the first adhesive layer 51 may be provided with a plurality of adhesive patterns for intervals; that is, a plurality of bonding patterns are arranged at intervals in a connection region around the chip 2 along the chip package cover 4 and the substrate 1.
In this case, in order to prevent the gap field leakage between two adjacent bonding patterns as much as possible, in some embodiments, a distance between any two adjacent bonding patterns among the plurality of bonding patterns arranged at intervals of the first bonding layer 51 may be formed to be less than or equal to one tenth of the minimum wavelength of the electromagnetic wave of the shielding frequency band.
Example two
The present embodiment provides a chip package device, as shown in fig. 6 and fig. 7 (top view of fig. 6), which adopts a lidless package manner (i.e., a package manner adopting a window), and includes a substrate 1 and a chip 2 disposed on the substrate 1. It is understood that the chip 2 and the substrate 1 may be connected by flip chip bonding, and certainly, may also be connected by wire bonding, which is not limited in the present application, and fig. 6 is only schematically illustrated by taking the flip chip connection between the chip 2 and the substrate 1 as an example.
On this basis, as shown in fig. 6 and 7, the chip package device includes a chip package ring (ring) R (i.e., a package structure, which is mostly made of a metal material); the chip packaging ring R is connected with the substrate 1 in the area around the chip 2 through a first bonding layer 51, and the first bonding layer 51 can adopt conductive adhesive or non-conductive adhesive (DK is more than or equal to 7, DF is more than or equal to 0.02).
As shown in fig. 6, the substrate 1 is provided with a solder resist layer 3 on the surface on the side where the chip 2 is provided, and the solder resist layer 3 is provided with a hollow area 31 in a connection region of the chip package ring R and the substrate 1 (see fig. 4 and 5). The solder resist layer 3 may be a green oil solder resist layer, but is not limited thereto, and may be a solder resist layer of another color or the like.
It will be appreciated here that the solder mask 3 is typically made of a low DK material (e.g., acrylic oligomer) that is applied as a protective layer to the upper surface of the substrate 1 in areas that are not required to be soldered to the chip 2 to function as a protective layer for the substrate. Because the solder mask layer 3 adopts a low DK material, the coupling plane capacitance density between the chip packaging ring R and the substrate 1 is reduced, so that the connection impedance between the chip packaging ring R and the substrate 1 is higher, and the problem of low EMI shielding efficiency is caused.
In this case, it can be understood that, by windowing (i.e., setting a hollow area) in the connection area where the solder mask is located between the chip packaging ring and the substrate, and removing part or all of the solder mask of the low DK material located in the connection area, the problem of poor cavity shielding efficiency caused by low capacitance density of the coupling plane between the chip packaging ring and the substrate and large connection impedance due to the solder mask in the connection area between the chip packaging ring and the substrate can be avoided.
In addition, as shown in fig. 8, in the lidless packaging manner, the chip packaging device further includes a heat dissipation device 7, the heat dissipation device 7 is connected to the upper surface (i.e., the surface facing away from the substrate 1) of the chip 2 through a third thermal conductive paste 63 (for example, a TIM may be used), and the heat dissipation device 7 is connected to the upper surface (i.e., the surface facing away from the substrate 1) of the chip packaging ring R through a second adhesive layer 52; the second adhesive layer 52 may be made of a conductive adhesive or a nonconductive adhesive (DK not less than 7 and DF not less than 0.02).
In this case, in the chip package device, the heat emitted from the chip 2 is directly transferred to the heat sink device 7 through the third heat conductive paste 63 to be dissipated; compared with the lid packaging mode adopted in the first embodiment, the heat dissipation path is reduced, the thermal resistance is reduced, and therefore heat dissipation is facilitated; the method is particularly suitable for chip packaging devices with high power, large size and high integration level.
In the present embodiment, the first adhesive layer 51 may be one of a conductive adhesive and a non-conductive adhesive, and the second adhesive layer 52 may also be one of a conductive adhesive and a non-conductive adhesive; the present embodiment is not particularly limited with respect to the type of the adhesive used for the first adhesive layer 51 and the second adhesive layer 52, and may be selected and arranged as needed in practice.
For example, the first adhesive layer 51 and the second adhesive layer 52 may both use conductive adhesives, and both use the same conductive adhesive or use different conductive adhesives, which is not limited in this embodiment; for another example, the first adhesive layer 51 and the second adhesive layer 52 may both use non-conductive adhesive, and both may use the same non-conductive adhesive or different non-conductive adhesives, which is not limited in this embodiment; for another example, one of the first adhesive layer 51 and the second adhesive layer 52 is made of a conductive adhesive, and the other is made of a non-conductive adhesive.
In some possible implementation manners, the first bonding layer 51 and the second bonding layer 52 may both be made of conductive adhesive, so as to ensure that the heat dissipation device 7 and the chip package ring R are connected to the substrate 1 in a low-impedance manner, and to form a relatively complete shielding cavity, thereby improving the cavity shielding effect between the chip package ring and the substrate to the maximum extent.
In some possible implementations, the first adhesive layer 51 and the second adhesive layer 52 may be both made of non-conductive adhesive; on one hand, the coupling plane capacitance density between the chip packaging ring and the substrate can be greatly improved, the connection impedance between the chip packaging ring and the substrate is reduced, cavity resonance is inhibited, and the cavity shielding effect between the chip packaging ring and the substrate is further improved; on the other hand, compared with the situation that the shielding effect is reduced due to the fact that the conductive adhesive is prone to cracking, layering, electrochemical corrosion and the like caused by aging in the long-time use process, the stability of the shielding effect between the chip packaging ring and the substrate can be effectively guaranteed by the aid of the non-conductive adhesive.
In summary, in the chip package device provided in this embodiment, on one hand, a window is opened (i.e., a hollow area is disposed) in a connection area where the solder resist layer is located between the chip package ring and the substrate, so as to remove a part or all of the solder resist layer of the low DK material located in the connection area; on the other hand, non-conductive adhesive (DK is more than or equal to 7, DF is more than or equal to 0.02) or conductive adhesive is adopted between the chip package and the substrate and between the chip package and the heat dissipation device, so that the connection impedance between the heat dissipation device and the substrate is reduced, the cavity shielding effect between the heat dissipation device and the substrate is improved, and the problems of electromagnetic interference and the like are effectively solved.
Note that, in this embodiment, the specific shape of the hollow area 31 on the solder resist layer 3 is not described. The hollow-out area 31 may be a continuous annular hollow-out pattern, or may be a plurality of hollow-out patterns arranged at intervals; specifically, reference may be made to fig. 3 and fig. 4 and the related description in the first embodiment, which are not repeated herein.
In addition, in the present embodiment, the specific composition of the non-conductive adhesive or the conductive adhesive used for the first adhesive layer 51 is not limited. For example, in some possible implementations, the first adhesive layer 51 may employ one or more of conductive silver paste, nickel carbon paste, silver copper paste; as another example, in some possible implementations, the first adhesive layer 51 may employ a silicone-based, epoxy-based nonconductive adhesive filled with a high DK material; reference may be specifically made to the related description in the first embodiment, and details are not described herein again.
Taking the first adhesive layer 51 made of non-conductive adhesive as an example, in some possible implementations, the thickness of the first adhesive layer 51 may be set to be less than or equal to 0.1mm (i.e., less than or equal to 0.1 mm); also adopt high DK material to form thinner tie coat between chip package ring and base plate, can further promote the coupling plane capacitance density between chip package ring and the base plate to make the parasitic inductance in plane between chip package ring and the base plate reduce, connect the impedance and reduce, and then more be favorable to the promotion of cavity shielding effect between chip package ring and the base plate.
In addition, the shape of the first adhesive layer 51 is not limited to a large amount, and may be set as needed. For example, in some possible implementations, the first adhesive layer 51 may be a closed loop adhesive pattern. For another example, in some possible implementations, the first adhesive layer 51 may be provided with a plurality of adhesive patterns for intervals; in this case, of course, in order to avoid the gap field leakage between two adjacent bonding patterns as much as possible, in some embodiments, a plurality of bonding patterns may be formed at intervals, and the distance between any two adjacent bonding patterns may be less than or equal to one tenth of the minimum wavelength of the electromagnetic wave in the shielding frequency band. Reference may be specifically made to the related description in the first embodiment, and details are not described herein again.
The specific arrangement of the second adhesive layer 52 in the present embodiment will be further described below.
It is understood that the heat spreader device 7 and the chip packaging ring R may have a certain tolerance in the thickness direction (i.e. the thickness direction of the chip packaging device) during the bonding process through the second adhesive layer 52, and therefore, in order to absorb the tolerance in the thickness direction, in some possible implementations, the second adhesive layer 52 may be provided as a flexible layer, i.e. the second adhesive layer 52 has elasticity.
In some possible implementations, a flexible material may be used in the second adhesive layer 52.
Illustratively, in the case that the second adhesive layer 52 employs a conductive adhesive, the conductive adhesive may include at least one of conductive foam and conductive silicone rubber. For example, the second adhesive layer 52 may be formed using conductive foam; for another example, the second adhesive layer 52 may be formed using conductive silicone rubber; for another example, the second adhesive layer 52 may be formed by mixing conductive foam and conductive silicone rubber.
Illustratively, in the case that the second bonding layer 52 is a non-conductive adhesive, the non-conductive adhesive may include at least one of a foam-based non-conductive adhesive and a rubber-based non-conductive adhesive filled with a high dielectric constant absorbing powder. For example, the second adhesive layer 52 may be a foamed non-conductive adhesive filled with a high dielectric constant absorbing powder; for another example, the second adhesive layer 52 may be a rubber-based non-conductive adhesive filled with high-dielectric-constant wave-absorbing powder; for another example, the second adhesive layer 52 may be formed by mixing a foam-type non-conductive adhesive filled with a high-dielectric-constant wave-absorbing powder and a rubber-type non-conductive adhesive filled with a high-dielectric-constant wave-absorbing powder.
In some possible implementations, an elastic member may be disposed in the second adhesive layer 52; for example, a stretchable structure such as a reed may be provided in the second adhesive layer 52.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. The chip packaging device is characterized by comprising a substrate and a chip arranged on the substrate;
the chip packaging device also comprises a solder mask layer and a packaging structure;
the packaging structure is connected with the substrate in the area around the chip through a first bonding layer;
the solder mask is positioned on the surface of one side of the substrate, which is provided with the chip, and a hollow area is formed in the connection area of the packaging structure and the substrate by the solder mask;
the first bonding layer adopts conductive adhesive; or the first adhesive layer is made of non-conductive glue with a dielectric constant larger than or equal to 7 and a loss factor larger than or equal to 0.02.
2. The chip package device according to claim 1, further comprising a heat spreader device, the package structure comprising a chip package lid;
the chip packaging cover is connected with the substrate in the area around the chip through the first bonding layer, and the first bonding layer is non-conductive glue with a dielectric constant larger than or equal to 7 and a loss factor larger than or equal to 0.02;
the chip packaging cover is connected with the surface of one side, away from the substrate, of the chip through first heat-conducting glue;
and the heat dissipation device is connected with the surface of one side of the chip packaging cover, which is far away from the chip, through second heat conduction glue.
3. The chip packaging device according to claim 1, wherein the chip packaging device further comprises a heat spreader device, the package structure comprises a chip package ring;
the chip packaging ring is connected with the substrate in the area around the chip through the first bonding layer;
the heat dissipation device is connected with the surface of one side, away from the substrate, of the chip through a third heat conduction adhesive, and the heat dissipation device is connected with the surface of one side, away from the substrate, of the chip packaging ring through a second bonding layer;
the second bonding layer adopts conductive adhesive; or the second adhesive layer is made of non-conductive glue with the dielectric constant being greater than or equal to 7 and the loss factor being greater than or equal to 0.02.
4. The chip packaging device of claim 3,
the first bonding layer and the second bonding layer are both made of conductive adhesive;
or the first bonding layer and the second bonding layer are both made of non-conductive glue, the dielectric constant of which is greater than or equal to 7, and the loss factor of which is greater than or equal to 0.02.
5. The chip packaging device of claim 3,
the second adhesive layer has elasticity.
6. The chip packaging device according to any one of claims 1 to 5,
the thickness of the first bonding layer is less than or equal to 0.1 mm.
7. The chip packaging device according to any one of claims 1 to 6,
the conductive adhesive adopted by the first bonding layer comprises at least one of conductive silver adhesive, nickel-carbon adhesive and silver-copper adhesive;
or the non-conductive adhesive adopted by the first bonding layer comprises at least one of silicone non-conductive adhesive and epoxy non-conductive adhesive filled with high dielectric constant materials.
8. The chip packaging device according to any one of claims 3 to 7,
the conductive adhesive adopted by the second bonding layer comprises at least one of conductive foam and conductive silicon rubber;
or the non-conductive adhesive adopted by the second bonding layer comprises at least one of foaming non-conductive adhesive and rubber non-conductive adhesive filled with high dielectric constant wave-absorbing powder.
9. The chip packaging device according to claims 1-8,
the first bonding layer is a closed annular bonding pattern;
or, the first bonding layer is formed by arranging a plurality of bonding patterns at intervals, and the distance between two adjacent bonding patterns is less than or equal to one tenth of the minimum wavelength of the electromagnetic wave in the shielding frequency band.
10. The chip packaging device according to any one of claims 1 to 9,
the hollow-out areas are continuous annular hollow-out patterns;
or the hollowed-out area comprises a plurality of hollowed-out patterns arranged at intervals.
11. An electronic device comprising a printed wiring board and a chip-packaged device according to any one of claims 1 to 10, said chip-packaged device being connected to said printed wiring board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010562083.9A CN113823622A (en) | 2020-06-18 | 2020-06-18 | Chip packaging device and electronic equipment |
| PCT/CN2021/083617 WO2021253912A1 (en) | 2020-06-18 | 2021-03-29 | Chip packaging device, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010562083.9A CN113823622A (en) | 2020-06-18 | 2020-06-18 | Chip packaging device and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113823622A true CN113823622A (en) | 2021-12-21 |
Family
ID=78911941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010562083.9A Pending CN113823622A (en) | 2020-06-18 | 2020-06-18 | Chip packaging device and electronic equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113823622A (en) |
| WO (1) | WO2021253912A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113922023A (en) * | 2021-11-29 | 2022-01-11 | 江苏贝孚德通讯科技股份有限公司 | Resonant rod and filter with temperature compensation |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1154944A (en) * | 1997-08-07 | 1999-02-26 | Toshiba Corp | Circuit board |
| US20020113306A1 (en) * | 2001-02-19 | 2002-08-22 | Kwon Heung Kyu | Semiconductor packages |
| US20040135238A1 (en) * | 2003-01-15 | 2004-07-15 | Sergiu Radu | EMI grounding pins for CPU/ASIC chips |
| CN1539167A (en) * | 2001-08-01 | 2004-10-20 | �Ҵ���˾ | EMI shielding for electronic packages |
| CN102779811A (en) * | 2012-07-20 | 2012-11-14 | 华为技术有限公司 | Chip package and chip packaging method |
| CN103943610A (en) * | 2014-04-16 | 2014-07-23 | 华为技术有限公司 | Electronic component packaging structure and electronic device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120053332A (en) * | 2010-11-17 | 2012-05-25 | 삼성전자주식회사 | Semiconductor package and method of forming the same |
| WO2012074775A1 (en) * | 2010-11-19 | 2012-06-07 | Analog Devices, Inc. | Packaged integrated device with electrically conductive lid |
| CN109727928B (en) * | 2017-10-30 | 2021-02-26 | 长鑫存储技术有限公司 | Semiconductor package structure with electromagnetic interference shielding and manufacturing method thereof |
-
2020
- 2020-06-18 CN CN202010562083.9A patent/CN113823622A/en active Pending
-
2021
- 2021-03-29 WO PCT/CN2021/083617 patent/WO2021253912A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1154944A (en) * | 1997-08-07 | 1999-02-26 | Toshiba Corp | Circuit board |
| US20020113306A1 (en) * | 2001-02-19 | 2002-08-22 | Kwon Heung Kyu | Semiconductor packages |
| CN1539167A (en) * | 2001-08-01 | 2004-10-20 | �Ҵ���˾ | EMI shielding for electronic packages |
| US20040135238A1 (en) * | 2003-01-15 | 2004-07-15 | Sergiu Radu | EMI grounding pins for CPU/ASIC chips |
| CN102779811A (en) * | 2012-07-20 | 2012-11-14 | 华为技术有限公司 | Chip package and chip packaging method |
| CN103943610A (en) * | 2014-04-16 | 2014-07-23 | 华为技术有限公司 | Electronic component packaging structure and electronic device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113922023A (en) * | 2021-11-29 | 2022-01-11 | 江苏贝孚德通讯科技股份有限公司 | Resonant rod and filter with temperature compensation |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021253912A1 (en) | 2021-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9968004B2 (en) | Thermal interface materials including electrically-conductive material | |
| JP5730159B2 (en) | Antenna board and antenna module | |
| CN108987378A (en) | Microelectronic device | |
| CN107305884B (en) | Board level shield with virtual ground capability | |
| JP2015233164A (en) | Electronic component | |
| US8890309B1 (en) | Circuit module and method of producing circuit module | |
| US20130113088A1 (en) | Chip packaging structure, chip packaging method, and electronic device | |
| JP2010245931A (en) | Antenna integrated module component, method for manufacturing the same, and electronic apparatus using the module component | |
| CN113823622A (en) | Chip packaging device and electronic equipment | |
| EP4181194A1 (en) | Packaging body and preparation method therefor, terminal and electronic device | |
| CN111653551B (en) | BGA chip packaging structure with high anti-electromagnetic pulse interference capability | |
| US20070077686A1 (en) | Packaging method for preventing chips from being interfered and package structure thereof | |
| EP4220705A1 (en) | Heat dissipation assembly reducing electromagnetic noise of chip, chip packaging assembly, and electronic device | |
| TWI797695B (en) | Packaging module, method thereof and electronic device | |
| CN211267247U (en) | Circuit board and electronic equipment | |
| KR20180094470A (en) | Heat dissipation assembly | |
| EP4231786A1 (en) | Reinforcing structure and electronic device | |
| KR101535914B1 (en) | Semiconductor package, circuit module having emi shield structure and circuit system comprising the same | |
| WO2023098503A1 (en) | Shielding structure, package body, board-level architecture, radiator, and electronic device | |
| CN210156370U (en) | Heat conduction shielding integrated structure of IC chip device | |
| KR101305581B1 (en) | Shield member and pcb comprising the shield member | |
| CN213126972U (en) | Panel, shell and electronic equipment with electromagnetic shielding function and antenna function | |
| CN218042315U (en) | Circuit board assembly and electronic equipment | |
| CN217881497U (en) | Semiconductor packaging device | |
| CN211267510U (en) | Communication device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20211224 Address after: 450046 Floor 9, building 1, Zhengshang Boya Plaza, Longzihu wisdom Island, Zhengdong New Area, Zhengzhou City, Henan Province Applicant after: Super fusion Digital Technology Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Applicant before: HUAWEI TECHNOLOGIES Co.,Ltd. |