CN113820892A - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

Info

Publication number
CN113820892A
CN113820892A CN202111141227.4A CN202111141227A CN113820892A CN 113820892 A CN113820892 A CN 113820892A CN 202111141227 A CN202111141227 A CN 202111141227A CN 113820892 A CN113820892 A CN 113820892A
Authority
CN
China
Prior art keywords
fan
display area
electrodes
array substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111141227.4A
Other languages
Chinese (zh)
Inventor
胡长珍
康报虹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to CN202111141227.4A priority Critical patent/CN113820892A/en
Publication of CN113820892A publication Critical patent/CN113820892A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)

Abstract

The application is applicable to the technical field of display, and provides an array substrate which comprises a plurality of data lines arranged in a display area, a fan-shaped lead structure arranged in a peripheral area and a plurality of first electrodes; the fan-shaped lead structure comprises a plurality of fan-out leads, two ends of each fan-out lead are respectively connected with a corresponding data line and a first electrode, and at least part of the fan-out leads are provided with curve sections at one ends deviating from the display area; the array substrate also comprises a chip on film, the chip on film comprises a film substrate and a plurality of second electrodes arranged on the film substrate, and the plurality of second electrodes are bound and connected with the plurality of first electrodes one by one; wherein, the distance from at least part of the second electrodes to the display area is unequal, so that the distance between the second electrodes and the connected curve section conforms to a preset range. The application also provides a display panel. The array substrate and the display panel can effectively prevent the fan-out lead wire from being short-circuited with the chip on film, and have good quality.

Description

Array substrate and display panel
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate and a display panel.
Background
In the GOA (Gate Driver on Array, abbreviated as Gate Driver on Array) circuit driving technology, the lead from the bonding pad (source bonding pad) of the data line (source line) to the active area (AA area) is designed to be fan out (fanout). In order to provide each lead with an equal resistance value, it is known in the prior art to design a partial section of the lead as an arcuate winding. However, if the arch winding is exposed in the outer electrode bonding (OLB) region, that is, the arch winding is not covered by the color film substrate, the arch winding is closer to the adjacent lead wires, and the electrodes on the Chip On Film (COF) are easily connected to the adjacent data line lead wires due to process deviation, thereby causing short circuit and further causing poor quality of the display device.
Disclosure of Invention
The application provides an array substrate and a display panel, which can enable electrodes on a chip on film to avoid a curve section of a fan-shaped lead so as to effectively prevent the fan-out lead from being short-circuited with the chip on film and improve the quality of the array substrate and the display panel.
An embodiment of a first aspect of the present application provides an array substrate, where a display area and a peripheral area located on a peripheral side of the display area are disposed on the array substrate;
the array substrate comprises a plurality of data lines arranged in the display area, a fan-shaped lead structure arranged in the peripheral area and a plurality of first electrodes; the fan-shaped lead structure comprises a plurality of fan-out leads, two ends of each fan-out lead are respectively connected with one corresponding data line and one first electrode, and at least part of the fan-out leads are provided with curve sections at one ends departing from the display area;
the array substrate further comprises a chip on film arranged in the peripheral area, the chip on film comprises a film substrate and a plurality of second electrodes arranged on the film substrate, and the plurality of second electrodes are bound and connected with the plurality of first electrodes one by one;
wherein, the distances from at least part of the second electrodes to the display area are unequal, so that the distance between the second electrodes and the connected curve segments conforms to a preset range
In the array substrate, at least one end of at least one part of the fan-out leads, which deviates from the display area, is provided with a curve section, the distances from at least one part of the second electrodes to the display area are unequal, namely the arrangement of the second electrodes is not parallel and level with the edge of the array substrate, through the design, the distances between the second electrodes and the corresponding curve sections can be controlled within a preset range, the second electrodes can avoid the curve sections, the phenomenon that the second electrodes contact the curve sections of the adjacent fan-out leads due to the manufacturing process or binding offset is avoided, the short circuit phenomenon is prevented, the quality of the array substrate is better, and the yield is higher.
In an embodiment, the distance from the end of the plurality of adjacent curved segments away from the display area to the display area gradually increases or decreases, and correspondingly, the distance from the plurality of second electrodes correspondingly connected with the plurality of curved segments to the display area gradually increases or decreases.
By adopting the technical scheme, the second electrodes are arranged according to the arrangement of the curve sections, and the curve sections are arranged in a step shape, so that the fan-out leads have equal impedance; the second electrodes are arranged in a step shape, the arrangement trend of the second electrodes is the same as that of the curve sections, and the second electrodes are prevented from contacting the curve sections corresponding to the adjacent data lines, so that short circuit is prevented.
In an embodiment, the outline edge of the flip chip film disposed toward the display area is not parallel to the edge of the display area.
By adopting the technical scheme, the flip chip film can avoid a plurality of curve segments which are arranged in a non-parallel and level manner, and the effect of preventing short circuit is realized.
In an embodiment, the shape of the flip chip is a parallelogram, and the shape edge of the flip chip facing the display area is inclined with respect to the edge of the display area.
By adopting the technical scheme, the second electrode on the chip on film can avoid the curve section, and the distance between the second electrode and the curve section is controlled within a preset range.
In an embodiment, the outline of the chip on film includes two connected parallelograms, each of the parallelograms is disposed obliquely with respect to an edge of the display area toward an outline side of the display area, and an intersection point of the two outline sides is closer to or farther from the display area than another end point of each of the outline sides.
By adopting the technical scheme, the shape of the chip on film is matched with the shape of the fan-shaped lead structure, and avoidance is carried out according to the shape of the fan-shaped lead structure.
In an embodiment, the shape of the flip-chip film is a sector, and a vertex of the sector is located on one side of the flip-chip film close to the display area or one side of the flip-chip film far from the display area.
By adopting the technical scheme, the chip on film is provided with the arc-shaped outline edge, and the end parts of the second electrodes can also be arranged along the arc-shaped outline edge.
In an embodiment, among the plurality of first electrodes, distances from the plurality of first electrodes connected to a plurality of adjacent curve segments to the display area gradually increase or decrease.
By adopting the technical scheme, part of the first electrodes are designed into the step shape, so that the first electrodes and the second electrodes can be completely overlapped, the area of a binding region is reduced, the area of a peripheral region is further reduced, and the narrow frame is favorably realized.
In an embodiment, the array substrate further includes an insulating layer covering the first electrode, and a thickness of the insulating layer is 0.3mm to 0.5 mm.
Through adopting above-mentioned technical scheme, the insulating layer obtains the thickening, avoids the insulating layer to be crushed, and then prevents that the second electrode is connected and the short circuit that causes with adjacent fan-out lead wire.
In an embodiment, the plurality of fan-out leads include a first fan-out lead arranged in the middle of the peripheral area and a second fan-out lead arranged on one side of the first fan-out lead, the first fan-out lead is connected with the data line through a straight line connecting section, the second fan-out lead is connected with the data line through an oblique line connecting section, wherein at least part of the first fan-out lead is provided with the curve section, and the curve section is arranged in an arc shape.
Because the first fan-out lead is closer to the binding area, the curve section is arranged on at least part of the first fan-out lead, and the resistance difference of the fan-out leads can be reduced.
A second aspect of the present application provides a display panel, comprising:
the array substrate as described in the first aspect, and
and the color film substrate is arranged opposite to the array substrate.
In the display panel, the chip on film is used for transmitting the driving signal sent by the driving circuit of the data line to each data line, and the display panel can effectively prevent the fan-out lead wire from being short-circuited with the chip on film, so that the quality is better.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application;
fig. 2 is a partial schematic view of a portion II of the array substrate shown in fig. 1;
fig. 3 is a schematic structural diagram of a chip on film in the array substrate shown in fig. 2;
fig. 4 is a partial schematic view of a part II in an array substrate according to a second embodiment of the present application;
fig. 5 is a schematic structural diagram of a first electrode in the array substrate shown in fig. 4;
fig. 6A to 6D are schematic views illustrating an outline of a chip on film according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a display panel according to a third embodiment of the present application;
fig. 8 is a schematic structural diagram of a display module according to a fourth embodiment of the present application.
The designations in the figures mean:
1. a display module; 2. a display panel; 3. a printed circuit board;
100. an array substrate; 10. a chip on film; 11. a film substrate; 12. a second electrode; 101. a contour edge; 21. a fan-out lead; 211. a curve segment; 212. a linear connecting section; 213. a diagonal connection section; 21a, first fan-out leads; 21b, second fan-out leads; 30. a first electrode; A. a fan-out region; B. a binding region; 201. an edge of the array substrate; 202. the edge of the color film substrate; 203. a display area edge;
200. a color film substrate; 300. frame glue; 400. and a liquid crystal layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings, which are examples. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered limiting of the present application. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
To explain the technical solutions of the present application, the following description is made with reference to specific drawings and examples.
Example one
A first aspect of the present application provides an array substrate. Referring to fig. 1, the array substrate 100 includes a Chip On Film (COF)10, such that the array substrate 100 is electrically connected to the printed circuit board through the COF 10.
Referring to fig. 1 and fig. 2, in a first embodiment of the present disclosure, an array substrate 100 is provided, where the array substrate 100 is provided with a display area (AA area) and a peripheral area located on a peripheral side of the display area, and fig. 2 illustrates a display area edge (AA edge)203, that is, an area above the display area edge 203 is the peripheral area, and an area below the display area edge 203 is the display area; the peripheral region comprises a fan-out region A and a binding region B, and the binding region B is located on one side, far away from the display region, of the fan-out region A.
The array substrate 100 includes a plurality of data lines (data lines) disposed in the display region, and a fan-shaped lead structure and a plurality of first electrodes 30 disposed in the peripheral region; the fan-out lead structure includes a plurality of fan-out leads 21, both ends of each fan-out lead 21 are respectively connected to a corresponding data line and a first electrode 30, and at least a part of the fan-out leads 21 have a curved section 211 at an end facing away from the display area. Because the lengths of the plurality of fan-out leads 21 in the fan-out area a are different, the impedance difference of each fan-out lead 21 can be reduced by arranging the curve section 211, so that the resistance values of the fan-out leads 21 are consistent. It can be understood that the lengths of the curved sections 211 in the adjacent fan-out leads 21 gradually change, so that the distances from the ends of the curved sections 211 far away from the display area to the display area also gradually change, and therefore, the adjacent curved sections 211 are arranged in a step shape.
Referring to fig. 2 and 3, the chip on film 10 includes a film substrate 11 and a plurality of second electrodes 12 disposed on the film substrate 11, the film substrate 11 is attached to the peripheral area of the array substrate 100, and the plurality of second electrodes 12 are connected to the plurality of first electrodes 30 in a one-to-one binding manner. It is understood that each second electrode 12 is electrically connected to a corresponding fan-out lead 21 through the first electrode 30, respectively.
Wherein, the distances from at least some of the second electrodes 12 to the display area are different, so that the distance between the second electrode 12 and the connected curve segment 211 conforms to a preset range. Specifically, the distances between the plurality of second electrodes 12 and the display area change along with the change of the distance from the end of the corresponding curve segment 211 far away from the display area to the display area, that is, the distances from the ends of the curve segments 211 far away from the display area to the display area of the plurality of fan-out leads 21 gradually change, correspondingly, the distances from the plurality of second electrodes 12 connected with the plurality of fan-out leads 21 to the display area also gradually change, and the change trends are consistent, so that the distances between the plurality of second electrodes 12 and the corresponding curve segments 211 can be controlled within a preset range, thereby preventing the second electrodes 12 from contacting the curve segments 211 of the adjacent fan-out leads 21 due to process or binding offset, and preventing the fan-out leads 21 from being short-circuited with the second electrodes 12. The preset distance range is not limited, and can be determined according to the structure of the array substrate.
It is understood that the array substrate 100 further includes a plurality of scan lines (source lines) and a plurality of Thin Film Transistors (TFTs) disposed in the display region, the plurality of scan lines and the plurality of data lines intersect with each other to form a plurality of pixel regions, and each pixel region is respectively disposed with at least one TFT and a pixel electrode electrically connected to the TFT. The scan lines are used for sending scan signals to the thin film transistors to control the switches of the thin film transistors, and the data lines are used for sending data voltage signals to the thin film transistors.
In one embodiment, the display panel is a GOA panel, and the driving circuit of the scan line is fabricated in a peripheral region of the display panel; the driving Circuit of the data line is fabricated on an external Printed Circuit Board (PCB), and the flip-chip film 10 is electrically connected between the PCB and the display panel to transmit a driving signal generated by the driving Circuit of the data line to each data line.
The array substrate 100 includes a chip on film 10, a plurality of data lines, a plurality of fan-out leads 21 and a plurality of first electrodes 30, wherein each first electrode 30 is connected to a corresponding data line through the fan-out lead 21; the flip chip film 10 includes a plurality of second electrodes 12, and each of the second electrodes 12 is respectively bound and connected to a corresponding first electrode 30, so as to connect a driving circuit of the data line and the data line through the flip chip film 10. The distance between the plurality of second electrodes 12 and the corresponding curve section 211 can be controlled within a preset range through the design, so that the second electrodes 12 are prevented from contacting the curve section 211 of the adjacent fan-out lead 21 due to process or binding offset, the short circuit phenomenon is prevented, and the array substrate 100 has better quality and higher yield.
In the array substrate 100, the shape of the flip chip film 10 is designed according to the structure of the fan-shaped lead to bypass the curved section 211 of the fan-shaped lead, thereby effectively preventing short circuit in the fan-out area and improving the quality of the product.
In an embodiment, the distance from the end of the adjacent curve segments 211 far away from the display area to the display area gradually increases or decreases, and correspondingly, the distance from the second electrodes 12 correspondingly connected to the adjacent curve segments 211 to the display area gradually increases or decreases, so that the end of the adjacent curve segments 211 far away from the display area and the second electrodes 12 correspondingly connected to the adjacent curve segments 211 are arranged in a step shape. The second electrodes 12 are arranged according to the arrangement of the curve sections 211, and the plurality of fan-out leads 21 can have equal impedance by arranging the curve sections 211 arranged in a step shape; by arranging the second electrodes 12 arranged in a ladder shape, the arrangement trend of the second electrodes 12 and the curve sections 211 can be the same, and the second electrodes 12 are prevented from contacting the curve sections 211 corresponding to the adjacent data lines, so that short circuit is prevented.
As shown in fig. 3, the plurality of second electrodes 12 in the chip on film 10 are arranged along the first direction X, the plurality of second electrodes 12 are arranged in parallel and at intervals, and at least a portion of the second electrodes 12 are arranged in a step shape.
Referring to fig. 1 to fig. 3, the second electrode 12 can avoid the curve segment 211 corresponding to the adjacent data line, and when binding deviation occurs, the second electrode 12 and the curve segment 211 corresponding to the adjacent data line are arranged in a staggered manner along the first direction X (horizontal direction); along a second direction Y (longitudinal direction) perpendicular to the first direction X, the second electrode 12 and the curve segment 211 corresponding to the adjacent data line are arranged in a staggered manner, so that the second electrode 12 avoids the curve segment 211 corresponding to the adjacent data line, and short circuit is prevented; in addition, the second electrode 12 does not directly connect to the curved section 211 in the second direction Y, and the avoidance effect can be achieved.
It will be appreciated that the bonding offset may be laterally offset and/or longitudinally offset, and that whichever offset is present, the above described flip-chip 10 bypasses the curved segment 211, preventing shorting at the fan-out region.
In one embodiment, the outline of the flip-chip film 10 disposed toward the display region is not parallel to the edge of the display region; the conventional flip-chip film 10 has a rectangular shape, so that the edge of the flip-chip film 10 is parallel to the edge of the display area, and the ends of the second electrodes 12 on the flip-chip film 10 are flush and cannot be staggered with the curve sections 211 arranged in a step shape; in the embodiment, by changing the shape of the chip on film 10, the chip on film 10 can avoid the plurality of curve segments arranged in a non-parallel manner, and the arrangement trends of the plurality of second electrodes 12 and the curve segments 211 are consistent, so that the short circuit prevention effect is realized.
Optionally, the shape of the flip-chip film 10 is a parallelogram, and the shape edge 101 of the flip-chip film 10 disposed toward the display area is disposed obliquely with respect to the edge of the display area, that is, the shape edge 101 of the flip-chip film 10 disposed toward the display area is disposed obliquely with respect to the first direction X. Accordingly, the connection line of the end portions of the plurality of second electrodes 12 is also disposed obliquely to the edge of the display area. By adopting the above technical scheme, the second electrode 12 on the chip on film 10 can avoid the curved section 211, and the distance between the second electrode 12 and the curved section 211 is ensured to be controlled within a preset range. It is understood that the distance between each second electrode 12 and the corresponding curved section 211 may be equal or different, as long as the plurality of second electrodes 12 can avoid the area where the curved section 211 is located as a whole.
Fig. 2 illustrates an array substrate edge 201 and a color filter substrate edge 202, and as shown in fig. 1 and fig. 2, at least a part of the curve segment 211 is not covered by the color filter substrate.
The array substrate 100 further includes an insulating layer covering the first electrode 30 and a conductive adhesive disposed between the first electrode 30 and the second electrode 12, wherein the insulating layer has a thickness of 0.3mm to 0.5 mm. The Conductive adhesive may be Anisotropic Conductive Film (ACF), and the ACF contains Conductive particles, so that the contact area between the first electrode 30 and the second electrode 12 is increased, and the signal conduction yield and strength are increased; in order to prevent the conductive particles from crushing the insulating layer after the pressing process, the thickness of the insulating layer is set to be 0.3mm to 0.5mm in the embodiment, and the insulating layer is prevented from being crushed by thickening the insulating layer, so that the second electrode 12 is prevented from being connected with the adjacent fan-out lead 21 to cause short circuit.
Optionally, the plurality of fan-out leads 21 include a first fan-out lead 21a disposed at a middle position of the peripheral region and a second fan-out lead 21b disposed at one side of the first fan-out lead 21a, that is, the first fan-out lead 21a is a middle fan-out lead, and the second fan-out lead 21b is a side fan-out lead.
The first fan-out lead 21a is connected with the data line through a straight line connecting section 212, and the second fan-out lead 21b is connected with the data line through an oblique line connecting section 213, wherein at least part of the first fan-out line is provided with a curved section 211, and the curved section 211 is arranged in an arc shape. Since the first fan-out lead 21a is closer to the bonding region B, the curved section 211 is provided on at least a part of the first fan-out lead 21a, so that the resistance difference of the plurality of fan-out leads 21 can be reduced. It can be understood that, according to the requirement, the curved sections 211 may be disposed on all the first fan-out leads 21a, or the curved sections 211 may be disposed on at least a portion of the second fan-out leads 21b, and in addition, the design of the curved sections 211 may also reduce the space where the fan-out leads 21 are located, which is beneficial to implement narrow framing.
Example two
Referring to fig. 4 and 5, a second embodiment of the present application provides an array substrate 100, similar to the first embodiment, the array substrate 100 includes a plurality of data lines disposed in a display area, and a fan-shaped lead structure and a plurality of first electrodes 30 disposed in a peripheral area; the fan-shaped lead structure comprises a plurality of fan-out leads 21, two ends of each fan-out lead 21 are respectively connected with a corresponding data line and a first electrode 30, and at least one part of the fan-out leads 21 is provided with a curve section 211 at one end departing from the display area; the array substrate 100 further includes a chip on film 10, and the chip on film 10 includes a film substrate and a plurality of second electrodes 12 disposed on the film substrate, wherein distances from at least some of the second electrodes 12 to the display area are different, so that distances between the second electrodes 12 and the corresponding curve segments conform to a predetermined range. The distance between the plurality of second electrodes 12 and the display area varies with the distance from the end of the corresponding curve segment 211 away from the display area to the display area. The difference is that, among the plurality of first electrodes 30, the distances from the plurality of first electrodes 30 connected to the plurality of adjacent curve segments 211 to the display region gradually increase or decrease, and the variation trend is the same as the variation trend of the curve segments, therefore, the plurality of first electrodes 30 are also arranged in a step shape, because the first electrodes 30 and the second electrodes 12 are arranged in an overlapping manner, in this embodiment, part of the first electrodes 30 are designed in a step shape, so that the first electrodes 30 and the second electrodes 12 can be completely overlapped, the area of the binding region B is reduced, the area of the peripheral region is further reduced, and the narrow-framing is favorably realized.
Optionally, the plurality of first electrodes 30 are parallel to each other, wherein a portion of the first electrodes 30 may be disposed flush with each other, and the plurality of first electrodes 30 connected to the plurality of adjacent curved segments 211 are arranged in a step shape.
It is understood that the second electrode 12 as the binding pad may be designed to be rectangular, but is not limited thereto.
In other embodiments, the shape of the flip-chip film 10 can be various shapes. Referring to fig. 6A, in an embodiment, the outline of the chip on film 10 includes two connected parallelograms, each parallelogram is disposed in an inclined manner with respect to the edge of the display area towards the outline side 101 of the display area, and the intersection point of the two outline sides 101 is farther away from the display area than the other end point of each outline side 101. The second electrodes 12 are arranged along the edge 101 of the flip-chip film 10 facing the display area, i.e. the distance between the second electrodes 12 and the display area gradually increases and then gradually decreases, and the shape of the flip-chip film 10 is adapted to the shape of the fan-shaped lead structure and is avoided according to the shape of the fan-shaped lead structure.
Referring to fig. 6B, in an embodiment, the outline of the chip on film 10 includes two connected parallelograms, each of the parallelograms is disposed obliquely with respect to the edge of the display area toward the outline side 101 of the display area, and the intersection of the two outline sides 101 is closer to the display area than the other end of each outline side 101. The second electrodes 12 are arranged along the edge 101 of the flip-chip film 10 facing the display area, i.e. the distance between the second electrodes 12 and the display area gradually decreases and then gradually increases, and the shape of the flip-chip film 10 is adapted to the shape of the fan-shaped lead structure and avoids according to the shape of the fan-shaped lead structure.
In the above embodiment, the plurality of second electrodes 12 are arranged in the first direction, and the end portions of the plurality of second electrodes 12 are disposed along the outer shape side 101 inclined to the first direction; in other embodiments, the flip-chip film 10 has an arc-shaped edge, and the ends of the second electrodes 12 can also be disposed along the arc-shaped edge 101.
Referring to fig. 6C, in an embodiment, the shape of the flip-chip film 10 is a sector, and a vertex of the sector is located on a side of the flip-chip film 10 close to the display area. The outer edge 101 of the flip chip 10 facing the display area is arc-shaped, and it can be understood that the second electrodes 12 are arranged along the arc-shaped outer edge 101, that is, the distance between the second electrodes 12 and the display area is gradually decreased and then gradually increased to adapt to the shape of the fan-shaped lead structure.
Referring to fig. 6D, in an embodiment, the shape of the flip-chip film 10 is a sector, and a vertex of the sector is located on a side of the flip-chip film 10 away from the display area. The outer edge 101 of the flip chip 10 facing the display area is arc-shaped, and it can be understood that the second electrodes 12 are arranged along the arc-shaped outer edge 101, that is, the distance between the second electrodes 12 and the display area gradually increases and then gradually decreases to adapt to the shape of the fan-shaped lead structure.
It is understood that the shape of the flip-chip film 10 is not limited thereto, and for example, the flip-chip film 10 may also have a diamond shape, a semi-arc shape, etc.
It is understood that the edge 101 of the flip-chip film 10 facing the display area may also include a straight edge portion and an arc portion, which are arranged according to the shape of the fan-shaped lead structure.
It is understood that the number of the flip-chip films 10 in the array substrate 100 may be one or more, and when the number of the flip-chip films 10 is multiple, the multiple flip-chip films 10 respectively connect to a portion of the data lines.
EXAMPLE III
A second aspect of the present application provides a display panel. Referring to fig. 1 and fig. 7, a third embodiment of the present application provides a display panel 2, including the array substrate 100 according to the first aspect, and a color filter substrate 200 disposed opposite to the array substrate 100.
The display panel 2 further includes a liquid crystal layer 400 and a sealant 300 disposed between the array substrate 100 and the color filter substrate 200, the array substrate 100 and the color filter substrate 200 are bonded together by the sealant 300, and the sealant 300 is disposed on the outer periphery of the display region.
Example four
Referring to fig. 8, the present application further provides a display module 1, which includes a display panel 2 and a printed circuit board 3, wherein the printed circuit board 3 is disposed on one side of the display panel 2, and a flip chip film 10 is electrically connected between the display panel 2 and the printed circuit board 3.
The printed circuit board 3 is provided with a driving circuit of the data line, and the chip on film 10 is used for transmitting a driving signal sent by the driving circuit of the data line to each data line.
The display module 1 and the display panel 2 can effectively prevent the fan-out lead 21 and the flip chip film 10 from being short-circuited, and have good quality.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. The utility model provides an array substrate, be equipped with the display area on the array substrate and be located the peripheral region of display area week side, its characterized in that:
the array substrate comprises a plurality of data lines arranged in the display area, a fan-shaped lead structure arranged in the peripheral area and a plurality of first electrodes; the fan-shaped lead structure comprises a plurality of fan-out leads, two ends of each fan-out lead are respectively connected with one corresponding data line and one first electrode, and at least part of the fan-out leads are provided with curve sections at one ends departing from the display area;
the array substrate further comprises a chip on film arranged in the peripheral area, the chip on film comprises a film substrate and a plurality of second electrodes arranged on the film substrate, and the plurality of second electrodes are bound and connected with the plurality of first electrodes one by one;
and the distances from at least part of the second electrodes to the display area are unequal, so that the distances between the second electrodes and the connected curve segments conform to a preset range.
2. The array substrate according to claim 1, wherein the distance from the end of the plurality of adjacent curved segments away from the display area to the display area gradually increases or decreases, and correspondingly, the distance from the plurality of second electrodes correspondingly connected to the plurality of adjacent curved segments to the display area gradually increases or decreases.
3. The array substrate of claim 2, wherein the edge of the COF disposed toward the display area is not parallel to the edge of the display area.
4. The array substrate of claim 3, wherein the shape of the flip-chip on film is a parallelogram, and the edge of the flip-chip on film disposed toward the display area is disposed obliquely with respect to the edge of the display area.
5. The array substrate of claim 3, wherein the COF outline comprises two connected parallelograms, each of the parallelograms is tilted toward an outline side of the display area relative to an edge of the display area, and an intersection of the two outline sides is closer to or farther from the display area than another end of each of the outline sides.
6. The array substrate of claim 3, wherein the shape of the COF is a sector, and the vertex of the sector is located on one side of the COF close to the display area or one side of the COF far from the display area.
7. The array substrate of claim 2, wherein the distance from the plurality of first electrodes connected to the plurality of adjacent curved segments to the display area gradually increases or decreases among the plurality of first electrodes.
8. The array substrate of any one of claims 1-7,
the array substrate further comprises an insulating layer covering the first electrode, and the thickness of the insulating layer is 0.3mm-0.5 mm.
9. The array substrate of any one of claims 1-7, wherein the plurality of fan-out leads includes a first fan-out lead disposed at a middle position of the peripheral region and a second fan-out lead disposed at one side of the first fan-out lead, the first fan-out lead is connected to the data line by a straight line connection section, the second fan-out lead is connected to the data line by a diagonal line connection section, wherein at least a portion of the first fan-out lead is provided with the curved section, and the curved section is disposed in an arcuate shape.
10. A display panel, comprising:
the array substrate of any one of claims 1-9, and
and the color film substrate is arranged opposite to the array substrate.
CN202111141227.4A 2021-09-28 2021-09-28 Array substrate and display panel Pending CN113820892A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111141227.4A CN113820892A (en) 2021-09-28 2021-09-28 Array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111141227.4A CN113820892A (en) 2021-09-28 2021-09-28 Array substrate and display panel

Publications (1)

Publication Number Publication Date
CN113820892A true CN113820892A (en) 2021-12-21

Family

ID=78921463

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111141227.4A Pending CN113820892A (en) 2021-09-28 2021-09-28 Array substrate and display panel

Country Status (1)

Country Link
CN (1) CN113820892A (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120257132A1 (en) * 2011-04-11 2012-10-11 Hitachi Displays, Ltd. Liquid crystal display device and manufacturing method thereof
CN104062789A (en) * 2014-07-21 2014-09-24 深圳市华星光电技术有限公司 Display device
CN206573830U (en) * 2017-03-13 2017-10-20 惠科股份有限公司 A kind of array base palte and display device
CN110488545A (en) * 2018-05-15 2019-11-22 三星显示有限公司 Display panel and display equipment including display panel
CN209803525U (en) * 2019-04-10 2019-12-17 武汉华星光电技术有限公司 Display panel and display device
CN111708231A (en) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 Display panel and display device
CN112133201A (en) * 2020-09-30 2020-12-25 厦门天马微电子有限公司 Array substrate and display panel display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120257132A1 (en) * 2011-04-11 2012-10-11 Hitachi Displays, Ltd. Liquid crystal display device and manufacturing method thereof
CN104062789A (en) * 2014-07-21 2014-09-24 深圳市华星光电技术有限公司 Display device
CN206573830U (en) * 2017-03-13 2017-10-20 惠科股份有限公司 A kind of array base palte and display device
CN110488545A (en) * 2018-05-15 2019-11-22 三星显示有限公司 Display panel and display equipment including display panel
CN209803525U (en) * 2019-04-10 2019-12-17 武汉华星光电技术有限公司 Display panel and display device
CN111708231A (en) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 Display panel and display device
CN112133201A (en) * 2020-09-30 2020-12-25 厦门天马微电子有限公司 Array substrate and display panel display device

Similar Documents

Publication Publication Date Title
CN108388054B (en) Display panel and display device
CN110579916A (en) display panel, preparation method thereof and display device
US8300200B2 (en) Fan-out circuit and display panel
TWI397736B (en) Active device arry substrate and display device
CN108469927B (en) Touch display panel, driving method thereof and touch display device
WO2020211200A1 (en) Display panel and display apparatus
JP2002139741A (en) Liquid crystal display device of equal resistance wiring
JP3276545B2 (en) Active matrix type liquid crystal display panel and active matrix type liquid crystal display device
CN110673409B (en) Liquid crystal display module
CN110246882B (en) Display panel, display device and manufacturing method of display panel
CN110928061B (en) Display panel and display device
KR20080000199A (en) Display substrate and display device having the same
WO2020168762A1 (en) Display panel
US7675602B2 (en) Board device and method for manufacturing display element
CN111323952B (en) LCD mother board
CN210294739U (en) Display panel and display device
TWI438527B (en) Display panel
CN1690778A (en) Display device
CN108073003B (en) Display panel, pixel array substrate and circuit array structure
CN113820892A (en) Array substrate and display panel
EP2728977A2 (en) Display device
US10928692B2 (en) Thin film transistor substrate and liquid crystal display panel
CN110890022A (en) Chip on film and display device
CN113823183B (en) Display panel and display device
US11487169B2 (en) Substrate comprising a first lead having a curved section close to a bonding electrode and a straight section close to an edge of a substrate and display panel

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20211221

RJ01 Rejection of invention patent application after publication