CN113820612B - Error compensation circuit and integrated circuit for measuring battery impedance - Google Patents
Error compensation circuit and integrated circuit for measuring battery impedance Download PDFInfo
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- CN113820612B CN113820612B CN202010567832.7A CN202010567832A CN113820612B CN 113820612 B CN113820612 B CN 113820612B CN 202010567832 A CN202010567832 A CN 202010567832A CN 113820612 B CN113820612 B CN 113820612B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
- G01R31/389—Measuring internal impedance, internal conductance or related variables
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention relates to an error compensation circuit which comprises a time delay unit, a first error detection unit, a second error detection unit, a first error compensation unit, a second error compensation unit and an output control unit. The delay unit is used for delaying an input signal for a fixed time to generate a first delay signal; the first error detection unit is used for comparing the first delay signal with an output signal of an external component to detect a rising edge error of the output signal, and the second error detection unit is used for comparing the first delay signal with the output signal of the external component to detect a falling edge error of the output signal; the first error compensation unit is used for generating a first compensation signal according to the rising edge error and the input signal, and the second error compensation unit is used for generating a second compensation signal according to the falling edge error and the input signal; the output control unit is used for controlling the error compensation circuit to output the first compensation signal or the second compensation signal so as to compensate the error of the output signal generated by the external element.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an error compensation circuit and an integrated circuit for measuring battery impedance.
Background
In the field of battery research, measuring internal resistance (impedance) parameters of batteries is an important means for evaluating battery performance. The internal resistance of the battery is generally measured by an Electrochemical Impedance Spectroscopy (EIS). The measurement principle is that in the normal working state of the battery, sinusoidal voltage (current) signals with small amplitude and different frequencies are input into a battery system, corresponding output current (voltage) signals are measured, the frequency impedance spectrum of the lithium battery is obtained according to the ratio of the voltage signals and the current signals of all the frequencies, and the fine change in the battery can be reflected.
FIG. 1 is a schematic diagram of a battery impedance measurement system. Referring to fig. 1, the battery impedance measurement system 100 mainly includes a signal generator 110 and a measurement circuit 120. The signal generator 110 outputs a sine wave signal and a cosine wave signal to the external battery 140 and the measuring circuit 120. The signal generator 110 may generate sine wave signals (Sin) and cosine wave signals (Cos) having frequencies of 7.45mHz to 7.8 kHz. Wherein Cos and-Cos have a phase difference of 180 degrees. The measurement circuit 120 is typically a Fast Fourier Transform/Discrete Fourier Transform (FFT/DFT) circuit. The battery impedance measurement system 100 also includes an external transistor 130 connected in parallel to an external battery 140. The external transistor 130 functions as a switch, and the external transistor 130 is used together with an external resistor 131 to control whether the current/voltage signal from the signal generator 110 is inputted to the external battery 140. As shown in fig. 1, the real part (Zreal) and the imaginary part (Zimag) of the impedance Z of the external battery 140 can be calculated by the measurement circuit 120. However, since the characteristics of the external transistor 130 are affected by temperature, voltage, etc., the signal passing through the external transistor 130 is distorted, such as changes in phase and amplitude, and thus the signal input to the external battery 140 is also distorted, such as changes in both duty ratio and amplitude of the current signal. And the variation is not constant but varies depending on the ambient temperature and the voltage applied to the external transistor 130, and the characteristics of the external transistor 130 itself. This may result in inaccurate impedance measurements of the external battery 140.
Fig. 2 is a schematic diagram of a signal distortion of the external transistor in fig. 1. Referring to fig. 2, ideally, the Gate voltage (Ideal Gate voltage) of the external transistor 130 and the MOS current (Ideal MOS current) flowing through the external transistor 130 are square waves having Ideal vertical rising and falling edges, and the duty ratio of the signal is 50%. However, due to the above problems, both the actual Gate voltage (Gate voltage) and the MOS current (MOS current) of the external transistor 130 are distorted, which is particularly shown in that the rising edge and the falling edge thereof are not ideal vertical rising and falling, but rise and fall in a curve. The left diagram in fig. 2 shows the deformation of the rising edge (Up), and the right diagram shows the deformation of the falling edge (Down). In addition, the rising edge and the falling edge of the gate voltage and the MOS current are respectively phase-shifted, and the phase shift of the rising edge and the phase shift of the falling edge are not equal, which corresponds to that the duty ratio of the signal is also changed, resulting in an error. The curves shown in fig. 2 may be different for different types, parameters, of external transistors 130, and different ambient temperatures and voltages. Therefore, it is desirable to provide a method for compensating signal errors that occur when the external transistors 130 are exposed to different ambient temperatures and voltages.
Disclosure of Invention
The invention aims to solve the technical problem of providing an error compensation circuit, which is used for carrying out error compensation on output signals of external elements in a battery impedance measurement circuit so as to realize accurate measurement on the impedance of an external battery.
In order to solve the above technical problem, the present invention provides an error compensation circuit, an input signal of the error compensation circuit has a rising edge and a falling edge, the error compensation circuit is connected to an external device for compensating an error caused by the external device, and the error compensation circuit includes: the device comprises a delay unit, a first error detection unit, a second error detection unit, a first error compensation unit, a second error compensation unit and an output control unit; the delay unit is used for delaying the input signal for a fixed time to generate a first delay signal; the first error detection unit is used for comparing the first delay signal with an output signal of the external component to detect a rising edge error of the output signal, and the second error detection unit is used for comparing the first delay signal with the output signal of the external component to detect a falling edge error of the output signal; the first error compensation unit is used for generating a first compensation signal according to the rising edge error and the input signal, and the second error compensation unit is used for generating a second compensation signal according to the falling edge error and the input signal; and the output control unit is used for controlling the error compensation circuit to output the first compensation signal or the second compensation signal.
In an embodiment of the invention, the error compensation circuit further includes a first counting unit and a second counting unit, the first counting unit is configured to count the rising edge errors detected by the first error detection unit, and the second counting unit is configured to count the falling edge errors detected by the second error detection unit.
In an embodiment of the invention, the first counting unit includes a first register for registering the number of rising edge errors, and the second counting unit includes a second register for registering the number of falling edge errors.
In an embodiment of the present invention, when the number of the rising edge errors reaches a first threshold, the first counting unit sends the number of the rising edge errors to the first error compensation unit; and when the number of the falling edge errors reaches a second threshold value, the second counting unit is used for sending the number of the falling edge errors to the second error compensation unit.
In an embodiment of the invention, the first error detection unit and/or the second error detection unit is a phase frequency detector.
In an embodiment of the present invention, the delay time of the fixed time is 2 microseconds.
In an embodiment of the invention, the output control unit is a switch circuit.
In an embodiment of the invention, the input signal is a square wave.
In an embodiment of the invention, the output signal is connected to an external battery and is used for measuring an impedance of the external battery.
In an embodiment of the invention, the error compensation circuit is adapted to be integrated in a battery impedance measurement circuit.
The present invention further provides a battery impedance measuring system for solving the above technical problems, including the above error compensation circuit.
The error compensation circuit takes the output signal of the external element as feedback input, and detects the rising edge and the falling edge of the output signal of the external element respectively, so that the error of the rising edge and the falling edge is compensated in real time, the error caused by the output signal of the external element by temperature, voltage and the like can be effectively compensated, and the error compensation circuit is suitable for various external elements of different types. The battery impedance measuring system of the invention adopts the error compensation circuit, and can improve the accuracy of impedance measurement of the external battery.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a schematic diagram of a battery impedance measurement system;
FIG. 2 is a schematic diagram of a signal distortion of the external transistor of FIG. 1;
FIG. 3 is a schematic diagram of a battery impedance measurement system according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a battery impedance measurement system according to another embodiment of the present invention;
fig. 5 is a schematic diagram of signals compensated by the error compensation circuit according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, so that the scope of the present application is not to be construed as being limited. Further, although the terms used in the present application are selected from publicly known and used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Further, it is required that the present application is understood not only by the actual terms used but also by the meaning of each term lying within.
It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.
In the battery impedance measuring circuit, the external element is used for controlling the on-off of the current transmitted to the battery to be measured, so that the performance of the external element has important influence on the transmission of the measuring signal and has obvious influence on the accuracy of the measuring result. Embodiments of the present invention describe an error compensation circuit and a battery impedance measurement system including the same.
Fig. 3 is a schematic structural diagram of a battery impedance measuring system according to an embodiment of the invention. As shown in fig. 3, in the battery impedance measurement system 200, the signal generator 210 may generate a square wave signal as an input signal S of the error compensation circuit 220 of the present invention. It will be appreciated that the square wave signal has a rising edge and a falling edge. The first harmonic(s) may be extracted from a square wave signal to produce a sine wave signal. The difference of the sine wave signal according to the phase may be in the form of a sine function or a cosine function, and the sine wave signal and the cosine wave signal may be input signals of the impedance measuring circuit 250.
In a normal case, signals measured from both ends of the external battery 240 of the impedance to be measured are input to the impedance measuring circuit 250 after passing through the processing circuit 260. The impedance measuring circuit 250 calculates and outputs the impedance Z of the external connection 240 according to the sine wave signal and/or the cosine wave signal generated by the signal generator 210 and the signal after passing through the processing circuit 260. The impedance measurement circuit 250 may be the measurement circuit 120 as described in fig. 1.
Referring to fig. 3, the present invention provides an error compensation circuit 220, wherein the error compensation circuit 220 is connected to an external component 230 for compensating an error caused by the external component 230. The error compensation circuit 220 includes a delay unit 221, a first error detection unit 222a, a second error detection unit 222b, a first error compensation unit 223a, a second error compensation unit 223b, and an output control unit 224. The delay unit 221 is configured to delay the input signal S for a fixed time to generate a first delayed signal S1. The first delayed signal S1 is transmitted to the first error detection unit 222a and the second error detection unit 222b. Accordingly, the first delay signal S1 also includes a rising edge and a falling edge.
In an embodiment of the present invention, the fixed delay time of the first delayed signal S1 with respect to the input signal S is 2 μ S. The duration of the fixed delay is determined by the maximum delay that can be caused by the external component 230.
Referring to fig. 3, the first delay signal S1 is input to the first error detection unit 222a and the second error detection unit 222b, respectively. In the embodiment shown in fig. 3, the external component 230 is specifically a transistor, the drain of which is connected to the anode of the external component 240 through a resistor 231; the source of the transistor is connected to the cathode of the external connection 240. The output terminal of the output control unit 224 is connected to the gate of the transistor, that is, the output signal of the output control unit 224 is used as the switching control signal Sc of the transistor to control the transistor to be turned on or off. The drains of the transistors are connected to the first error detection unit 222a and the second error detection unit 222b, and the output signal next after passing through the external element 230 is input to the first error detection unit 222a and the second error detection unit 222b.
The first error detection unit 222a is configured to compare the first delay signal S1 with the output signal next of the external component 230 to detect a rising edge error Sd _ u of the output signal next, and the second error detection unit 222b is configured to compare the first delay signal S1 with the output signal next of the external component 230 to detect a falling edge error Sd _ d of the output signal next.
The present invention is not limited to the specific implementation of the external device 230, and the external device 230 may be various transistors, such as a Bipolar Junction Transistor (BJT), a Field Effect Transistor (FET), etc., or other similar electronic devices that may cause errors.
Referring to fig. 3, the first error detecting unit 222a is connected to the first error compensating unit 223a, and inputs the detected rising edge error Sd _ u to the first error compensating unit 223a; the second error detecting unit 222b is connected to the second error compensating unit 223b, and inputs the detected falling edge error Sd _ d to the second error compensating unit 223b. The input signal S generated from the signal generator 210 is also input to the first error compensation unit 223a and the second error compensation unit 223b at the same time.
The first error compensation unit 223a determines the first compensation signal Sc1 output therefrom according to the input signal S and the rising edge error Sd _ u, and inputs the first compensation signal Sc1 to the output control unit 224; the second error compensation unit 223b determines the second compensation signal Sc2 output therefrom according to the input signal S and the falling edge error Sd _ d, and inputs the second compensation signal Sc2 to the output control unit 224.
The output control unit 224 is configured to control the error compensation circuit 220 to output the first compensation signal Sc1 or the second compensation signal Sc2. Specifically, the output control unit 224 determines the control signal Sc to be output to the external component 230 according to the first compensation signal Sc1 and the second compensation signal Sc2. The control signal Sc may be the first compensation signal Sc1 or the second compensation signal Sc2. The signal inputted to the external component 230 is controlled by the control signal Sc, so as to compensate the problems of the deformation and delay of the rising edge and the falling edge caused by the external component 230.
In some embodiments, the output control unit 224 is a switching circuit.
For example, when the fixed delay of the first delayed signal S1 with respect to the input signal S is set to 2 μ S, i.e. 2000ns. When the first error detection unit 222a detects that the rising edge error Sd _ u of the output signal Sext is 200ns and the second error detection unit 222b detects that the falling edge error Sd _ d of the output signal Sext is 600ns, the first error compensation unit 223a delays the first compensation signal Sc1 by 1800ns compared with the input signal S and the second error compensation unit 223b delays the second compensation signal Sc2 by 1400ns compared with the input signal S.
In some embodiments, the first error detection unit 222a and/or the second error detection unit 222b may be a Phase Detector or a Phase and Frequency Detector (Phase and Frequency Detector). A phase detector may be used to detect a phase difference between the input signal and the reference signal. The first error detecting unit 222a is configured to detect a phase difference between a rising edge of the output signal next and a rising edge of the first delay signal S1, and the second error detecting unit 222b is configured to detect a phase difference between a falling edge of the output signal next and a falling edge of the first delay signal S1.
In a preferred embodiment, the first error detection unit 222a and the second error detection unit 222b are both phase and frequency detectors for comparing the phase or frequency difference of the signal to be measured and the reference signal. Typically, the phase and frequency detector comprises two output pins: an UP (UP) pin and a DOWN (DOWN) pin. And generating a pulse train on the UP pin and the DOWN pin according to the comparison result, wherein the pulse train represents the degree to which the signal to be detected needs to be adjusted, for example, the pulse train of the UP pin represents the degree to which the frequency of the signal to be detected needs to be increased, and the pulse train of the DOWN pin represents the degree to which the frequency of the signal to be detected needs to be decreased. For a signal input to the phase and frequency detector, the phase of the signal may be obtained by the position of the detected signal edge, and the frequency of the signal may be obtained by the number of detected signal edges. It will be appreciated that the phase and frequency detector obtains the phase and frequency of its detected signal by some computational method.
The phase and frequency detector as the first error detection unit 222a is set to a rising edge trigger. Accordingly, the phase and frequency detector as the second error detection unit 222b is set to the falling edge trigger. When the frequency and/or phase of the rising edge of the first delay signal S1 and the rising edge of the output signal next of the external component 230 are different, the UP pin or the DOWN pin of the first error detection unit 222a outputs a pulse train as the rising edge error Sd _ u output by the first error detection unit 222 a. Accordingly, when the frequency and/or phase of the falling edge of the first delay signal S1 and the falling edge of the output signal next of the external element 230 are different, the UP pin or the DOWN pin of the second error detection unit 222b outputs a pulse train as the falling edge error Sd _ d output by the second error detection unit 222b.
The phase detector or phase and frequency detector employed in the present invention may be one commonly used in the art and is suitable for integration in an integrated circuit.
In some cases, the first error detection unit 222a and the second error detection unit 222b may be caused to detect some jitter errors as the rising edge error Sd _ u and/or the falling edge error Sd _ d due to jitter of the first delay signal S1 and/or the output signal Sext. To address this issue, in some embodiments, the error compensation circuit 220 of the present invention further includes a first counting unit 225a and a second counting unit 225b, as shown in fig. 4.
Fig. 4 is a schematic structural diagram of a battery impedance measuring system according to another embodiment of the present invention. In the embodiment shown in fig. 4, the first error detecting unit 222a sends the detected rising edge error Sd _ u to the first counting unit 225a, the first counting unit 225a counts the number of the received rising edge errors Sd _ u, and when the number is found to reach a first threshold, the first counting unit 225a sends the rising edge error Sd _ u to the first error compensating unit 223a. Referring to fig. 4, the first counting unit 225a of this embodiment is further connected to a first register 226a, and the first register 226a is configured to register the number of rising edge errors Sd _ u obtained by the first counting unit 225a, and send the rising edge errors Sd _ u to the first error compensation unit 223a only when the number of rising edge errors Sd _ u reaches a first threshold.
Similarly, the second error detecting unit 222b sends the detected falling edge error Sd _ d to the second counting unit 225b, and the second counting unit 225b counts the number of the received falling edge errors Sd _ d, and when the number is found to reach a second threshold, the second counting unit 225b sends the falling edge error Sd _ d to the second error compensating unit 223b. Referring to fig. 4, the second counting unit 225b of this embodiment is further connected to a second register 226b, and the second register 226b is used for registering the number of the falling edge errors Sd _ d obtained by the second counting unit 225b, and sending the falling edge errors Sd _ d to the second error compensation unit 223b only when the number of the falling edge errors Sd _ d reaches a second threshold value.
In some embodiments, the first threshold and the second threshold are two fixed values. Only when the counting results of the first counting unit 225a and the second counting unit 225b reach the first threshold and the second threshold, respectively, the output results of the first register 226a and the second register 226b are updated once, so that the error compensation caused by the jitter of the signal can be avoided.
In the embodiment shown in fig. 3 and 4, the first error detection unit 222a detects a falling edge error Sd _ d of the output signal Sext, and the second error detection unit 222b detects a rising edge error Sd _ u of the output signal Sext. In other embodiments, the rising edge error Sd _ u of the output signal Sext may be detected by the first error detection unit 222a, and the falling edge error Sd _ d of the output signal Sext may be detected by the second error detection unit 222b.
In one embodiment, the clock period of the battery impedance measurement system 200 of the present invention is assumed to be 62.5ns. If the count result obtained by the first register 226a and the count result obtained by the second register 226b are 13 and 8 respectively as measured by the error compensation circuit 220 of the present invention, the detected rising edge error Sd _ u of the output signal Sext is 13 × 62.5=812.5ns, and the detected falling edge error Sd _ d is 8 × 62.5=500ns.
The first and second error compensation units 223a and 223b compensate for rising and falling edges of a signal input to the external element 230, respectively, according to the count results obtained from the first and second registers 226a and 226b, thereby canceling distortion of the signal due to the external element 230.
Referring to fig. 4, the first error compensation unit 223a obtains a compensated first compensation signal Sc1 from the count result of the first register 226a and the input signal S, the first compensation signal Sc1 representing the compensated rising edge signal. The second error compensation unit 223b obtains a compensated second compensation signal Sc2 from the count result of the second register 226b and the input signal S, the second compensation signal Sc2 representing the compensated falling edge signal. When the rising edge signal of the first compensation signal Sc1 is sent to the external component 230 through the output control unit 224, the external component 230 is turned on; when the falling edge signal of the second compensation signal Sc2 is sent to the external component 230 through the output control unit 224, the external component 230 is turned off. The output control unit 224 controls the first compensation signal Sc1 and the second compensation signal Sc2 to be alternately connected to the external component 230, and accordingly, the external component 230 is turned on or off.
Fig. 5 is a schematic diagram of signals compensated by the error compensation circuit according to an embodiment of the invention. Fig. 5 shows, from top to bottom, the output signal Sext, the control signal Sc, the Gate current (Gate current) of the external element 230, and the MOS current (MOS current) of the external element 230. The output signal Sext is a voltage signal (VR) measured from a connection point of the resistor 231 and the external element 230, and the control signal Sc is a gate voltage (gate) measured from a gate of the external element 230. Referring to fig. 5, after passing through the error compensation circuit 220 of the present invention, the gate voltage of the external device 230 and the rising edge and the falling edge of the MOS current are almost vertical, and the duty ratios of the two signals reach 50% in an ideal state, and no offset occurs. Therefore, the error compensation circuit 220 of the present invention compensates for the rising edge and falling edge signals, respectively.
In some embodiments, the battery impedance measurement circuit is provided in an integrated circuit chip, and the error compensation circuit of the present invention is adapted to be integrated in an integrated circuit chip including the battery impedance measurement circuit.
Referring to fig. 3, an additional delay unit T1 is further included in the battery impedance measuring system 200 of the present invention. The additional delay unit T1 is configured to delay the input signal S generated by the signal generator 210 by a certain time to obtain a delay signal S2, and input the delay signal S2 to the impedance measuring circuit 250. The processing circuit 260 may include an analog-to-digital conversion unit ADC, a delay unit, a CIC filter (a Cascaded integrator-comb filter), and the like, and processes the error-compensated output signal next to obtain a processed output signal next 1.
Referring to fig. 1 and fig. 3, the impedance measuring circuit 250 may be, for example, the measuring circuit 120 shown in fig. 1, an FFT/DFT circuit, which includes a multiplier and other modules, and may input the delay signal S2 and the processed output signal next 1 into the impedance measuring circuit 250, so as to calculate the real part (Zreal) and imaginary part (Zimag) of the impedance Z of the external battery 240 to be measured.
In addition, referring to fig. 1, the battery impedance measuring system 200 of the present invention may further include a corresponding analog-to-digital conversion unit ADC, a corresponding digital-to-analog conversion unit DAC, and the like. Those skilled in the art may add other electronic elements, functional modules, etc. on the basis of the idea of the invention.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure of the embodiments of the invention is provided merely as an example and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such alterations, modifications, and improvements are intended to be suggested herein and are intended to be within the spirit and scope of the exemplary embodiments of this application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (11)
1. An error compensation circuit, wherein an input signal of the error compensation circuit has a rising edge and a falling edge, and the error compensation circuit is connected to an external component for compensating an error caused by the external component, the error compensation circuit comprising: the device comprises a delay unit, a first error detection unit, a second error detection unit, a first error compensation unit, a second error compensation unit and an output control unit; wherein the content of the first and second substances,
the delay unit is used for delaying the input signal for a fixed time to generate a first delay signal;
the first error detection unit is used for comparing the first delay signal with an output signal of the external component to detect a rising edge error of the output signal, and the second error detection unit is used for comparing the first delay signal with the output signal of the external component to detect a falling edge error of the output signal;
the first error compensation unit is used for generating a first compensation signal according to the rising edge error and the input signal, and the second error compensation unit is used for generating a second compensation signal according to the falling edge error and the input signal; and
the output control unit is used for controlling the error compensation circuit to output the first compensation signal or the second compensation signal.
2. The circuit of claim 1, further comprising a first counting unit to count rising edge errors detected by the first error detection unit and a second counting unit to count falling edge errors detected by the second error detection unit.
3. The circuit of claim 2, wherein the first counting unit includes a first register for registering the number of rising edge errors and the second counting unit includes a second register for registering the number of falling edge errors.
4. The circuit of claim 2, wherein the first counting unit sends the number of rising edge errors to the first error compensation unit when the number of rising edge errors reaches a first threshold; and when the number of the falling edge errors reaches a second threshold value, the second counting unit is used for sending the number of the falling edge errors to the second error compensation unit.
5. The circuit of claim 1, wherein the first error detection unit and/or the second error detection unit is a phase frequency detector.
6. The circuit of claim 1, wherein the fixed time delay is 2 microseconds.
7. The circuit of claim 1, wherein the output control unit is a switching circuit.
8. The circuit of claim 1, wherein the input signal is a square wave.
9. The circuit of claim 1, wherein the output signal is connected to an external battery and is used to measure an impedance of the external battery.
10. The circuit of claim 1, wherein the error compensation circuit is adapted to be integrated in a battery impedance measurement circuit.
11. A battery impedance measurement system comprising an error compensation circuit according to any one of claims 1 to 10.
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| CN202010567832.7A CN113820612B (en) | 2020-06-19 | 2020-06-19 | Error compensation circuit and integrated circuit for measuring battery impedance |
| PCT/CN2021/086090 WO2021253934A1 (en) | 2020-06-19 | 2021-04-09 | Error compensation circuit, and integrated circuit for measuring battery impedance |
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| CN202010567832.7A CN113820612B (en) | 2020-06-19 | 2020-06-19 | Error compensation circuit and integrated circuit for measuring battery impedance |
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| CN104702249A (en) * | 2013-12-10 | 2015-06-10 | 苏州普源精电科技有限公司 | Signal generator with burst synchronization function |
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| WO2021253934A1 (en) | 2021-12-23 |
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