CN113811086B - Manufacturing method of ceramic mixed-voltage circuit board - Google Patents
Manufacturing method of ceramic mixed-voltage circuit board Download PDFInfo
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- CN113811086B CN113811086B CN202111016555.1A CN202111016555A CN113811086B CN 113811086 B CN113811086 B CN 113811086B CN 202111016555 A CN202111016555 A CN 202111016555A CN 113811086 B CN113811086 B CN 113811086B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0067—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto an inorganic, non-metallic substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/227—Drying of printed circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a manufacturing method of a ceramic mixed voltage circuit board, which comprises the following steps: the method comprises the steps of first substrate cutting, plate drying, internal light imaging, inner layer etching, inner layer AOI, inner layer drilling, depth control milling, ceramic substrate burying, resin filling, curing, ceramic substrate protection and resin polishing, wherein the depth control depth of the depth control milling is at least 0.15mm larger than the periphery of the ceramic substrate, the height of the ceramic substrate after being buried is lower than the plate surface of the first substrate, and the ceramic substrate is prevented from being stressed during pressing. According to the invention, the ceramic material is used in the local packaging area, and the FR-4 high TG material is used in other areas for mixing and pressing, so that the high thermal conductivity of the packaging area is satisfied, and meanwhile, the good characteristics of good insulativity and small high-frequency loss under high-density assembly are improved.
Description
Technical Field
The invention relates to the technical field of printed circuit boards, in particular to a manufacturing method of a ceramic mixed-voltage circuit board.
Background
The ceramic substrate has good high-frequency performance and electrical performance, and has the performances of high heat conductivity, excellent chemical stability and thermal stability and the like which the organic substrate does not have, and is an ideal packaging material for a new generation of large-scale integrated circuits and power electronic modules.
With the continuous updating of wireless communication, optical fiber communication and high-speed data network products, the high-speed information processing and the modularization of a wireless analog front end are realized, and the high-frequency high-speed circuit board is applied to more and more products. Ceramic substrates with good insulation, low dielectric constant, low loss factor and high thermal conductivity are the materials of choice for the substrate and are considered by many designers. In the age of 5G networks in particular, circuit boards are required to meet the high frequency and high speed of signal transmission. However, the ceramic-based material is expensive, the cost of the whole ceramic-based laminated high-multilayer circuit board is high, and the expansion and contraction mismatch, difficult control of lamination parameters, difficult hole wall metallization and the like are formed due to the differentiation of the whole mixed-pressure thermal expansion coefficients. Meanwhile, the thickness and the size of the ceramic substrate are single, different plate thickness requirements of customers are difficult, and the application amount and the application field are greatly reduced.
Disclosure of Invention
In order to solve the technical problems, the invention provides the following technical scheme:
the invention provides a method for manufacturing a ceramic mixed voltage circuit board,
the method comprises the following steps:
s1: the method comprises the steps of first substrate cutting, drying, internal light imaging, inner layer etching, inner layer AOI, inner layer drilling, depth control milling, ceramic substrate burying, resin filling, curing, ceramic substrate protection and resin polishing, wherein the depth control depth of the depth control milling is at least 0.15mm larger than the periphery of the ceramic substrate, and the height of the ceramic substrate is lower than the plate surface of the first substrate after the ceramic substrate is buried, so that the ceramic substrate is prevented from being stressed during pressing;
s2: cutting a second substrate, drying a plate, performing internal light imaging, etching an inner layer, AOI (argon oxygen decarburization) and drilling an inner layer target;
s3: cutting a third substrate, drying a plate, performing internal light imaging, etching an inner layer, AOI (argon oxygen decarburization) of the inner layer and drilling an inner layer target;
s4: fourth substrate cutting, drying plate, internal light imaging, internal etching, internal AOI and internal drilling target;
s5: fifth substrate cutting, drying, internal light imaging, internal etching, internal AOI and internal drilling target;
s6: after the flow of the five substrates from S1 to S5 is finished, the substrates and the prepregs are laminated together in a lamination mode.
Optionally, the method further comprises the steps of:
s7: the substrate laminated by the S6 sequentially comprises the following manufacturing processes:
drilling, plasma, copper deposition, negative film electroplating, external light imaging, external light inspection, external layer etching, external layer AOI, printing and welding resistance, welding resistance imaging, characters, nickel palladium gold, appearance and electric measurement, wherein the drilling is set as laser drilling, the drilling is performed on a substrate by using short pulse and high-peak power laser so as to achieve the process of gathering high-density energy, removing materials and forming a through hole, and a ceramic substrate region is deeply drilled by using blind holes, wherein the through layer is between a first substrate and a third substrate.
Optionally, the first substrate, the second substrate, the third substrate, the fourth substrate and the fifth substrate are all FR-4 substrates.
Optionally, the baking plate flow in the step S1-S5 is 170 ℃ for 4 hours and high-temperature baking is performed;
the internal light imaging flow in the steps S1-S5 is to paste a dry film or a wet film for pattern transfer;
the inner layer etching process in the steps S1-S5 is to remove the unexposed area through chemical liquid medicine and keep the wires for connection;
the inner layer AOI flow in the S1-S5 steps is obtained by comparing patterns, and defective defects are checked;
the inner layer drilling target process in the S1-S5 steps is used for aligning the laminated rivets of the multilayer substrate.
Optionally, the resin pore-filling procedure in the step S1 is as follows: filling gaps between the embedded ceramic substrate and the first substrate by using flowable epoxy resin in a vacuum environment, ensuring the tight combination of the gaps, and simultaneously, not allowing the defects of bubbles, holes, cracks and the like;
the curing process in the step S1 is as follows: and (3) baking the flowable resin, wherein the parameters are 150 ℃ for 2 hours, and the state of the flowable resin is semi-cured, so that the flowable resin is convenient for polishing in the subsequent process.
The ceramic substrate protection flow in the step S1 is as follows: the wear-resistant soft rubber is used for protecting the ceramic substrate area, so that the ceramic plate surface is prevented from being rubbed by the grinding brush during grinding;
the resin polishing process in the step S1 is as follows: the surface of the cured resin adhesive is cleaned by using cloth, and the resin is polished to remove accumulated resin and ensure the flatness of the resin adhesive because of a semi-cured state.
Optionally, the plasma flow in the step S7 is: and the hole wall is activated and cleaned in a vacuum environment, so that the preparation for the subsequent copper deposition hole wall metallization is facilitated.
The copper deposition flow in the step S7 is as follows: carrying out chemical copper deposition on the hole wall;
the negative film electroplating process in the step S7 is as follows: using a continuous vertical plating line to carry out hole plating on the hole wall, wherein the process needs to meet the requirement that the thickness of hole copper is more than or equal to 25 mu m; the copper thickness of the surface is more than or equal to 35 mu m;
the external light imaging flow in the step S7 is as follows: pasting a dry film for pattern transfer;
the outer layer etching process in the step S7 is as follows: removing the unexposed areas by chemical solution, and retaining the wires for connection;
the solder mask printing process in the step S7 is as follows: the surface wire part is printed with ink, so that the effect of protecting the plate surface and insulating is achieved;
the solder mask imaging process in the step S7 is as follows: removing PAD ink to be welded through chemical liquid medicine, and reserving the ink in other areas;
the character flow in the step S7 is as follows: the part of the board surface, which needs to be pasted with the piece, is marked with characters, so that the device can be conveniently identified;
the nickel-palladium-gold flow in the step S7 is as follows: the surface of the bonding pad to be welded is coated with nickel-palladium-gold, so that the bonding wires between the ceramic substrate and the FR-4 substrate are conveniently bonded while the surface oxidation is prevented
The appearance flow in the step S7 is as follows: cutting the produced substrate into a size required by a customer by using a mechanical milling cutter;
the electrical measurement flow in the step S7 is as follows: the functionality is tested, and the phenomenon of open and short circuit is mainly prevented.
Optionally, the lamination in the step S6 is performed by laminating the substrate at a high temperature under a vacuum environment.
The invention has the beneficial effects that
The invention uses ceramic material in local packaging area, and FR-4 high TG material in other areas to mix pressure, while meeting the high heat conductivity of semiconductor in packaging area, improving the good property of good insulation and small high frequency loss in high density assembly, and simultaneously solving the requirements of high cost and different thickness.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention.
FIG. 2 is a schematic diagram of the nickel-palladium-gold flow scheme of the present invention.
Reference numerals illustrate: 1-a first substrate, 2-a second substrate, 3-a third substrate, 4-a fourth substrate, 5-a fifth substrate, 6-a ceramic substrate, 7-a flowable epoxy resin, 8-a prepreg,
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples
As shown in fig. 1-2, the present invention provides a method for manufacturing a ceramic mixed voltage circuit board,
the method comprises the following steps:
s1: the method comprises the steps of first substrate 1 cutting, drying, internal light imaging, internal layer etching, internal layer AOI, internal layer drilling, depth control milling, ceramic substrate 6 burying, resin filling, curing, ceramic substrate 6 protecting and resin polishing, wherein the depth control depth of the depth control milling is at least 0.15mm larger than the periphery of the ceramic substrate 6, the height of the ceramic substrate 6 after being buried is lower than the surface of the first substrate 1, and the ceramic substrate 6 is prevented from being stressed during pressing;
s2: cutting the second substrate 2, drying a plate, performing internal light imaging, etching an inner layer, performing AOI on the inner layer and performing inner layer drilling;
s3: cutting the third substrate 3, drying a plate, performing internal light imaging, etching an inner layer, performing AOI on the inner layer and performing inner layer drilling;
s4: cutting the fourth substrate 4, drying a plate, performing internal light imaging, etching an inner layer, performing AOI on the inner layer and performing inner layer drilling;
s5: cutting the fifth substrate 5, drying a plate, performing internal light imaging, etching an inner layer, performing AOI on the inner layer and performing inner layer drilling;
s6: after the flow of the five substrates from S1 to S5 is finished, laminating the substrates and the prepreg 8 together in a laminating mode;
the baking plate flow in the steps S1-S5 is 170 ℃ for 4 hours and high-temperature baking is carried out;
the internal light imaging flow in the steps S1-S5 is to paste a dry film or a wet film for pattern transfer;
the inner layer etching process in the steps S1-S5 is to remove the unexposed area through chemical liquid medicine and keep the wires for connection;
the inner layer AOI flow in the S1-S5 steps is obtained by comparing patterns, and defective defects are checked;
the inner layer drilling target flow in the S1-S5 steps is used for aligning the laminated rivets of the multilayer substrate;
the resin pore-filling flow in the step S1 is as follows: filling gaps between the embedded ceramic substrate 6 and the first substrate 1 by using the flowable epoxy resin 7 in a vacuum environment, ensuring the tight combination of the gaps, and simultaneously, not allowing the defects of bubbles, hollows, cracks and the like;
the curing process in the step S1 is as follows: and (3) baking the flowable resin, wherein the parameters are 150 ℃ for 2 hours, and the state of the flowable resin is semi-cured, so that the flowable resin is convenient for polishing in the subsequent process.
The protection flow of the ceramic substrate 6 in the step S1 is as follows: the wear-resistant soft rubber is used for protecting the area of the ceramic substrate 6, so that the ceramic plate surface is prevented from being rubbed by a grinding brush during grinding;
the resin polishing process in the step S1 is as follows: the surface of the cured resin adhesive is cleaned by using cloth, and the resin is polished to remove accumulated resin and ensure the flatness of the resin adhesive in a semi-cured state;
laminating in the step S6, wherein the substrates are laminated at high temperature in a vacuum environment;
the method further comprises the steps of:
s7: the substrate laminated by the S6 sequentially comprises the following manufacturing processes:
drilling, plasma, copper deposition, negative film electroplating, external light imaging, external light inspection, external layer etching, external layer AOI, printing and welding resistance, welding resistance imaging, characters, nickel palladium gold, appearance and electric measurement, wherein the drilling is set as laser drilling, the drilling is performed on a substrate by using short pulse and high-peak power laser so as to achieve the process of gathering high-density energy, removing materials and forming a through hole, a ceramic substrate 6 region is deeply drilled by using blind holes, and the through layer is between a first substrate 1 and a third substrate 3;
the first substrate 1, the second substrate 2, the third substrate 3, the fourth substrate 4 and the fifth substrate 5 are all FR-4 substrates;
the plasma flow in the step S7 is as follows: and the hole wall is activated and cleaned in a vacuum environment, so that the preparation for the subsequent copper deposition hole wall metallization is facilitated.
The copper deposition flow in the step S7 is as follows: carrying out chemical copper deposition on the hole wall;
the negative film electroplating process in the step S7 is as follows: using a continuous vertical plating line to carry out hole plating on the hole wall, wherein the process needs to meet the requirement that the thickness of hole copper is more than or equal to 25 mu m; the copper thickness of the surface is more than or equal to 35 mu m;
the external light imaging flow in the step S7 is as follows: pasting a dry film for pattern transfer;
the outer layer etching process in the step S7 is as follows: removing the unexposed areas by chemical solution, and retaining the wires for connection;
the solder mask printing process in the step S7 is as follows: the surface wire part is printed with ink, so that the effect of protecting the plate surface and insulating is achieved;
the solder mask imaging process in the step S7 is as follows: removing PAD ink to be welded through chemical liquid medicine, and reserving the ink in other areas;
the character flow in the step S7 is as follows: the part of the board surface, which needs to be pasted with the piece, is marked with characters, so that the device can be conveniently identified;
the nickel-palladium-gold flow in the step S7 is as follows: the surface of the bonding pad to be welded is coated with nickel-palladium-gold, so that the bonding wires between the ceramic substrate 6 and the FR-4 substrate are conveniently bonded while the surface oxidation is prevented
The appearance flow in the step S7 is as follows: cutting the produced substrate into a size required by a customer by using a mechanical milling cutter;
the electrical measurement flow in the step S7 is as follows: the functionality is tested, and the phenomenon of open and short circuit is mainly prevented;
the invention uses ceramic material in local packaging area, and FR-4 high TG material in other areas to mix pressure, while meeting the high heat conductivity of the semiconductor in packaging area, improving the good characteristics of good insulation and small high frequency loss in high density assembly, and simultaneously solving the requirements of high cost and different thickness.
Finally, it should be noted that: the foregoing description is only illustrative of the preferred embodiments of the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements or changes may be made without departing from the spirit and principles of the present invention.
Claims (6)
1. A method for manufacturing a ceramic mixed voltage circuit board is characterized in that,
the method comprises the following steps:
s1: the method comprises the steps of first substrate cutting, drying, internal light imaging, inner layer etching, inner layer AOI, inner layer drilling, depth control milling, ceramic substrate burying, resin filling, curing, ceramic substrate protection and resin polishing, wherein the depth control depth of the depth control milling is at least 0.15mm larger than the periphery of the ceramic substrate, and the height of the ceramic substrate is lower than the plate surface of the first substrate after the ceramic substrate is buried, so that the ceramic substrate is prevented from being stressed during pressing;
s2: cutting a second substrate, drying a plate, performing internal light imaging, etching an inner layer, AOI (argon oxygen decarburization) and drilling an inner layer target;
s3: cutting a third substrate, drying a plate, performing internal light imaging, etching an inner layer, AOI (argon oxygen decarburization) of the inner layer and drilling an inner layer target;
s4: fourth substrate cutting, drying plate, internal light imaging, internal etching, internal AOI and internal drilling target;
s5: fifth substrate cutting, drying, internal light imaging, internal etching, internal AOI and internal drilling target;
s6: after the flow of the five substrates from S1 to S5 is finished, laminating the substrates and the prepregs together in a laminating mode;
the method further comprises the steps of:
s7: the substrate laminated by the S6 sequentially comprises the following manufacturing processes:
drilling, plasma, copper deposition, negative film electroplating, external light imaging, external light inspection, external layer etching, external layer AOI, printing and welding resistance, welding resistance imaging, characters, nickel palladium gold, appearance and electric measurement, wherein the drilling is set as laser drilling, the drilling is performed on a substrate by using short pulse and high-peak power laser so as to achieve the process of gathering high-density energy and removing materials to form a through hole, and a ceramic substrate region is drilled by using blind holes in a depth-controlled manner, wherein the through layer is between the first substrate and the third substrate.
2. The method for manufacturing a ceramic mixed voltage circuit board according to claim 1, wherein,
the first substrate, the second substrate, the third substrate, the fourth substrate and the fifth substrate are all FR-4 substrates.
3. The method for manufacturing a ceramic mixed voltage circuit board according to claim 1, wherein,
the baking plate flow in the steps S1-S5 is 170 ℃ for 4 hours and high-temperature baking is carried out;
the internal light imaging flow in the steps S1-S5 is to paste a dry film or a wet film for pattern transfer;
the inner layer etching process in the steps S1-S5 is to remove the unexposed area through chemical liquid medicine and keep the wires for connection;
the inner layer AOI flow in the S1-S5 steps is obtained by comparing patterns, and defective defects are checked;
the inner layer drilling target process in the S1-S5 steps is used for aligning the laminated rivets of the multilayer substrate.
4. The method for manufacturing a ceramic mixed voltage circuit board according to claim 1, wherein,
the resin pore-filling flow in the step S1 is as follows: filling gaps between the embedded ceramic substrate and the first substrate by using flowable epoxy resin in a vacuum environment, ensuring the tight combination of the gaps, and simultaneously, not allowing the defects of bubbles, holes, cracks and the like;
the curing process in the step S1 is as follows: baking the flowable resin for 2 hours at the temperature of 150 ℃ in a semi-cured state, so that the polishing in the subsequent process is facilitated;
the ceramic substrate protection flow in the step S1 is as follows: the wear-resistant soft rubber is used for protecting the ceramic substrate area, so that the ceramic plate surface is prevented from being rubbed by the grinding brush during grinding;
the resin polishing process in the step S1 is as follows: the surface of the cured resin adhesive is cleaned by using cloth, and the resin is polished to remove accumulated resin and ensure the flatness of the resin adhesive because of a semi-cured state.
5. The method for manufacturing a ceramic mixed voltage circuit board according to claim 1, wherein,
the plasma flow in the step S7 is as follows: activating and cleaning the hole wall in a vacuum environment, so that the subsequent copper deposition hole wall metallization is convenient to prepare;
the copper deposition flow in the step S7 is as follows: carrying out chemical copper deposition on the hole wall;
the negative film electroplating process in the step S7 is as follows: using a continuous vertical plating line to carry out hole plating on the hole wall, wherein the process needs to meet the requirement that the thickness of hole copper is more than or equal to 25 mu m; the copper thickness of the surface is more than or equal to 35 mu m;
the external light imaging flow in the step S7 is as follows: pasting a dry film for pattern transfer;
the outer layer etching process in the step S7 is as follows: removing the unexposed areas by chemical solution, and retaining the wires for connection;
the solder mask printing process in the step S7 is as follows: the surface wire part is printed with ink, so that the effect of protecting the plate surface and insulating is achieved;
the solder mask imaging process in the step S7 is as follows: removing PAD ink to be welded through chemical liquid medicine, and reserving the ink in other areas;
the character flow in the step S7 is as follows: the part of the board surface, which needs to be pasted with the piece, is marked with characters, so that the device can be conveniently identified;
the nickel-palladium-gold flow in the step S7 is as follows: the surface of the bonding pad to be welded is coated with nickel-palladium-gold, so that the bonding wires between the ceramic substrate and the FR-4 substrate are conveniently bonded while the surface oxidation is prevented;
the appearance flow in the step S7 is as follows: cutting the produced substrate into a size required by a customer by using a mechanical milling cutter;
the electrical measurement flow in the step S7 is as follows: the functionality is tested, and the phenomenon of open and short circuit is mainly prevented.
6. The method for manufacturing a ceramic mixed voltage circuit board according to claim 1, wherein,
and (3) laminating in the step S6, wherein the substrates are laminated at high temperature in a vacuum environment.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006303055A (en) * | 2005-04-19 | 2006-11-02 | Murata Mfg Co Ltd | Multilayer ceramic substrate and manufacturing method thereof |
| CN107911937A (en) * | 2017-11-10 | 2018-04-13 | 生益电子股份有限公司 | The production method and PCB of a kind of PCB |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006303055A (en) * | 2005-04-19 | 2006-11-02 | Murata Mfg Co Ltd | Multilayer ceramic substrate and manufacturing method thereof |
| CN107911937A (en) * | 2017-11-10 | 2018-04-13 | 生益电子股份有限公司 | The production method and PCB of a kind of PCB |
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