CN113810636B

CN113810636B - Logic circuit capable of improving image transmission efficiency based on FPGA chip design

Info

Publication number: CN113810636B
Application number: CN202111112566.XA
Authority: CN
Inventors: 陶亚雄
Original assignee: Chongqing College of Electronic Engineering
Current assignee: Chongqing College of Electronic Engineering
Priority date: 2021-09-23
Filing date: 2021-09-23
Publication date: 2023-06-20
Anticipated expiration: 2041-09-23
Also published as: CN113810636A

Abstract

The invention relates to the technical field of logic circuits, in particular to a logic circuit capable of improving image transmission efficiency based on an FPGA chip design, which comprises an FPGA control circuit and an FPGA peripheral circuit, wherein the FPGA peripheral circuit is provided with an FPGA_CAM_DN0, an FPGA_CAM_DP0, an FPGA_CAM_DN1, an FPGA_CAM_DP1, an FPGA_CAM_CN, an FPGA_CAM_CP, an FPGA_CAM_RST, an FPGA_CAM_GPIO, an FPGA_CAM_SCL, an FPGA_CAM_SDA and a VCC_3V.3, the logic circuit is designed as a main innovation point to apply for the cooperative work among a CMOS module, an MIPI CSI-2 module, a data conversion and display control module by taking the FPGA as a main signal processing center, and the stable work of each module can realize the stable and high-quality stable transmission of image signals.

Description

Logic circuit capable of improving image transmission efficiency based on FPGA chip design

Technical Field

The invention relates to the technical field of logic circuits, in particular to a logic circuit which is designed based on an FPGA chip and can improve image transmission efficiency.

Background

Image sensors have recently become a focus of market attention as "eyes" for electronic devices, and are becoming a hotspot in the semiconductor industry. At present, the image sensors which are commonly used are a CCD image sensor (Charge-coupled Device) and a CMOS image chip, and the CMOS image chip gradually replaces the CCD image sensor with the advantages of lower power consumption, better photosensitive performance, higher integration level and the like, so that the CMOS image sensor becomes a mainstream image acquisition Device. Since the invention of CMOS image chips until the beginning of the 21 st century, research on the design of FPGA-based CMOS image chip control circuits has mostly employed DVP parallel interfaces. However, as the pixel density of the image chip increases, the upper limit of the transmission rate of the DVP parallel interface also has a larger influence on the image display performance. Subsequently, MIPI (Mobile Industry Processor Interface) alliance promulgates MIPI CSI-2 protocol that is specifically applied to high definition, high frame rate camera head end data transmission. The interface adopts high-speed low-voltage differential signals and has advanced architecture design, and provides more choices and greater support for developers, manufacturers and final consumers while maintaining the advantages of standard interfaces.

Currently, MIPI-DSI based ASIC (Application Specific Integrated Circuit ) solutions are relatively expensive and are not sufficiently heterogeneous to fully meet the increasingly diverse market demands. In this context, FPGAs with circuit programmable characteristics have become an ideal alternative. Many FPGA vendors and third party IP (Intellectual Property ) vendors have introduced their own IP core solutions to the market. FPGA manufacturer Ledi provides MIPI-CSI transceiver IP core, can configure own FPGA as the bridge between application processor and camera, realize traditional CMOS level signal to MIPI-CSI signal conversion [3]. Xilinx and their cooperating high-cascade alliance members Northwest Logic and Xylon propose a Xilinx FPGA-based low-cost MIPI interface IP that is optimized for cost-sensitive video displays and cameras.

Disclosure of Invention

The invention aims to provide a logic circuit capable of improving image transmission efficiency based on an FPGA chip design, which comprises an FPGA control circuit and an FPGA peripheral circuit, wherein the FPGA peripheral circuit is provided with an FPGA_CAM_DN0, an FPGA_CAM_DP0, an FPGA_CAM_DN1, an FPGA_CAM_DP1, an FPGA_CAM_CN, an FPGA_CAM_CP, an FPGA_CAM_RST, an FPGA_CAM_GPIO, an FPGA_CAM_SCL, an FPGA_CAM_SDA and a VCC_3V3, the FPGA_CAM_DN1 and the FPGA_CAM_DP1 are connected to a clock channel of a CSI-2 interface, the FPGA_CAM_DN0 and the FPGA_CAM_DP1 are connected to a data channel Lane2 of the CSI interface, the FPGA_CAM_SCL and the FPGA_CAM_SDA are connected to SCCB bus ports of a CMOS image chip, the FPGA_CAM_RST is connected to a hardware reset end of the CMOS image chip, a terminal impedance of 150 omega is connected to a terminal of the differential signal port, the FPGA_CAM_DN1 and the FPGA_CAM_DPD1 is connected to a terminal of the VCC_C3, and the FPGA_C3 is connected to the other end of the VCC_C3 through a VCC_C3 resistor, and the FPGA_C3 is connected to the other end of the VCC 3 resistor is connected to the VCC 3 resistor, and the other end of the VCC is connected to the VCC 3 resistor is connected to the power resistor, and the VCR is connected to the other end of the VCC resistor, and the VCR is connected to the VCR 3.

Preferably, the FPGA control circuit adopts a D-PHY protocol at a physical layer, and an interface of the FPGA control circuit adopts a high-speed LSVS differential signal to carry out image transmission.

Preferably, the FPGA control circuit adopts an XC7S15 series chip, and the logic resource of the FPGA control circuit reaches 12K.

Preferably, the development Board adopted by the FPGA peripheral circuit is an edge acceleration Xilinx development Board Spartan Edge Accelerator Board and SEA Board, and the development Board integrates the necessary FPGA peripheral circuit, MIPI CSI interface and mini HDMI interface.

Preferably, the logic function is realized by using the MIPI CSI interface of the platform and the FPGA chip.

Compared with the prior art, the invention has the beneficial effects that: in a large image display environment, the logic circuit design is taken as a main innovation point, the whole logic circuit system is applied to take an FPGA as a main signal processing center, the CMOS module, the MIPI CSI-2 module and the data conversion and display control module work cooperatively, the CMOS driving and configuration module can capture image information, and the stable work of each module can realize the stable and high-quality stable transmission of picture signals.

Drawings

FIG. 1 is a schematic diagram of a development board structure;

FIG. 2 is a schematic diagram of a CSI interface pin;

FIG. 3 is a general circuit scheme frame diagram;

FIG. 4 is a power-on timing diagram of OV 5647;

FIG. 5 is a power-on timing diagram;

FIG. 6 is a diagram of a simulation of a configuration OV5647 register;

fig. 7 is an OV5647 configured board level debug engine.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the technical solutions of the present invention, all other embodiments obtained by a person skilled in the art without making any creative effort fall within the protection scope of the present invention.

Referring to fig. 1 to 7, the present invention provides a technical solution: the logic circuit capable of improving image transmission efficiency based on the design of an FPGA chip comprises an FPGA control circuit and an FPGA peripheral circuit, wherein the FPGA peripheral circuit is provided with an FPGA_CAM_DN0, an FPGA_CAM_DP0, an FPGA_CAM_DN1, an FPGA_CAM_DP1, an FPGA_CAM_CN, an FPGA_CAM_CP, an FPGA_CAM_RST, an FPGA_CAM_GPIO, an FPGA_CAM_SCL, an FPGA_CAM_SDA and a VCC_3V3, the FPGA_CAM_DN1 and the FPGA_CAM_DP1 are connected to clock channels of a CSI-2 interface, the FPGA_CAM_DN0 and the FPGA_CAM_DP1 are connected to data channels Lane2 of the CSI interface, the FPGA_CAM_SCL and the FPGA_CAM_CAM_SCB are connected to SCCB bus ports of the CMOS image chip, the FPGA_CAM_SCM_SCL is connected to hardware reset terminals of the image chip, terminal impedances of 150 omega are connected to the differential signal ports, the peripheral circuit is provided with two VCC_3 and VCC_C3 is connected to one end of the VCC_C3, and the other end of the VCC_C3 is connected to the other end of the VCC resistor of the CSI-3 through the VCC_CsC3 resistor, and the VCC_C3 is connected to the VCC-C3 is connected to the other end of the VCC resistor of the VCC-C3.

The physical layer adopts a D-PHY protocol, and an interface of the physical layer adopts a high-speed LSVS differential signal to carry out image transmission. Although the common FPGA chip IO resource only supports LVDS level standards (low voltage differential signaling ), the level standards are not matched, when the transmission rate is smaller than 800Mbit/s, the LSVS signal can be converted into an LVDS signal by using a bridge resistor network for being received and processed by the FPGA end. The spar-7 series FPGA of Xilinx has logic cells up to 102K using the 28nm technology of TSMC. The transmission rate of the LVDS differential signals supported by the IO resources can reach 1.25Gb/s. The built-in clock management resource (Clock Management Tile, CMT) integrates a phase locked loop (Phase Locked Loop, PLL) and mixed mode clock manager (Mixed Mode Clock Manager, MMCM) module to provide high quality clocks for developers. The Spartan-7 series FPGA has the advantages of low price, low power consumption, small volume and the like, and is very suitable for middle-low end application. The XC7S15 series chip is adopted, the logic resource reaches 12K, and the design requirement can be met theoretically.

The development Board employed was an edge acceleration Xilinx development Board (Spartan Edge Accelerator Board, SEA Board). The development board integrates necessary FPGA peripheral circuits, MIPI CSI interfaces, mini HDMI interfaces and the like.

FPGA and CSI interface connection pin description

Pin number	Pin name	Chip pin	Description of the invention
				1，4，7，10	Without any means for	Without any means for	Grounded (earth)
2	FPGA_CAM_DN0	J12	CSI data No. 1 channel N pole pin
				3	FPGA_CAM_DP0	J11	CSI data No. 1 channel P pole pin
5	FPGA_CAM_DN1	P11	CSI data No. 2 channel N pole pin
				6	FPGA_CAM_DP1	P10	CSI data No. 2 channel P pole pin
8	FPGA_CAM_CN	F11	CSI clock channel N pole pin
				9	FPGA_CAM_CP	G11	CSI clock channel N pole pin
11	FPGA_CAM_RST	M12	CMOS image chip reset terminal
				12	FPGA_CAM_GPIO	F13	CMOS image chip expanding terminal
13	FPGA_CAM_SCL	K11	SIO_C port
				14	FPGA_CAM_SDA	K12	SIO_D port
15	VCC_3V3	Without any means for	3.3V power supply

The OV5647 image chip interface circuit design adopts a Raspberry Pi generation camera, the camera uses an OV5647 image chip as an image signal source, a 24Mhz crystal oscillator is built in a circuit board, a power supply driving chip and image data are led out through a 15pin flexible flat cable, and the interface uses a special CSI interface which is specially designed for being connected to the camera. The following table describes the CSI interface of the camera.

Raspberry Pi Camera Pin description

Pin number	Pin name	Description of the invention
			1	DGND	Grounded (earth)
2	CAM_D0_N	CSI data No. 1 channel N pole pin
			3	CAM_D0_P	CSI data No. 1 channel P pole pin
4	DGND	Grounded (earth)
			5	CAM_D1_N	CSI data No. 2 channel N pole pin
6	CAM_D1_P	CSI data No. 2 channel P pole pin
			7	DGND	Grounded (earth)
8	CAM_C_N	CSI clock channel N pole pin
			9	CAM_C_P	CSI clock channel P pole pin
10	DGND	Grounded (earth)
			11	POWER_EN	Power-on enable
12	LEN_EN	Flash enable
			13	SCL	SCCB clock line
14	SDA	SCCB data line
			15	+3.3V	Power supply

The circuit system takes the FPGA as a core and comprises a CMOS driving and configuring module, an MIPI CSI-2 data receiving module and a data conversion and display control module. The test phase computer writes the program onto the FPGA through JTAG, when the system is powered on and the FLASH loads the PROM program onto the FPGA, the CMOS control module controls the power-on sequence of driving signals of DOVDD, AVDD, DVDD, PWDN and the like, the SCCB bus is used for configuring 86 8-bit registers in the CMOS, the MIPI CSI-2 data receiving module is used for receiving 2 paths of differential data output by the CMOS and analyzing the internal image pixel data, the data conversion and display module acquires the image data output by the upper receiving module, processes such as data conversion and control of mini HDMI interface output and the like, and finally the display displays the image captured by the CMOS in real time.

The CMOS image chip driving control module is used for realizing the power-on and configuration functions of the OV5647 image chip, so that the CMOS image chip can work normally, the correct power-on time sequence is provided, the normal work of the image chip is ensured, an SCCB bus control circuit is realized, and the parameter configuration is carried out on the CMOS image chip through the interface.

The power-on time sequence is required by the OV5647 dataset, wherein DOVDD, AVDD, DVDD is respectively interface circuit voltage, analog circuit power supply voltage and digital circuit power supply voltage, and the three signals are powered on simultaneously or sequentially to enable the OV5647 image chip to work normally. And secondly, PWDN is an effective power-down signal with high level, and the PWDN can be made to be low after the power supply voltage is required to be stable for at least 5ms by adopting an asynchronous design, and finally, after the PWND is stable for 20ms, the OV5647 can be configured by an SCCB. Because the raspberry-based camera module used in the project is integrated with the POWER supply module, and the power_EN signal is used in the module to replace the PWDN signal, the POWER supply module is high-level and effective. The design of the level conversion circuit is not needed, and the power-on time sequence is only required to be met after the power-on. To ensure accurate POWER-up, the reset signal triggers the POWER_EN signal to go high 6ms after being sent out, and the configuration enable signal CONFIG_EN is pulled low after 21 ms.

The CMOS image chip register configuration, the built-in parameter registers in the OV5647 for controlling the operation of the image chip, has more than three hundred, wherein most of the parameter settings are related to gain control (AGC), exposure control (AEC), white balance control (AWB), gamma-like positive, background compensation, black level correction, etc. of the image, and can maintain the default values. According to the actual situation, only 80 register values are changed, most registers are kept at default values after power-on, and the CMOS image chip is configured to be 1280 multiplied by 720-resolution MIPI serial interface output, so that the gain and the exposure time are automatically controlled. The relevant register configuration and its meaning are shown in the following table:

table 4.1 ov5647 register configuration information

Register address	Configuration parameters	Description of the invention
			0x3016	0x08	MIPI output interface Enable
0x3036	0xa8	Chip PLL frequency multiplication number
			0x380a	0x05	Image pixel column number (high-order)
0x380b	0x00	Image pixel column number (Low level)
			0x380c	0x02	Image pixel line number (high-order)
0x380d	0xd0	Image pixel line number (high-order)
			0x503d	0x80	Bar graph test on
0x3a08	0x01	Automatic gain adjustment

When the SCCB bus transfer is implemented in the Verilog HDL programming language, SIO_D and SIO_C are generated in a counter controlled manner. At 400khz clock, the time required for a single configuration is 165 clock cycles. For the three-phase write transfer process of a single SCCB bus, state machine circuit programming is used herein for a total of 6 states.

The single configuration simulation waveform sccb_scl is a clock signal, sccb_sda is a data signal, sccb_en is a three-phase write enable signal, and when SCCB is high, the SCCB write timing starts to work; sccb_cfg_done is a configuration complete signal that goes high when all parameters are configured.

The OV5647 power-on control module and the register configuration module are combined to form a CMOS image chip driving configuration module, and in order to verify that the module can be normally powered on and can be correctly configured, the logic analysis debugging is carried out by utilizing a logic analyzer setup debug grabbing signal of Vivado software. According to the development flow of the Xilinx FPGA, the module is synthesized, a bit file is generated, finally the bit file is downloaded to a development board for debugging, and the debugging waveform can clearly see that the data written into the register 0x3018 is correctly read.

It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the technical solution, and although the applicant has described the present invention in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents of the technical solution of the present invention can be made without departing from the spirit and scope of the technical solution, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.

Claims

1. The utility model provides a logic circuit that can promote image transmission efficiency based on FPGA chip design, includes FPGA control circuit and FPGA peripheral circuit, its characterized in that: the FPGA peripheral circuit is provided with an FPGA_CAM_DN0, an FPGA_CAM_DN1, an FPGA_CAM_DP1, an FPGA_CAM_CN, an FPGA_CAM_CP, an FPGA_CAM_RST, an FPGA_CAM_GPIO, an FPGA_CAM_SCL, an FPGA_CAM_SDA and a VCC_3V3, wherein the FPGA_CAM_CN and the FPGA_CAM_CPare connected to clock channels of the CSI interface, the FPGA_CAM_DN0 and the FPGA_CAM_DP0 are connected to a data channel lane1 of the CSI interface, the FPGA_CAM_DN1 and the FPGA_CAM_DP1 are connected to a data channel lane2 of the CSI interface, the FPGA_CAM_SCL and the FPGA_CAM_SDA are connected to SCCB bus ports of the CMOS image chip, the FPGA_CAM_is connected to a hardware reset end of the CMOS image chip, a terminal impedance of 150 omega is connected to the differential signal port, two VCC_3V3 power supplies are arranged on the FPGA peripheral circuit, one VCC_3V3 power supply end is connected to a capacitor C12 and one end of the VCC_3V3 power supply through a resistor R37, the other VCC_C12 is connected to the other end of the capacitor RST through the capacitor RST, and the other end of the FPGA_CACAM_SDA is connected to the SCCB bus port through the resistance R_C3, and the VCC_RST is connected to the other end of the VCC 3 power supply end of the VCC.

2. The logic circuit capable of improving image transmission efficiency based on FPGA chip design according to claim 1, wherein: the FPGA control circuit adopts a D-PHY protocol in a physical layer, and an interface of the FPGA control circuit adopts a high-speed differential signal to carry out image transmission.

3. The logic circuit capable of improving image transmission efficiency based on the FPGA chip design according to claim 2, wherein: the FPGA control circuit adopts an XC7S15 series chip, and the logic resource reaches 12K.

4. The FPGA chip design-based logic capable of improving image transmission efficiency according to claim 3, wherein: the development board adopted by the FPGA peripheral circuit is an edge acceleration Xilinx development board SpartanEdgeAcceleratorBoard, SEABoard, and the development board integrates the FPGA peripheral circuit, the MIPICII interface and the miniHDMI interface.

5. The logic circuit capable of improving image transmission efficiency based on FPGA chip design according to claim 4, wherein: and realizing a logic function by utilizing the MIPICII interface of the platform and the FPGA chip.