CN113810147A - Multi-channel ultrasonic flaw detector synchronization and data transmission device and control method - Google Patents
Multi-channel ultrasonic flaw detector synchronization and data transmission device and control method Download PDFInfo
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Abstract
The invention provides a synchronization and data transmission device of a multi-channel ultrasonic flaw detector and a control method, comprising the following steps: the probe, the emitting circuit and receive amplifier circuit are connected to the probe, emitting circuit and receive amplifier circuit connect the channel control circuit, receive amplifier circuit and channel control circuit connection multiplex circuit, multiplex circuit passes through data acquisition line connection digital analog conversion circuit, the channel control circuit passes through control bus connection control unit, digital analog conversion circuit connection control unit, control unit connects flaw detector CPU and bus interface circuit. The device and the method for synchronizing and transmitting data of the multi-channel ultrasonic flaw detector realize one-to-many control with high bandwidth and high-precision synchronization of multiple channels, have high data throughput, and can finish a large amount of data transmission work in a short time.
Description
Technical Field
The invention relates to the technical field of industrial ultrasonic flaw detection and measurement, in particular to a synchronization and data transmission device of a multi-channel ultrasonic flaw detector and a control method.
Background
The multi-channel ultrasonic flaw detector is widely applied to industrial automatic ultrasonic flaw detection. Conventional multi-channel ultrasonic flaw detectors generally require the use of multiple signal lines to effect the transmission of synchronization signals, control signals, and ultrasonic signals. The control signal line is mainly used for controlling multi-channel switching and setting preamplification parameters. The number of control signal lines is directly related to the number of channels and the number of pre-amplification stages. In the prior art, some flaw detectors adopt a single-wire transmission signal technology to transmit synchronous signals, control signals and ultrasonic signals, but under many conditions, the flaw detectors are influenced by parallel operation of channels, and the data throughput of single-wire transmission is far from meeting the requirements. For example, in a medium steel plate flaw detection system, the highest sampling repetition frequency requires 8KHz, hundreds of channels need to be detected simultaneously, real-time control is also needed, and a large amount of data transmission work cannot be completed in a short time through single-line transmission. Therefore, it is necessary to design a synchronization and data transmission device and a control method for a multi-channel ultrasonic flaw detector.
Disclosure of Invention
The invention aims to provide a synchronization and data transmission device and a control method for a multi-channel ultrasonic flaw detector, which realize one-to-many control with high bandwidth and high-precision synchronization of multiple channels, have high data throughput and can finish a large amount of data transmission work in a short time.
In order to achieve the purpose, the invention provides the following scheme:
a multichannel ultrasonic flaw detector synchronization and data transmission device comprises: the probe comprises a back-end circuit, a transmission line, a plurality of front-end circuits and a probe, wherein the probe is connected with the front-end circuits, and the front-end circuits are connected with the back-end circuits through the transmission line;
the transmission line comprises a control bus and a data acquisition line;
the front-end circuit comprises a multiplexing circuit, a first PHY circuit, a channel control circuit, a plurality of groups of transmitting circuits and receiving amplification circuits, the probe is connected with the transmitting circuits and the receiving amplification circuits, the transmitting circuits and the receiving amplification circuits are connected with the channel control circuit, the receiving amplification circuits and the channel control circuit are connected with the multiplexing circuit, the channel control circuit is connected with the first PHY circuit, the first PHY circuit is connected with the rear-end circuit through a control bus, and the multiplexing circuit is connected with the rear-end circuit through the data acquisition line;
the rear end circuit comprises a digital-to-analog conversion circuit, a control unit, a second PHY circuit, a flaw detector CPU and a bus interface circuit, the multiplexing circuit is connected with the digital-to-analog conversion circuit through the data acquisition line, the first PHY circuit is connected with the second PHY circuit through a control bus, the second PHY circuit and the digital-to-analog conversion circuit are connected with the control unit, and the control unit is connected with the flaw detector CPU and the bus interface circuit.
Optionally, the channel control circuit is an FPGA or a microcontroller, the control unit is an FPGA or a microcontroller, and the data acquisition line is a radio frequency analog signal transmission line.
The invention also provides a synchronization and data transmission control method of the multi-channel ultrasonic flaw detector, which is applied to the synchronization and data transmission device of the multi-channel ultrasonic flaw detector and is characterized by comprising the following steps:
step 1: the control unit encodes the synchronous signal and the control signal to obtain an encoded information stream, transmits the encoded information stream to the channel control circuit by using the control bus through an Ethernet transmission protocol, decodes the encoded information stream by the channel control circuit to obtain a decoded information stream, and obtains a high-precision clock by a CDR technology;
step 2: the channel control circuit simultaneously controls a multi-channel transmitting circuit, a receiving amplifying circuit and a multiplexing circuit according to the decoding information flow, the multi-channel transmitting circuit transmits excitation signals to the probes in parallel, the probes transmit ultrasonic signals in parallel, the multi-channel receiving amplifying circuit receives ultrasonic echoes in parallel, and the amplified ultrasonic echo signals are input into the digital-to-analog conversion circuit through a data acquisition line with the help of the multiplexing circuit;
and step 3: the digital-to-analog conversion circuit converts the ultrasonic echo signals into digital signals and sends the digital signals to the control unit, and the control unit reads data and processes the data, and sends the processed data to the flaw detector CPU and the bus interface circuit.
Optionally, in step 1, the encoded information stream is transmitted to the channel control circuit by using a control bus through an ethernet transport protocol, which specifically includes:
the control unit transmits the coded information stream to a data link layer of the back-end circuit, the data link layer of the back-end circuit transmits the coded information stream to a physical layer of the back-end circuit, the physical layer of the back-end circuit transmits the coded information stream to a physical layer of the front-end circuit through a control bus, the physical layer of the front-end circuit transmits the coded information stream to the data link layer of the front-end circuit, and the data link layer of the front-end circuit transmits the coded information stream to the channel control circuit.
Optionally, the physical layer of the back-end circuit transmits the encoded information stream to the physical layers of all the front-end circuits via the control bus, the physical layer of the front-end circuit transmits the encoded information stream to the data link layer of the front-end circuit, and the data link layer of the front-end circuit transmits the encoded information stream to the channel control circuit.
Optionally, the physical layer of the back-end circuit transmits the encoded information stream to the physical layer of one or more front-end circuits through the control bus, the physical layer of the front-end circuit sends the encoded information stream to the data link layer of the front-end circuit, the data link layer of the front-end circuit sends the encoded information stream to the channel control circuit, and after sending is completed, the front-end circuit forwards the encoded information stream to other front-end circuits that do not receive the encoded information stream in a data copying manner.
Optionally, in step 1, the encoded information stream is transmitted to the channel control circuit by using a control bus through an ethernet transport protocol, which specifically includes:
the control unit is directly in circuit connection with the channel control circuit through an MAC protocol, the control unit transmits the coded information stream to the channel control circuit through a control bus, and the channel control circuit forwards the coded information stream to other channel control circuits in a data copying mode.
Optionally, in step 1, the control unit encodes the control signal to obtain an encoded information stream, and transmits the encoded information stream to the channel control circuit through the ethernet transport protocol by using the control bus, and the channel control circuit decodes the encoded information stream to obtain a decoded information stream, and obtains the high-precision clock through the CDR technology, specifically:
the control unit detects that control data needs to be sent, sequentially performs transmission control according to the priority of data transmission, encodes the data to be transmitted into an MAC frame, wherein the data field of the MAC frame is divided into three parts, namely a data type field, a data length field and the data field to be transmitted, transmits the MAC frame to a channel control circuit by using a control bus through an Ethernet transmission protocol after encoding is completed, and the channel control circuit decodes the MAC frame and performs data distribution according to the data type field.
Optionally, in step 1, the control unit encodes the synchronization signal to obtain an encoded information stream, and transmits the encoded information stream to the channel control circuit through an ethernet transport protocol by using the control bus, and the channel control circuit decodes the encoded information stream to obtain a decoded information stream, and obtains a high-precision clock through a CDR technique, specifically:
the control unit obtains synchronous data of a time service system, encodes the synchronous data into an MAC frame, transmits the MAC frame to the channel control circuit by using a control bus through an Ethernet transmission protocol, the channel control circuit decodes the MAC frame to extract the synchronous data, and obtains a high-precision clock by using a first PHY circuit and a second PHY circuit through a CDR technology, the channel control circuit obtains a self synchronous state according to the synchronous data according to the high-precision clock and corrects the self synchronous state to be consistent with the control unit, and the control unit circularly executes a synchronous flow to enable the channel control circuit to continuously correct the self synchronous state.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects: the invention provides a multichannel ultrasonic flaw detector synchronization and data transmission device and a control method, which can realize one-to-many control with high bandwidth and multichannel high-precision synchronization, and the device comprises a back-end circuit, a transmission line, a plurality of front-end circuits and probes, wherein the front-end circuit and the back-end circuit are in modular design and have strong function expansion capability, the front-end circuit comprises a multiplexing circuit, a channel control circuit, a plurality of groups of transmitting circuits and receiving and amplifying circuits, the back-end circuit comprises a digital-to-analog conversion circuit, a control unit, a flaw detector CPU and a bus interface circuit, and the control unit and the channel control circuit can carry a self-defined communication protocol on a data link layer to complete data interaction and can also directly complete data interaction by circuit connection through an MAC protocol; the device can form a more complex topological structure, enhances the expansion capability and data throughput of the multi-channel ultrasonic flaw detection system, and simultaneously provides a solid guarantee for the time-sharing multiplexing function of the system; the control method comprises the steps that a control unit encodes a synchronous signal and a control signal to obtain an encoded information stream, the encoded information stream is transmitted to a channel control circuit by utilizing an Ethernet transmission protocol through a control bus, the channel control circuit decodes the encoded information stream to obtain a decoded information stream, the channel control circuit simultaneously controls a multiplex transmitting circuit, a receiving amplifying circuit and a multiplex circuit transmitting circuit according to the decoded information stream to transmit an excitation signal to a probe, the probe transmits an ultrasonic signal, the receiving amplifying circuit receives an ultrasonic echo, the amplified ultrasonic echo signal is input into a digital-to-analog conversion circuit through a data acquisition line under the assistance of the multiplex circuit, the digital-to-analog conversion circuit converts the ultrasonic echo signal into a digital signal and transmits the digital signal to the control unit, the control unit reads and processes the data, and transmits the processed ultrasonic echo signal to a flaw detector CPU and a bus interface circuit, the method adopts a form of digitizing the synchronous signals for transmission, the back-end circuit transmits the synchronous signals to other front-end circuits, and the front-end circuit decodes the digitized synchronous signals and applies the decoded signals to a self timing system for equipment synchronization; in the method, the control unit is in an active working state, the channel control circuit is in a passive working state, the control signals of the channels are only transmitted by the control bus and are isolated from the data acquisition lines for transmitting the analog signals without mutual interference, and the method is particularly suitable for the conditions of large number of channels, long transmission distance and high parallel working requirement of the channels.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic structural diagram of a synchronization and data transmission device of a multi-channel ultrasonic flaw detector according to an embodiment of the invention;
FIG. 2 is a flow chart of a method for synchronizing and transmitting data of a multi-channel ultrasonic flaw detector according to an embodiment of the invention;
FIG. 3 is a schematic diagram of data transmission between an Ethernet transport protocol implementation control unit and a channel control circuit;
FIG. 4 is a diagram illustrating data transmission between a control unit and a channel control circuit implemented by MAC protocol;
FIG. 5 is a schematic diagram of an expanded structure of a synchronization and data transmission device of a multi-channel ultrasonic flaw detector according to an embodiment of the invention;
fig. 6 is a diagram illustrating a data field structure of a MAC frame.
Reference numerals: 1. a probe; 2. a transmitting circuit; 3. a receiving amplifying circuit; 4. a channel control circuit; 5. a multiplexing circuit; 6. a first PHY circuit; 7. a radio frequency analog signal transmission line; 8. a control bus; 9. a digital-to-analog conversion circuit; 10. a second PHY circuit; 11. a control unit; 12. a flaw detector CPU and a bus interface circuit; 13. a front-end circuit; 14. a back end circuit; 15. a data link layer; 16. a physical layer; 17. a data type field; 18. a data length field; 19. a data field to be transmitted.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a synchronization and data transmission device and a control method for a multi-channel ultrasonic flaw detector, which realize one-to-many control with high bandwidth and high-precision synchronization of multiple channels, have high data throughput and can finish a large amount of data transmission work in a short time.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1, a multi-channel ultrasonic flaw detector synchronization and data transmission apparatus provided by an embodiment of the present invention includes: the probe comprises a back-end circuit 12, a transmission line, a plurality of front-end circuits 11 and a probe 1, wherein the probe 1 is connected with the front-end circuits 11, and the front-end circuits 11 are connected with the back-end circuit 12 through the transmission line;
the front-end circuit 13 comprises a multiplexing circuit 5, a first PHY circuit 6, a channel control circuit 4, a plurality of sets of transmitting circuits 2 and receiving amplification circuits 3, the probe 1 is connected to the transmitting circuits 2 and the receiving amplification circuits 3, the transmitting circuits 2 and the receiving amplification circuits 3 are connected to the channel control circuit 4, the receiving amplification circuits 3 and the channel control circuit 4 are connected to the multiplexing circuit 5, the channel control circuit 4 is connected to the first PHY circuit 6, the first PHY circuit 6 is connected to the back-end circuit 14 through a control bus 8, and the multiplexing circuit 5 is connected to the back-end circuit 14 through the data acquisition line;
the rear end circuit 14 comprises a digital-to-analog conversion circuit 9, a control unit 11, a second PHY circuit 10, a flaw detector CPU and a bus interface circuit 12, the multiplexing circuit 5 is connected with the digital-to-analog conversion circuit 9 through the data acquisition line, the first PHY circuit 10 is connected with the second PHY circuit 10 through a control bus 8, the second PHY circuit 10 and the digital-to-analog conversion circuit 9 are connected with the control unit 11, and the control unit 11 is connected with the flaw detector CPU and the bus interface circuit 12.
The number of the probes 1 corresponds to the number of the transmitting circuits 2 and the receiving amplifying circuits 3, the number of the transmitting circuits 2 and the receiving amplifying circuits 3 is set according to specific requirements, and the number of the front-end circuits 13 is set according to requirements.
The channel control circuit 4 is an FPGA or a microcontroller, the control unit 11 is an FPGA or a microcontroller, and the data acquisition line is a radio frequency analog signal transmission line 7.
The first PHY circuit and the second PHY circuit output control signals, and high-precision clocks can be obtained by using CDR technology.
As shown in fig. 2, the present invention further provides a method for controlling synchronization and data transmission of a multi-channel ultrasonic flaw detector, comprising the following steps:
step 1: the control unit encodes the synchronous signal and the control signal to obtain an encoded information stream, transmits the encoded information stream to the channel control circuit by using the control bus through an Ethernet transmission protocol, decodes the encoded information stream by the channel control circuit to obtain a decoded information stream, and obtains a high-precision clock by a CDR technology;
step 2: the channel control circuit simultaneously controls a multi-channel transmitting circuit, a receiving amplifying circuit and a multiplexing circuit according to the decoding information flow, the multi-channel transmitting circuit transmits an excitation signal to the probes in parallel, the probes are provided with piezoelectric wafers, a plurality of probes transmit ultrasonic signals in parallel under the action of the excitation signal, the multi-channel receiving amplifying circuit receives ultrasonic echoes in parallel, and the amplified ultrasonic echo signals are input into the digital-to-analog conversion circuit through a data acquisition line with the assistance of the multiplexing circuit;
and step 3: the digital-to-analog conversion circuit converts the ultrasonic echo signals into digital signals and sends the digital signals to the control unit, and the control unit reads data and processes the data, and sends the processed data to the flaw detector CPU and the bus interface circuit.
In one embodiment, in step 1, one method for transmitting the encoded information stream to the channel control circuit through the ethernet transport protocol by using the control bus is as follows:
as shown in fig. 3, the control bus uses a mature ethernet transmission protocol for data transmission, carries a customized communication protocol and completes data interaction on a data link layer, the control unit transmits a coded information stream to the data link layer of the back-end circuit, the data link layer of the back-end circuit transmits the coded information stream to the physical layer of the back-end circuit, the physical layer of the back-end circuit transmits the coded information stream to the physical layer of the front-end circuit via the control bus, the physical layer of the front-end circuit transmits the coded information stream to the data link layer of the front-end circuit, and the data link layer of the front-end circuit transmits the coded information stream to the channel control circuit.
There are two methods for the multi-channel front-end circuit to obtain the encoded information stream, one of which is: the physical layer of the back-end circuit transmits the coded information stream to the physical layers of all the front-end circuits through the control bus, the physical layer of the front-end circuit transmits the coded information stream to the data link layer of the front-end circuit, and the data link layer of the front-end circuit transmits the coded information stream to the channel control circuit.
The other is as follows: the physical layer of the back-end circuit transmits the coded information stream to one or more physical layers of the front-end circuit through a control bus, the physical layer of the front-end circuit transmits the coded information stream to a data link layer of the front-end circuit, the data link layer of the front-end circuit transmits the coded information stream to a channel control circuit, and after the transmission is finished, the front-end circuit transmits the coded information stream to other front-end circuits which do not receive the coded information stream in a data copying mode.
In the second embodiment, in step 1, another method for transmitting the encoded information stream to the channel control circuit by using the control bus through the ethernet transport protocol is as follows:
as shown in fig. 4, with the advantage of ethernet layered transmission, data transmission is not limited to the 1000BASE-X based optical fiber transmission and the 1000BASE-T based twisted pair transmission, the control unit may also directly perform circuit connection with the channel control circuit in the MAC protocol, and the control unit transmits the encoded information stream to the channel control circuit through the control bus, where the control unit may transmit the encoded information stream to the channel control circuits of all front-end circuits, or to one or more channel control circuits, and the channel control circuit forwards the encoded information stream to other channel control circuits in the form of data replication.
Through the above data transmission scheme, the synchronization and data transmission device of the multi-channel ultrasonic flaw detector can form a more complex topological structure, for example, as shown in fig. 5, an embodiment of the present invention is that a control unit of a back-end circuit is connected to channel control circuits of three front-end circuits, a channel control circuit of one front-end circuit is connected to a new channel control circuit of one front-end circuit, and a channel control circuit of the new front-end circuit is connected to a channel control circuit of another new front-end circuit.
In data transmission control, in step 1, a control unit encodes a control signal to obtain an encoded information stream, and transmits the encoded information stream to a channel control circuit by using a control bus through an ethernet transmission protocol, and the channel control circuit decodes the encoded information stream to obtain a decoded information stream, and obtains a high-precision clock through a CDR technology, specifically:
the control unit detects that control data needs to be sent, sequentially performs transmission control according to the priority of data transmission, and encodes the data to be transmitted into an MAC frame, as shown in fig. 6, wherein the data field of the MAC frame is divided into three parts, namely a data type field 17, a data length field 18, and a data field 19 to be transmitted, after the encoding is completed, the MAC frame is transmitted to the channel control circuit through the ethernet transmission protocol by using the control bus, and the channel control circuit decodes the MAC frame and distributes the data according to the data type field.
In the synchronous control, in step 1, the control unit encodes the synchronous signal to obtain an encoded information stream, and transmits the encoded information stream to the channel control circuit by using the control bus through the ethernet transmission protocol, and the channel control circuit decodes the encoded information stream to obtain a decoded information stream, and obtains a high-precision clock through the CDR technology, specifically:
the control unit obtains a synchronous signal of a time service system, digitalizes the synchronous signal to obtain synchronous data, encodes the synchronous data into an MAC frame, transmits the MAC frame to a channel control circuit by using an Ethernet transmission protocol through a control bus, the channel control circuit decodes the MAC frame to extract the synchronous data, obtains a high-precision clock by using a first PHY circuit and a second PHY circuit through a CDR technology, obtains the self synchronous state according to the synchronous data by the channel control circuit and corrects the self synchronous state to be consistent with the control unit, and the control unit circularly executes a synchronous flow to enable the channel control circuit to continuously correct the self synchronous state.
One embodiment of the invention is: when a control signal is transmitted, an RGMII transmission protocol is adopted to transmit data, a control unit detects that the control signal needs to be sent, the control signal is converted into control data through a digital-to-analog conversion circuit, transmission control is sequentially performed according to the priority of data transmission, the data to be transmitted is encoded into an MAC frame, the data field of the MAC frame is divided into three parts, namely a data type field, a data length field and a data field to be transmitted, and the MAC frame is subjected to data transmission through the RGMII transmission protocol.
The most important of the multi-channel control is synchronous control, the method adopts a form of digitalizing synchronous signals for transmission, by means of the data communication mode, a back-end circuit transmits the synchronous signals to other front-end circuits, the front-end circuit decodes the digitalized synchronous signals and applies the digitalized synchronous signals to a self timing system for equipment synchronization, compared with the traditional method of exciting signals by synchronous pulses, the method not only reduces the requirements of synchronous signal lines, but also greatly improves the jitter precision of the synchronous signals, and specifically comprises the following steps:
the control unit obtains the synchronous signal of the time service system, digitalizes the synchronous signal to obtain synchronous data, codes the synchronous data into an MAC frame, the MAC frame is transmitted to a channel control circuit by utilizing a control bus through an RGMII transmission protocol, the channel control circuit decodes the MAC frame to extract synchronous data, and a high-precision clock is obtained by using the first PHY circuit and the second PHY circuit through CDR technology, the channel control circuit is used for controlling the channel control circuit according to the high-precision clock, obtaining the self synchronous state according to the synchronous data, correcting the self synchronous state to keep the self synchronous state consistent with the control unit, circularly executing the synchronous flow by the control unit to ensure that the channel control circuit continuously corrects the self synchronous state because all channels are based on the synchronous data of the same control unit, therefore, the synchronization state between multiple channels is excellent, and the error between the synchronization time of the control circuit and the control unit is only 0.5ns according to the actual measurement channel.
Through the use of the control bus data transmission, the requirements of simultaneous acquisition of multi-channel data, real-time control and synchronous uploading of sampling data are fully met, and the method is applied to multi-channel ultrasonic flaw detection and has the following flaw detection flow:
the control unit digitalizes the synchronous signal and the control signal, codes the synchronous signal and the control signal on the control bus, transmits the synchronous signal and the control signal to the channel control circuit, the channel control circuit decodes the coded data, and controls the multiplex transmitting circuit, the receiving amplifying circuit and the multiplex circuit in parallel according to the decoded data, wherein, a plurality of channels are controlled by the real-time channel control circuit, the parallel control transmitting circuit transmits the excitation signal to the probe, the probe transmits the ultrasonic signal, the receiving amplifying circuit receives the ultrasonic echo, the amplifying work is carried out by the real-time control of the channel control circuit, the amplified ultrasonic echo signal is input into the digital-analog conversion circuit by the data acquisition line under the assistance of the multiplex circuit, the data conversion circuit converts the ultrasonic echo signal into the digital signal, and then the digital signal is input into the digital control unit and processed by the control unit, the control unit is in an active working state, the channel control circuit is in a passive working state, the control signals of the channels are only transmitted by the control bus and are isolated from the data acquisition lines for transmitting the analog signals without mutual interference.
The invention provides a multichannel ultrasonic flaw detector synchronization and data transmission device and a control method, which can realize one-to-many control with high bandwidth and multichannel high-precision synchronization, and the device comprises a back-end circuit, a transmission line, a plurality of front-end circuits and probes, wherein the front-end circuit and the back-end circuit are in modular design and have strong function expansion capability, the front-end circuit comprises a multiplexing circuit, a channel control circuit, a plurality of groups of transmitting circuits and receiving and amplifying circuits, the back-end circuit comprises a digital-to-analog conversion circuit, a control unit, a flaw detector CPU and a bus interface circuit, and the control unit and the channel control circuit can carry a self-defined communication protocol on a data link layer to complete data interaction and can also directly complete data interaction by circuit connection through an MAC protocol; the device can form a more complex topological structure, enhances the expansion capability and data throughput of the multi-channel ultrasonic flaw detection system, and simultaneously provides a solid guarantee for the time-sharing multiplexing function of the system; the control method comprises the steps that a control unit encodes a synchronous signal and a control signal to obtain an encoded information stream, the encoded information stream is transmitted to a channel control circuit by utilizing an Ethernet transmission protocol through a control bus, the channel control circuit decodes the encoded information stream to obtain a decoded information stream, the channel control circuit controls a transmitting circuit, a receiving amplifying circuit and a multiplexing circuit according to the decoded information stream, the transmitting circuit transmits an excitation signal to a probe, the probe transmits an ultrasonic signal, the receiving amplifying circuit receives an ultrasonic echo, the amplified ultrasonic echo signal is input into a digital-to-analog conversion circuit through a data acquisition line under the assistance of the multiplexing circuit, the digital-to-analog conversion circuit converts the ultrasonic echo signal into a digital signal and transmits the digital signal to the control unit, the control unit reads and processes the data, and transmits the processed ultrasonic echo to a flaw detector CPU and a bus interface circuit, the method adopts a form of digitizing the synchronous signals for transmission, the back-end circuit transmits the synchronous signals to other front-end circuits, and the front-end circuit decodes the digitized synchronous signals and applies the decoded signals to a self timing system for equipment synchronization; in the method, the control unit is in an active working state, the channel control circuit is in a passive working state, the control signals of the channels are only transmitted by the control bus and are isolated from the data acquisition lines for transmitting the analog signals without mutual interference, and the method is particularly suitable for the conditions of large number of channels, long transmission distance and high parallel working requirement of the channels.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (9)
1. The utility model provides a multichannel ultrasonic flaw detector synchronization and data transmission device which characterized in that includes: the probe comprises a back-end circuit, a transmission line, a plurality of front-end circuits and a probe, wherein the probe is connected with the front-end circuits, and the front-end circuits are connected with the back-end circuits through the transmission line;
the transmission line comprises a control bus and a data acquisition line;
the front-end circuit comprises a multiplexing circuit, a first PHY circuit, a channel control circuit, a plurality of groups of transmitting circuits and receiving amplification circuits, the probe is connected with the transmitting circuits and the receiving amplification circuits, the transmitting circuits and the receiving amplification circuits are connected with the channel control circuit, the receiving amplification circuits and the channel control circuit are connected with the multiplexing circuit, the channel control circuit is connected with the first PHY circuit, the first PHY circuit is connected with the rear-end circuit through a control bus, and the multiplexing circuit is connected with the rear-end circuit through the data acquisition line;
the rear end circuit comprises a digital-to-analog conversion circuit, a control unit, a second PHY circuit, a flaw detector CPU and a bus interface circuit, the multiplexing circuit is connected with the digital-to-analog conversion circuit through the data acquisition line, the first PHY circuit is connected with the second PHY circuit through a control bus, the second PHY circuit and the digital-to-analog conversion circuit are connected with the control unit, and the control unit is connected with the flaw detector CPU and the bus interface circuit.
2. The multi-channel ultrasonic flaw detector synchronizing and data transmitting device of claim 1, wherein the channel control circuit is an FPGA or a microcontroller, the control unit is an FPGA or a microcontroller, and the data acquisition line is a radio frequency analog signal transmission line.
3. A multi-channel ultrasonic flaw detector synchronization and data transmission control method applied to the multi-channel ultrasonic flaw detector synchronization and data transmission device of any one of claims 1-2, characterized by comprising the following steps:
step 1: the control unit encodes the synchronous signal and the control signal to obtain an encoded information stream, transmits the encoded information stream to the channel control circuit by using the control bus through an Ethernet transmission protocol, decodes the encoded information stream by the channel control circuit to obtain a decoded information stream, and obtains a high-precision clock by a CDR technology;
step 2: the channel control circuit simultaneously controls a multi-channel transmitting circuit, a receiving amplifying circuit and a multiplexing circuit according to the decoding information flow, the multi-channel transmitting circuit transmits excitation signals to the probes in parallel, the probes transmit ultrasonic signals in parallel, the multi-channel receiving amplifying circuit receives ultrasonic echoes in parallel, and the amplified ultrasonic echo signals are input into the digital-to-analog conversion circuit through a data acquisition line with the help of the multiplexing circuit;
and step 3: the digital-to-analog conversion circuit converts the ultrasonic echo signals into digital signals and sends the digital signals to the control unit, and the control unit reads data and processes the data, and sends the processed data to the flaw detector CPU and the bus interface circuit.
4. The multi-channel ultrasonic flaw detector synchronization and data transmission control method according to claim 3, wherein in step 1, the coded information stream is transmitted to the channel control circuit by using the control bus through the ethernet transmission protocol, specifically:
the control unit transmits the coded information stream to a data link layer of the back-end circuit, the data link layer of the back-end circuit transmits the coded information stream to a physical layer of the back-end circuit, the physical layer of the back-end circuit transmits the coded information stream to a physical layer of the front-end circuit through a control bus, the physical layer of the front-end circuit transmits the coded information stream to the data link layer of the front-end circuit, and the data link layer of the front-end circuit transmits the coded information stream to the channel control circuit.
5. The multi-channel ultrasonic flaw detector synchronization and data transmission control method according to claim 4, wherein the physical layer of the back-end circuit transmits the coded information stream to the physical layers of all the front-end circuits via the control bus, the physical layer of the front-end circuit transmits it to the data link layer of the front-end circuit, and the data link layer of the front-end circuit transmits the coded information stream to the channel control circuit.
6. The multi-channel ultrasonic flaw detector synchronization and data transmission control method of claim 4, wherein the physical layer of the back-end circuit transmits the coded information stream to the physical layer of one or more front-end circuits via the control bus, the physical layer of the front-end circuit transmits the coded information stream to the data link layer of the front-end circuit, the data link layer of the front-end circuit transmits the coded information stream to the channel control circuit, and after the transmission is finished, the front-end circuit forwards the coded information stream to other front-end circuits which do not receive the coded information stream in a data copying mode.
7. The multi-channel ultrasonic flaw detector synchronization and data transmission control method according to claim 3, wherein in step 1, the coded information stream is transmitted to the channel control circuit by using the control bus through the ethernet transmission protocol, specifically:
the control unit is directly in circuit connection with the channel control circuit through an MAC protocol, the control unit transmits the coded information stream to the channel control circuit through a control bus, and the channel control circuit forwards the coded information stream to other channel control circuits in a data copying mode.
8. The multi-channel ultrasonic flaw detector synchronization and data transmission control method of claim 3, wherein in step 1, the control unit encodes the control signal to obtain an encoded information stream, and transmits the encoded information stream to the channel control circuit by using the control bus through the ethernet transmission protocol, and the channel control circuit decodes the encoded information stream to obtain a decoded information stream, and obtains the high-precision clock by using the CDR technique, specifically:
the control unit detects that control data needs to be sent, sequentially performs transmission control according to the priority of data transmission, encodes the data to be transmitted into an MAC frame, wherein the data field of the MAC frame is divided into three parts, namely a data type field, a data length field and the data field to be transmitted, transmits the MAC frame to a channel control circuit by using a control bus through an Ethernet transmission protocol after encoding is completed, and the channel control circuit decodes the MAC frame and performs data distribution according to the data type field.
9. The multi-channel ultrasonic flaw detector synchronization and data transmission control method of claim 3, wherein in step 1, the control unit encodes the synchronization signal to obtain an encoded information stream, and transmits the encoded information stream to the channel control circuit by using the control bus through the ethernet transmission protocol, and the channel control circuit decodes the encoded information stream to obtain a decoded information stream, and obtains the high-precision clock by the CDR technique, specifically:
the control unit obtains synchronous data of a time service system, encodes the synchronous data into an MAC frame, transmits the MAC frame to the channel control circuit by using a control bus through an Ethernet transmission protocol, the channel control circuit decodes the MAC frame to extract the synchronous data, and obtains a high-precision clock by using a first PHY circuit and a second PHY circuit through a CDR technology, the channel control circuit obtains a self synchronous state according to the synchronous data according to the high-precision clock and corrects the self synchronous state to be consistent with the control unit, and the control unit circularly executes a synchronous flow to enable the channel control circuit to continuously correct the self synchronous state.
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