CN113809089A - Semiconductor structure, manufacturing method and three-dimensional memory - Google Patents

Semiconductor structure, manufacturing method and three-dimensional memory Download PDF

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Publication number
CN113809089A
CN113809089A CN202111072584.XA CN202111072584A CN113809089A CN 113809089 A CN113809089 A CN 113809089A CN 202111072584 A CN202111072584 A CN 202111072584A CN 113809089 A CN113809089 A CN 113809089A
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etched
opening
film layer
substrate
semiconductor structure
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吴加吉
石艳伟
邹欣伟
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202111072584.XA priority Critical patent/CN113809089A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Abstract

The invention provides a semiconductor structure, a manufacturing method and a three-dimensional memory, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a film layer to be etched on a substrate; performing ion implantation on the film layer to be etched; at least one opening is formed in the film layer to be etched in the longitudinal direction perpendicular to the substrate, the opening comprises a first part and a second part, the longitudinal depth of the first part corresponds to a specific depth, the cross section width of the longitudinal lower end of the first part is larger than that of the longitudinal upper end of the second part, the etching rate of the film layer to be etched, which is subjected to ion implantation, is changed by performing etching after the film layer to be etched is subjected to ion implantation, so that at least one opening is formed in the film layer to be etched, wherein the cross section width of the longitudinal lower end of the first part is larger than that of the longitudinal upper end of the second part, the problem that residues generated by deep hole etching are difficult to clean is solved, and the requirement of mass production is met.

Description

Semiconductor structure, manufacturing method and three-dimensional memory
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method and a three-dimensional memory.
[ background of the invention ]
Three-dimensional memory (3D NAND Flash) is widely applied to computers, solid state disks and electronic equipment due to the advantages of high storage density, high programming speed and the like. The market demands that the storage capacity is continuously increased without increasing the storage area, and in order to meet such demands, it is necessary to increase the storage density and reduce the size of the three-dimensional memory. Therefore, an X-stacking architecture is proposed, in which an Array memory cell (Array) of a three-dimensional memory and a peripheral Circuit (peripheral Circuit) for controlling the Array memory cell are fabricated on two or more wafers (wafers), and then the two or more wafers are subjected to wire Bonding (Bonding) to increase the memory density. As the Bit Line (Bit Line) of the array memory cell adopting the X-stacking architecture is smaller and smaller, the scaling of the peripheral circuit size corresponding to the Bit Line is challenging, and correspondingly, the deep holes in the array memory cell and the peripheral circuit are smaller and smaller in diameter and larger in depth, that is, the aspect ratio of the deep holes is larger and larger, and the distance between the deep holes is smaller and smaller, so that the size reduction of the three-dimensional memory adopting the X-stacking architecture is challenging to couple interference (coupling). Meanwhile, as the diameter of the deep hole is smaller and the depth-to-width ratio of the deep hole is larger and larger, the deep hole etching only depends on the optimization of the etching process (Etch) to encounter a bottleneck, and residues (Residue) generated by the deep hole etching are difficult to Clean (Clean), so that the defect of the DVC (Dark Voltage Contrast) is caused, and the requirement of mass production cannot be met.
Therefore, the prior art has defects and needs to be improved and developed.
[ summary of the invention ]
The invention aims to provide a semiconductor structure, a manufacturing method and a three-dimensional memory, which break through the bottleneck of an etching process, and simultaneously solve the problem that residues generated by deep hole etching are difficult to clean so as to meet the requirement of mass production.
In order to solve the above problems, the present invention provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a film layer to be etched on a substrate; performing ion implantation on the film layer to be etched to reach a specific depth; at least one opening is formed in the film layer to be etched in a longitudinal direction perpendicular to the substrate, and the opening comprises a first portion and a second portion, wherein the longitudinal depth of the first portion corresponds to a specific depth, and the cross-sectional width of the longitudinal lower end of the first portion is larger than the cross-sectional width of the longitudinal upper end of the second portion.
Wherein, before carrying out ion implantation on the film layer to be etched, the method further comprises the following steps:
and forming a patterned photoresist layer with an opening corresponding to the film layer to be etched, so that ions can be injected into the part, corresponding to the opening, of the film layer to be etched.
Wherein, after ion implantation is carried out on the film layer to be etched, the method further comprises the following steps:
and forming a patterned photoresist layer corresponding to the opening on the film layer to be etched.
Wherein, the longitudinal section between first portion and the second part forms there is the level difference, and the cross sectional shape of first portion includes the down-trapezoidal.
Wherein the opening comprises any one or more of a via, a groove, or a contact hole.
And forming at least one opening in the film layer to be etched in a longitudinal direction perpendicular to the substrate by a dry etching process.
Wherein, after at least one opening is formed in the film layer to be etched in the longitudinal direction perpendicular to the substrate, the method further comprises the following steps:
and cleaning the opening to remove residues in the opening.
Wherein, after at least one opening is formed in the film layer to be etched in the longitudinal direction perpendicular to the substrate, the method further comprises the following steps:
the opening is filled with a metal material.
Wherein the metal material comprises any one of tungsten, copper or aluminum.
The dopant for ion implantation includes a non-charged substance or a non-charged substance.
Wherein the uncharged species comprises argon.
The charged substance includes boron or phosphorus.
Wherein, the material of the film layer to be etched comprises oxide.
The film layer to be etched further comprises a hard mask layer and an anti-reflection layer which are sequentially stacked.
In order to solve the above problem, an embodiment of the present application further provides a semiconductor structure, including: the filling block comprises a first part and a second part, wherein the longitudinal depth of the first part corresponds to a specific depth, and the cross-sectional width of the longitudinal lower end of the first part is larger than that of the longitudinal upper end of the second part.
Wherein, the longitudinal section between first portion and the second part forms there is the level difference, and the cross sectional shape of filling the piece includes the trapezoidal of falling.
Wherein the material of the filling block comprises any one of tungsten, copper or aluminum.
In order to solve the above problem, embodiments of the present application further provide a three-dimensional memory, which includes an array memory structure and a peripheral circuit, wherein any one of the semiconductor structures is located in the array memory structure and/or the peripheral circuit, and the filling blocks in the semiconductor structure include any one or more of via filling blocks, recess filling blocks, or contact hole filling blocks.
The invention has the beneficial effects that: the invention provides a semiconductor structure, a manufacturing method and a three-dimensional memory, which are different from the prior art, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a film layer to be etched on a substrate; performing ion implantation on the film layer to be etched to reach a specific depth; at least one opening is formed in the film layer to be etched in the longitudinal direction perpendicular to the substrate, the opening comprises a first part and a second part, the cross section width of the longitudinal lower end of the first part is larger than the cross section width of the longitudinal upper end of the second part, the film layer to be etched is subjected to ion implantation and then is etched, the etching rate of the film layer to be etched subjected to ion implantation is changed, so that at least one opening is formed in the film layer to be etched, the cross section width of the longitudinal lower end of the first part is larger than the cross section width of the longitudinal upper end of the second part, the problem that residues generated by deep hole etching are difficult to clean is solved, and the requirement of mass production is met.
[ description of the drawings ]
FIG. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of a substrate provided in one embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a film layer to be etched according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram illustrating an ion implantation process performed on a film to be etched according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure for forming a photoresist layer in accordance with one embodiment of the present invention;
FIG. 6 is a schematic view of an embodiment of the present invention illustrating the formation of an opening;
FIG. 7 is a flow chart illustrating a method of fabricating a semiconductor structure according to another embodiment of the present invention;
FIG. 8 is a schematic diagram of a photoresist layer formed in accordance with another embodiment of the present invention;
FIG. 9 is a schematic structural diagram illustrating ion implantation of a film to be etched according to another embodiment of the present invention;
FIG. 10 is a schematic view of a photoresist layer formed according to another embodiment of the present invention;
FIG. 11 is a schematic diagram of a semiconductor structure in accordance with one embodiment of the present invention;
fig. 12 is a schematic structural diagram of a semiconductor structure according to another embodiment of the invention.
[ detailed description ] embodiments
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Likewise, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive step are within the scope of the present invention.
In addition, directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], and the like, refer to directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the various figures, elements of similar structure are identified by the same reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, some well-known elements may not be shown in the figures.
As shown in fig. 1, the present invention provides a method for manufacturing a semiconductor device, and the specific process is compared with the structure diagrams of fig. 2 to 5, and may include the following steps:
s101, a step: a substrate 110 is provided.
Fig. 2 shows the structure formed in step S101, which includes: a substrate 110. The base 110 may be a substrate, the substrate is used as a base for forming a semiconductor device, the substrate is made of a semiconductor material, and may be silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), or the like, or other materials, and the base 110 may further include a substrate and one or more other film layers formed on the substrate, such as an oxide film layer (SiO film layer)2) The silicon nitride film (SiN), silicon oxynitride film (SiON), or the like, and may also include a substrate and an active device or a passive device formed on the substrate, which is not particularly limited.
S102, a step: a film layer to be etched 120 is formed on the substrate 110.
Fig. 3 shows the structure formed in step S102, which includes: a substrate 110 and a dielectric layer as a film layer 120 to be etched on the substrate 110. Typically, the material of the film 120 to be etched is a non-metal, such as an oxide (SiO)2) Silicon nitride SiN), silicon oxynitride (SiON), and the like, and may also be a metal such as tungsten (W), aluminum (Al), or the like, without particular limitation.
Before the step S103, the method further includes:
and S105: a patterned photoresist layer 130 corresponding to the opening 140 is formed on the film layer to be etched 120 for ion implantation into a portion of the film layer to be etched 120 corresponding to the opening 140.
Fig. 4 shows the structure formed in step S105, which includes: the mask includes a substrate 110, a film layer 120 to be etched on the substrate 110, and a patterned photoresist layer 130 corresponding to an opening 140 on the film layer 120 to be etched.
Specifically, the photolithography process (Photo) is a technique for copying images, and is a key process technique in the integrated circuit manufacturing process, and the photolithography process uses a photocopying method to precisely copy the patterns on the mask onto the photoresist layer 130 coated on the surface of the film layer 120 to be etched, so as to form the patterned photoresist layer 130 having the openings 140 on the film layer 120 to be etched, so as to implant ions into the portions of the film layer 120 to be etched, which correspond to the openings 140, and then perform various processes such as ion implantation, etching process, or thin film deposition on the wafer under the protection of the photoresist layer 130. The pattern on the patterned photoresist layer 130 corresponds to the pattern on the mask plate to be etched, and is used as an etching protection layer, so that the profile (profile) of the opening 140 is formed at the corresponding position through an etching process.
The film layer to be etched 120 further includes a hard mask layer and an anti-reflection layer (not shown in the figure) stacked in sequence.
Specifically, a Hard Mask layer (Hard Mask) may be formed between the film layer 120 to be etched and the patterned photoresist layer 130 before the etching process, and the Hard Mask layer may be an inorganic thin film material formed by Chemical Vapor Deposition (CVD), and its main components are usually titanium nitride (TiN), silicon nitride (SiN) and silicon oxide (SiO) respectively2) After the hard mask layer is formed between the film layer 120 to be etched and the patterned photoresist layer 130, the hard mask layer in the region corresponding to the opening 140 is removed through an etching process, and the hard mask layers in other regions where the opening 140 is not formed are retained, so that the film layer 120 to be etched in the region not required to be etched can be protected from being damaged in the subsequent etching process and other processes.
Further, because of the optical reflection effect on the surface of the substrate, the reflected light and the incident light interfere with each other, a standing wave effect and multiple exposure are formed in the photoresist, so that the critical dimension of the pattern cannot be controlled, and the etching precision is reduced.
S103, a step: and performing ion implantation on the film layer 120 to be etched.
Fig. 5 shows the structure formed in step S103, which includes: the semiconductor device includes a substrate 110 and a film layer to be etched 120 on the substrate 110, wherein a doped region 121 is formed in the film layer to be etched 120 in a direction perpendicular to a longitudinal direction of the substrate 110.
Specifically, the ion implantation has the advantages of no lateral diffusion, low temperature, and wide range of selectable doping materials, wherein the ion implantation ionizes atoms or molecules to be doped, and then accelerates to a certain energy to implant the atoms or molecules into the film layer 120 to be etched, so as to achieve the purpose of doping, thereby forming a doping region 121 in the film layer 120 to be etched in the longitudinal direction perpendicular to the substrate 110, and the depth of the doping region 121 is L1. Since in executing step S103: before the ion implantation is performed on the film layer 120 to be etched, step S105 is performed: the patterned photoresist layer 130 corresponding to the opening 140 is formed on the film layer to be etched 120, so as to allow ions to be implanted into a portion of the film layer to be etched 120 corresponding to the opening 140, since the patterned photoresist layer 130 is formed on the film layer to be etched 120 as a protective film for ion implantation during ion implantation, ion implantation can be performed only in the portion of the patterned photoresist layer 130 corresponding to the opening 140, and the doped region 121 with a depth of L1 as shown in fig. 4 is formed by controlling the energy and the concentration of the dopant during ion implantation.
Since ion implantation is likely to damage the wafer surface, step S103 is generally performed after: after the ion implantation is performed on the film layer 120 to be etched, an annealing step needs to be performed.
Specifically, in the ion implantation process, due to collision of incident ions, damage may be caused to the crystal structure of the ion-implanted surface film layer, and after the ion implantation is performed on the film layer to be etched 120, by performing an annealing step, rapid surface heating is provided to repair the damage without making the temperature of the surface film layer reach a diffusion degree.
And S104: at least one opening 140 is formed in the film layer to be etched 120 in a longitudinal direction perpendicular to the substrate 110, and the opening 140 includes a first portion (i.e., an upper portion of the opening 140) and a second portion (i.e., a lower portion of the opening 140), wherein a longitudinal depth of the first portion corresponds to the specific depth L1, and a cross-sectional width of a longitudinal lower end of the first portion is greater than a cross-sectional width of a longitudinal upper end of the second portion.
Wherein, the step S104 specifically includes:
at least one opening 140 is formed in the film layer to be etched 120 in a longitudinal direction perpendicular to the substrate 110 through a dry etching process.
Fig. 6 shows the structure formed in step S104, which includes: the thin film transistor includes a substrate 110, a film layer 120 to be etched on the substrate 110, an opening 140 in the film layer 120 to be etched in a longitudinal direction perpendicular to the substrate 110, and a doped region 121 around the opening 140.
Wherein, the material of the film layer 120 to be etched includes oxide.
Specifically, at least one opening 140 is formed in the film layer 120 to be etched in a direction perpendicular to the longitudinal direction of the substrate 110 by using an anisotropic dry etching process, and the material of the film layer 120 to be etched is generally a non-metal, such as an oxide (SiO)2) SiN, or SiON, etc., when the material of the film 120 to be etched is silicon dioxide (SiO)2) When used, the etching gas may be carbon tetrafluoride (CF)4) And oxygen (O)2) By anisotropic dry etching, when the reaction time reaches a certain set value or when the thickness of the film to be etched reaches a certain set value, the reaction is stopped, so as to precisely control the formation of the at least one opening 140 in the film to be etched 120 in the direction perpendicular to the longitudinal direction of the substrate 110 without damaging other films to be remained.
Specifically, in executing step S103: after the ion implantation is performed on the film layer 120 to be etched, the step S104 is continuously performed: at least one opening 140 is formed in the film layer 120 to be etched in a direction perpendicular to the longitudinal direction of the substrate 110, since the film layer 120 to be etched is subjected to ion implantation before the opening 140 is formed by the etching process, the ion implantation changes the film layer structure of the film layer 120 to be etched, i.e., the film layer of the ion-implanted doped region 121 (corresponding to the region to be etched to form the opening 140) becomes loose due to the ion implantation, correspondingly, the film layer 120 to be etched corresponding to the doped region 121 is more easily etched than the film layer 120 to be etched of other regions not being ion-implanted, and when the film layer 120 to be etched is subjected to the etching process, the etching Rate (Etch Rate, ER) of the film layer 120 to be etched corresponding to the doped region 121 is faster than the etching Rate of the film layer 120 to be etched of other regions not being ion-implanted, and a difference in etching Rate is formed, so that the opening 140 having a cross-sectional width at the lower longitudinal end of the first portion larger than the cross-sectional width at the upper longitudinal end of the second portion is formed Therefore, the problem that residues (Residue) generated by deep hole etching are difficult to clean is solved, and the requirement of mass production is met.
In addition, it should be noted that, in the process of forming the opening 140 by performing the dry etching process, as the depth of the opening 140 gradually increases, the polymer (polymer) generated in the etching process is more difficult to clean, and correspondingly, the physical bombardment of the dry etching and the chemical reaction of the etching gas gradually decrease, so that, at the initial stage of forming the opening 140 by the dry etching process, due to the influence of the ion implantation on the film structure of the film layer 120 to be etched, a first portion with a larger cross-sectional width at the longitudinal lower end is formed, and as the depth of the opening 140 gradually increases, due to the restriction of the opening 140 with a high aspect ratio, the influence of the ion implantation on the etching rate of the film layer 120 to be etched is reduced, a second portion is gradually formed in the first portion of the opening, that is, the opening is divided into two portions, the first portion and the second portion, there is a transitional interface between the first portion and the second portion, i.e. the longitudinal cross-section between the first and second portions is formed with a level difference. In general, the depth L2 of the first portion of the opening is positively correlated with the depth L1 of the ion implantation, but the depth L2 of the first portion is smaller than the depth L1 of the ion implantation, subject to the high aspect ratio opening 140.
In addition, the ion implantation and the dry etching process can be combined, namely, the depth and the appearance of the formed opening are controlled by controlling the ion implantation energy and the concentration of the ion implanted dopant, and the dry etching process optimization idea is matched to break through the bottleneck of the etching process. Dry etching is the physical bombardment with plasma and chemical reaction of the etching gas to form the opening 140, and the etching gas (e.g., CF) can be controlled2、CF4、C4F6、CH2F2Or O2) The flow rate (Gas flow), Power (Power) or Gap (Gap, i.e. the Gap between the wafer and the top inner wall of the etching reaction chamber) in the etching reaction, and the like, and then, in cooperation with the depth control of the ion implantation process, at least one opening 140 is formed in the film layer to be etched, wherein the width of the cross section of the lower end of the first part in the longitudinal direction is larger than that of the upper end of the second part in the longitudinal direction, and the opening is perpendicular to the longitudinal direction of the substrate, so that the problem that residues generated by deep hole etching are difficult to clean is solved, and the requirement of mass production is met.
The dopant for ion implantation includes a non-charged substance or a non-charged substance.
Specifically, as can be seen from the foregoing, the purpose of the ion implantation is to change the film structure of the film layer 120 to be etched, and the control of the depth of the doped region 121 of the film layer 120 to be etched is realized by controlling the energy of the ion implantation and the concentration of the dopant, so as to control the ratio of the etching rate of the film layer 120 to be etched corresponding to the doped region 121 to the etching rate of the film layer 120 to be etched in other regions that are not ion implanted, and further realize the control of the shape of the opening 140, the cross section of the longitudinal lower end of the first portion of the opening 140, and the cross section width of the longitudinal upper end of the second portion of the opening 140. By controlling the shape of the opening 140, it is advantageous to completely remove residue from the bottom wall of the opening 140. By controlling the cross-sectional width of the upper end of the second portion of the opening 140 in the longitudinal direction, that is, by forming a small dimension (CD) only at the bottom of the second portion of the opening 140, the size of other structures electrically connected thereto can be made smaller, which is advantageous for improving the integration of the semiconductor device.
Wherein the uncharged species comprises argon.
As can be seen from the foregoing, since the film structure of the film 120 to be etched only needs to be changed by ion implantation, so that the film 120 to be etched, which is subjected to ion implantation, becomes loose, and accordingly, the etching rate of the film 120 to be etched, which is subjected to ion implantation, is faster, in general, a non-charged substance is used as a dopant for ion implantation, such as argon (Ar), an inert gas, which does not chemically react with other substances at normal temperature and is not dissolved in liquid metal at high temperature, and based on the characteristics of argon, argon is used as a dopant for ion implantation, so that only changing the etching rate of the film 120 to be etched, which is subjected to ion implantation, can be achieved without changing the electrical properties of the film 120 to be etched.
The charged substance includes boron or phosphorus.
In addition, a charged substance may also be used as a dopant for ion implantation, such as the most commonly used dopant, and ions containing boron or phosphorus, in general, by using ions containing boron as the dopant for ion implantation, the content of the carriers in the film layer 120 to be etched, which are holes, can be increased, and by using ions containing phosphorus as the dopant for ion implantation, the content of the carriers in the film layer 120 to be etched, which are electrons, can be increased, when the content of the carriers in the film layer 120 to be etched increases, correspondingly, the electrical properties of the film layer 120 to be etched change, and then, at least one opening 140 is formed in the film layer 120 to be etched in the vertical direction to the substrate 110, the opening 140 is filled with a metal material, and the opening 140 after being filled with the metal material is used as a conducting wire for electrically connecting the upper and lower film layers of the opening, and a suitable dopant can be selected according to actual requirements, while forming the required opening 140 topography, certain electrical properties can also be satisfied.
The above steps are the first embodiment of the present invention, break through the bottleneck of the etching process, and at the same time, solve the problem that the residue generated by deep hole etching is difficult to be cleaned, so as to meet the requirement of mass production, as shown in fig. 7, a schematic flow diagram of a manufacturing method of a semiconductor structure according to another embodiment of the present invention is shown, and the specific flow chart compares with the structural diagrams of fig. 2-3 and 8-10, and may include the following steps:
as shown in fig. 7, steps S101 to S104 of the method for fabricating a semiconductor structure according to another embodiment of the present invention are the same, wherein the structures formed in steps S101 and S102 are respectively shown in fig. 2 and fig. 3, which have been described in detail above and are not repeated herein, and since step S105 of the above embodiment is not performed before step S103, the structure formed in step S103 in another embodiment of the present invention is different from the structure formed in step S103 of the above embodiment.
Fig. 8 shows a structure formed in step S103 in another embodiment, which includes: the substrate 110 and the film layer to be etched 120 on the substrate 110 form a complete doped region 121 in the film layer to be etched 120 in a direction perpendicular to the longitudinal direction of the substrate 110.
Unlike the structure formed by the step S103 shown in fig. 5, since there is no step S105 performed before the step S103 is performed: the patterned photoresist layer 130 corresponding to the opening 140 is formed on the film layer 120 to be etched, so that ions are implanted into a portion of the film layer 120 to be etched corresponding to the opening 140, that is, the patterned photoresist layer 130 corresponding to the opening 140 is not formed on the film layer 120 to be etched as a protection layer, and when the step S103 is performed, since there is no protection layer covering the film layer 120 to be etched, a complete doped region 121 as shown in fig. 8 is formed in the film layer 120 to be etched in a direction perpendicular to the longitudinal direction of the substrate 110. And then by controlling the energy and the dopant concentration during the ion implantation process, a doped region 121 with a depth L3 as shown in fig. 8 is formed.
After step S103, the method further includes:
s106, a step: a patterned photoresist layer 130 having openings 140 corresponding to the openings is formed on the film layer 120 to be etched.
Fig. 9 shows a structure formed in step S106 in another embodiment, including: the method includes the steps of forming a substrate 110, a film layer to be etched 120 on the substrate 110, a doped region 121 in the film layer to be etched 120 in a direction perpendicular to a longitudinal direction of the substrate 110, and forming a patterned photoresist layer 130 having an opening 140 on the film layer to be etched 120.
Specifically, the pattern on the mask is accurately copied onto the photoresist layer 130 coated on the surface of the film layer 120 to be etched through a photolithography process to form the patterned photoresist layer 130 having the openings 140 on the film layer 120 to be etched, so that at least one opening 140 is formed in the film layer 120 to be etched in a longitudinal direction perpendicular to the substrate 110.
In addition, a hard mask layer and an anti-reflection layer (not shown in the figures) may be sequentially stacked between the film layer to be etched 120 and the patterned photoresist layer 130, which are not described herein again because they have been described in detail above.
Fig. 10 shows a structure formed in step S104 in another embodiment, including: the etching method includes the steps of a substrate 110, a film layer to be etched 120 on the substrate 110, a doped region 121 in the film layer to be etched 120 in a longitudinal direction perpendicular to the substrate 110, and at least one opening 140 formed in the film layer to be etched 120 in the longitudinal direction perpendicular to the substrate 110, wherein the opening 140 includes a first portion and a second portion, the longitudinal depth of the first portion is L3, and the cross-sectional width of the longitudinal lower end of the first portion is greater than the cross-sectional width of the longitudinal upper end of the second portion. As can be seen from the above, the depth L4 of the first portion of the opening 140 is generally positively correlated with the depth L3 of the ion implantation, but the depth L4 of the first portion is smaller than the depth L3 of the ion implantation due to the high aspect ratio of the opening 140.
Specifically, at least one opening 140 is formed in the film layer 120 to be etched in a direction perpendicular to the longitudinal direction of the substrate 110 by using an anisotropic dry etching process, and the material of the film layer 120 to be etched is generally a non-metal, such as an oxide (SiO)2) SiN, or SiON, etc., when the material of the film 120 to be etched is silicon dioxide (SiO)2) When used, the etching gas may be carbon tetrafluoride (CF)4) And oxygen (O)2) By anisotropic dry etching, when the reaction time reaches a certain set value or when the thickness of the film to be etched reaches a certain set value, the reaction is stopped, so as to precisely control the formation of the at least one opening 140 in the film to be etched 120 in the direction perpendicular to the longitudinal direction of the substrate 110 without damaging other films to be remained.
As can be seen from the foregoing, the purpose of the ion implantation is to change the film structure of the film 120 to be etched, and the control of the depth of the doped region 121 of the film 120 to be etched is realized by controlling the ion implantation energy and the dopant concentration, so as to control the ratio of the etching rate of the film 120 to be etched corresponding to the doped region 121 to the etching rate of the film 120 to be etched in other regions that are not ion implanted, and further realize the control of the shape of the opening 140, the cross section of the longitudinal lower end of the first portion of the opening 140, and the cross section width of the longitudinal upper end of the second portion of the opening 140. By controlling the shape of the opening 140, it is advantageous to completely remove residue from the bottom wall of the opening 140. By controlling the cross-sectional width of the upper end of the second portion of the opening 140 in the longitudinal direction, that is, by forming a small dimension (CD) only at the bottom of the second portion of the opening 140, the size of other structures electrically connected thereto can be made smaller, which is advantageous for improving the integration of the semiconductor device.
In addition, the dopant for ion implantation may be a non-charged species, such as argon, or a charged species, such as boron or phosphorus-containing ions, which have been described in detail above and will not be described herein.
After step S104, the method further includes:
the opening 140 is cleaned to remove the residue in the opening 140.
Specifically, the cleaning process may include plasma dry stripping and/or wet etching, wherein the patterned photoresist layer 130 is removed by plasma dry stripping and/or wet etching, carbon dioxide and water are generated by reaction of active oxide groups in plasma with the photoresist in a plasma dry stripping manner, the plasma dry stripping has high precision and is performed in vacuum to ensure that the cleaning surface is not secondarily contaminated, or the wet etching manner is performed, and a chemical solution with a certain selectivity ratio is used to ensure that the solution has a high etching rate for the patterned photoresist layer 130 (photoresist material) and a low etching rate for other film layers, so that other film layers are not substantially damaged when the patterned photoresist layer 130 is removed, for example, sulfuric acid (H) is used to remove the patterned photoresist layer 1302SO4) And hydrogen peroxide (H)2O2) Strong oxidation ofOxidizing the main component C, H in the photoresist to form CO2And H2And O, thereby removing the photoresist. In order to completely remove the patterned photoresist layer 130 to avoid the defects caused by the influence of the residues on the subsequent process, it is preferable that the patterned photoresist layer 130 is completely removed by using the plasma dry photoresist removal and the wet etching in combination or by using the plasma dry photoresist removal or the wet etching for multiple times.
Subsequently, the opening 140 is subjected to a next cleaning process, i.e., a cleaning process (Clean), to remove residues from the bottom wall and the side wall of the opening 140. In wafer processing, it is necessary to form a film on a wafer or perform high-temperature heat treatment, and it is generally necessary to clean the wafer to remove foreign substances such as surface contamination and impurities before performing these treatments. The wafer is immersed in an acid solution to dissolve and remove foreign materials, rinsed with flowing pure water, dried to remove water, and the like, thereby completely removing residues on the bottom and side walls of the opening 140. In general, the cleaning process has a long route and is repeated for many times, which is indispensable.
Wherein the opening 140 includes any one or more of a via hole, a groove, or a contact hole.
Specifically, since the opening 140 may be any one or more of a Via (Via), a recess (Metal), or a Contact (Contact), in general, the Contact may be counted as one of the vias. Hydrofluoric acid (HF) and hydrogen peroxide (H) may be used when the opening 140 is a via, a trench, or a contact hole and the bottom of the opening 140 is tungsten, silicon, or other non-nickel Silicide (nickel Silicide) material2O2) The opening 140 is cleaned to remove Residue (Residue) from the bottom and side walls of the opening 140. When the opening 140 is a via, a groove or a contact hole and the bottom material of the opening 140 needs to be nickel silicide in order to realize ohmic contact between the opening 140 and metal lines electrically connected to the upper and lower sides of the opening 140 (the metal and the semiconductor form a small pure resistance at the contact position), hydrofluoric acid cannot be used for cleaning based on the characteristics of nickel silicide, and hot sulfuric acid (H) can be used2SO4) And hydrogen peroxide to clean the opening 140 to remove residues on the bottom wall and the side wall of the opening 140The film layer of the nickel silicide is not damaged.
Wherein the cross-sectional shape of the first portion comprises an inverted trapezoid.
Specifically, since the cross-sectional shape of the opening 140 is an inverted trapezoid (also referred to as a trumpet), it is advantageous to completely remove residues from the bottom and side walls of the opening 140. However, the openings 140 of the prior art are generally completely vertical or have a slightly inclined angle, and it is difficult to completely remove the residues on the bottom wall of the openings 140 with the vertical or slightly inclined angle by the cleaning process, which results in the DVC (Dark Voltage Contrast) defect, and thus the requirement of mass production cannot be satisfied. Through adopting the opening 140 with the inverted trapezoid-shaped cross section, the residues on the bottom wall and the side wall of the opening 140 can be cleared completely, meanwhile, through adopting the scheme that the opening 140 with the inverted trapezoid-shaped cross section is adopted, under the condition that the residues on the bottom wall and the side wall of the opening 140 are cleared completely, the size of the second part of the opening 140 can be designed to be smaller than the corresponding size in the prior art, the sizes of other structures electrically connected with the opening can be made smaller, and the integration level of a semiconductor device can be improved.
After step S104, the method further includes:
the opening 140 is filled with a metal material.
Specifically, based on the schematic structural diagram of forming the opening 140 in fig. 6, the opening 140 is filled with a metal material, as shown in fig. 11, which is a schematic structural diagram of a semiconductor structure formed in an embodiment of the present invention, and the schematic structural diagram includes: the thin film transistor array substrate comprises a substrate 110, a film layer to be etched 120 on the substrate 110, a doped region 121 in the film layer to be etched 120 in a longitudinal direction perpendicular to the substrate 110, and at least one filling block 141 formed in the film layer to be etched 120 in a longitudinal direction perpendicular to the substrate 110, wherein the filling block 141 comprises a first portion and a second portion, wherein a longitudinal depth of the first portion corresponds to a specific depth L1, and a cross-sectional width of a longitudinal lower end of the first portion is greater than a cross-sectional width of a longitudinal upper end of the second portion.
Specifically, since the step S103 is executed: before the ion implantation is performed on the film layer 120 to be etched to the specific depth L1, step S105 is performed: the patterned photoresist layer 130 corresponding to the opening 140 is formed on the film layer 120 to be etched, so as to allow ions to be implanted into a portion of the film layer 120 to be etched corresponding to the opening 140, during ion implantation, the patterned photoresist layer 130 is formed on the film layer 120 to be etched as a protective film for ion implantation, and only a portion of the patterned photoresist layer 130 corresponding to the opening 140 can be subjected to ion implantation, so that the doped region 121 around the filling block 141 is small.
Different from the schematic structural view of forming the opening 140 in fig. 6, based on the schematic structural view of the opening 140 formed in fig. 10, the opening 140 is filled with a metal material, as shown in fig. 12, which is a schematic structural view of a semiconductor structure formed in another embodiment of the present invention, and includes: the thin film transistor array substrate comprises a substrate 110, a film layer to be etched 120 on the substrate 110, a doped region 121 in the film layer to be etched 120 in a longitudinal direction perpendicular to the substrate 110, and at least one filling block 141 formed in the film layer to be etched 120 in a longitudinal direction perpendicular to the substrate 110, wherein the filling block 141 comprises a first portion and a second portion, wherein a longitudinal depth of the first portion corresponds to a specific depth L3, and a cross-sectional width of a longitudinal lower end of the first portion is greater than a cross-sectional width of a longitudinal upper end of the second portion.
Specifically, since the step S105 is not performed before the ion implantation of the step S103 is performed: the patterned photoresist layer 130 corresponding to the opening 140 is formed on the film layer to be etched 120, so that ions are implanted into a portion of the film layer to be etched 120 corresponding to the opening 140, that is, the patterned photoresist layer 130 corresponding to the opening 140 is not formed on the film layer to be etched 120 as a protection layer, and when the ion implantation in step S103 is performed, since there is no protection layer covered on the film layer to be etched 120, the doping region 121 around the filling block 141 is relatively large.
Wherein the metal material comprises any one of tungsten, copper or aluminum.
Specifically, a uniform metal thin film may be formed within the opening 140 using Physical Vapor Deposition (PVD) to completely fill the opening 140 to form the filling block 141 corresponding to the shape of the opening 140. The metal material filled in the opening 140 may be any one of tungsten, copper, or aluminum, or other metal materials, as long as the opening 140 can be completely filled to form a filling block 141 corresponding to the shape of the opening 140, and the filling block 141 can function as a conductive line, which is not limited specifically.
In addition, in order to ensure that the opening 140 is completely filled, the height of the formed filling block 141 is generally higher than the height of the film layer 120 to be etched, and the surface of the filling block 141 is not flat, Chemical Mechanical Polishing (CMP) may be performed to make the surface of the filling block 141 level with the height of the film layer 120 to be etched, and to make the surface of the filling block 141 flat.
In addition, the prior art opening 140 is generally a completely vertical opening 140 or has a slightly small inclination angle, since the top slope of the prior art opening 140 is too steep to be completely filled when filling the metal material, so that a gap (Void) exists in the middle filling, and cracks (Crack) may be formed on the top after the chemical mechanical polishing is performed, which affects the circuit connection, and thus the quality and yield of the product are affected. The shape of the opening 140 is designed to be inverted trapezoid (or called as trumpet shape), and the shape of the inverted trapezoid opening 140 is beneficial to filling of metal materials, so that gaps formed in the process of filling the opening 140 are reduced, cracks are avoided after chemical mechanical polishing, and the quality and yield of products are improved.
Based on the manufacturing method of the semiconductor structure described in the above embodiment, an embodiment of the present application further provides a semiconductor structure, including: a substrate 110 and a dielectric layer on the substrate 110, at least one filling block 141 formed in the dielectric layer in a direction perpendicular to a longitudinal direction of the substrate 110, the filling block 141 including a first portion (i.e., an upper portion of the filling block 141 as shown in fig. 11) and a second portion (i.e., a lower portion of the filling block 141 as shown in fig. 11), wherein a longitudinal depth of the first portion corresponds to a specific depth L3, and a cross-sectional width of a longitudinal lower end of the first portion is greater than a cross-sectional width of a longitudinal upper end of the second portion.
As shown in fig. 11, which is a schematic structural diagram of a semiconductor structure formed in an embodiment of the present invention, the semiconductor structure includes: the etching method includes the steps of forming a substrate 110, a film layer 120 to be etched (i.e., a dielectric layer) on the substrate 110, forming at least one filling block 141 in the film layer 120 to be etched in a direction perpendicular to a longitudinal direction of the substrate 110, and a doped region 121 around the filling block 141, wherein the filling block 141 includes a first portion and a second portion, a longitudinal depth of the first portion corresponds to a specific depth L1, a longitudinal cross section between the first portion and the second portion of the filling block 141 is formed with a step difference, and a cross sectional width of a longitudinal lower end of the first portion is greater than a cross sectional width of a longitudinal upper end of the second portion.
In addition, it should be noted that, when the filling block 141 is formed after the ion implantation is performed, if the width of the ion implantation is smaller than the width of the filling block 141, the finally formed semiconductor structure does not have the doped region 121. In order to form the filling block 141 having a cross-sectional width at the lower end of the first portion in the longitudinal direction larger than that at the upper end of the second portion in the longitudinal direction, the width of the ion implantation is generally larger than that for forming the filling block 141, i.e., the doping region 121 exists in the finally formed semiconductor structure.
Unlike the scheme of the doped region 121 of the semiconductor structure shown in fig. 11, as shown in fig. 12, a schematic structural diagram of a semiconductor structure formed in another embodiment of the present invention includes: the etching method includes the steps of forming a substrate 110, a film layer 120 to be etched (i.e., a dielectric layer) on the substrate 110, forming at least one filling block 141 in the film layer 120 to be etched in a direction perpendicular to a longitudinal direction of the substrate 110, and a doped region 121 around the filling block 141, wherein the filling block 141 includes a first portion and a second portion, a longitudinal depth of the first portion corresponds to a specific depth L3, a longitudinal cross section between the first portion and the second portion of the filling block 141 is formed with a step difference, and a cross sectional width of a longitudinal lower end of the first portion is greater than a cross sectional width of a longitudinal upper end of the second portion.
In addition, it should be noted that, since the ion implantation is performed on the entire film layer to be etched, the width of the ion implantation is always greater than the width of the opening 140, and then the opening 140 is filled with a metal material to form the filling block 141, the finally formed semiconductor structure must have the doping region 121, the size of the doping region 121 is related to the size of the filling block 141, and the larger the volume of the filling block 141 is, the smaller the volume of the doping region 121 is.
As shown in fig. 11 or 12, a longitudinal section between the first portion and the second portion of the filling block 141 is formed with a step, and a longitudinal lower end of the first portion has a cross-sectional width greater than a longitudinal upper end of the second portion. As can be seen from the above, as the depth of the opening 140 gradually increases and the influence of the ion implantation on the etching rate of the film layer 120 to be etched decreases due to the restriction of the opening 140 with a high aspect ratio, a second portion is gradually formed in the first portion of the opening, that is, the opening is divided into two portions, the first portion and the second portion, and a transitional interface exists between the first portion and the second portion, that is, a step difference is formed in the longitudinal cross section between the first portion and the second portion. Subsequently, the opening 140 is filled with a metal material, and a filling block 141 having a level difference formed in a longitudinal section between the first portion and the second portion is formed.
In addition, it should be noted that, by adjusting the ion implantation energy, the dopant concentration and the etching process parameters, the opening 140 having no level difference in the longitudinal section between the first portion and the second portion may be formed, and finally the filling block 141 having no level difference may be formed in the longitudinal section between the first portion and the second portion.
Wherein, the longitudinal section of the first part and the second part forms a step difference, and the cross-sectional shape of the filling block 141 comprises an inverted trapezoid.
Specifically, as can be seen from the above, since the cross-sectional shape of the opening 140 is an inverted trapezoid, it is more beneficial to remove the residues on the bottom wall and the side wall of the opening 140, so as to meet the requirement of mass production. Meanwhile, the shape of the opening 140 is inverted trapezoid, which is more beneficial to filling the opening 140, so as to avoid forming a gap in the process of filling the metal material, which affects the circuit connection, and thus affects the quality and yield of the product. Accordingly, the cross-sectional shape of the formed filling block 141 is an inverted trapezoid, which has been described in detail above and will not be described herein.
Wherein, the material of the filling block 141 includes any one of tungsten, copper or aluminum.
Specifically, in general, the filling block 141 mainly functions as a conductive line, that is, the substrate 110 under the filling block 141 is electrically connected to other film layers directly contacting above the filling block 141 through the filling block 141. In the semiconductor device, the Via (Via) fill 141, the Metal (Metal) fill 141, or the Contact (Contact) fill 141 is generally referred to as the Via (Via) fill 141, and the Contact may be generally counted as one of the Via holes, and the material of the fill 141 is generally tungsten, copper, or aluminum. The via filling block 141 is mainly used to connect metal lines across layers, and is generally applied to an array memory structure or a peripheral circuit; the groove filling block 141 is mainly used as a Bit Line (Bit Line) or a metal Line in an array memory structure or a peripheral circuit; the contact Hole filling block 141 is mainly used as a connection Line for connecting a functional element (such as a filled Channel/Channel Hole or a Gate isolation structure/Gate Line Slit) and a metal Line, and is applied to an array memory structure.
Based on the manufacturing method of the semiconductor structure described in the above embodiments, the present application further provides a three-dimensional memory (not shown in the drawings), where the three-dimensional memory includes an array memory structure and a peripheral circuit, where any one of the semiconductor structures is located in the array memory structure and/or the peripheral circuit, and the filling blocks in the semiconductor structure include any one or more of via filling blocks, recess filling blocks, or contact hole filling blocks.
Specifically, the three-dimensional memory (3D NAND Flash) includes an Array memory structure (Array) and a peripheral Circuit (peripheral Circuit), any one of the semiconductor structures is located in the Array memory structure and/or the peripheral Circuit, wherein the Array memory structure is used for storing information, and the peripheral Circuit can be located above or below the Array memory structure or located around the Array memory structure, and the peripheral Circuit is used for controlling the corresponding Array memory structure. In addition, the semiconductor structure can also be applied to other microelectronic devices, such as a non-volatile Flash (Nor Flash) and the like, and is not particularly limited.
In particular, when the semiconductor structure is applied in a three-dimensional memory, the filling blocks in the semiconductor structure may be any one or more of via filling blocks, recess filling blocks, or contact hole filling blocks. In order to continuously increase the storage capacity without increasing the storage area, it is necessary to increase the storage density and reduce the size, i.e., it is necessary to increase the height of the gate layers and the insulating layers which are alternately stacked and to reduce the size of the devices in the semiconductor structure, when the filling blocks are via filling blocks, correspondingly, the size of the via filling blocks is also increasingly smaller, and the depth of the via filling blocks is increasingly larger. Typically, the via fill blocks may be located in the peripheral circuitry as metal connections for electrically connecting the array memory structure and the peripheral circuitry. The forming process of the through hole filling block comprises the following steps: firstly, forming a through hole by an etching process; then, the through holes are cleaned, and finally, the through holes are filled with a metal material, such as tungsten, to form through hole filling blocks. Because the size of through-hole filling block is more and more littleer, and the degree of depth of through-hole filling block is more and more big, correspondingly, the size of through-hole is also more and more littleer, and the degree of depth of through-hole is more and more big, leads to when wasing the through-hole, and the residue that the deep hole sculpture produced is difficult to by the clearance, leads to the DVC defect, can't satisfy the needs of volume production. Through forming the through hole with the cross section width of the longitudinal lower end of the first part larger than that of the longitudinal upper end of the second part, the problem that residues generated by deep hole etching are difficult to clean is solved, and the requirement of mass production is met.
In addition, the filling blocks in the semiconductor structure can also be groove filling blocks or contact hole filling blocks. The groove filling blocks are mainly applied to peripheral circuits as Bit lines (Bit lines) or metal lines, and are used for electrically connecting the array memory structure and the peripheral circuits through one or more through hole filling blocks. The contact Hole filling block is mainly used in the array memory unit as a connecting Line for connecting functional elements (such as a Gate layer, a filled Channel/Channel Hole or a Gate isolation structure/Gate Line Slit), and is used for electrically connecting the Gate layer of a step region in the array memory unit with a peripheral circuit, or electrically connecting the Channel structure in the array memory unit with the peripheral circuit. As can be seen from the above, in order to continuously increase the storage capacity without increasing the storage area, the storage density needs to be increased and the sizes of the grooves and the contact holes need to be reduced, and the sizes of the grooves and the contact holes become smaller and smaller, and the grooves or the contact holes with the cross section width at the lower end in the longitudinal direction of the first portion larger than the cross section width at the upper end in the longitudinal direction of the second portion are formed, so that the problem that residues generated by deep hole etching are difficult to clean is solved, and the requirement of mass production is met.
Different from the prior art, the semiconductor structure, the manufacturing method and the three-dimensional memory in the embodiment of the invention are different from the prior art, and the manufacturing method of the semiconductor structure includes: providing a substrate; forming a film layer to be etched on a substrate; performing ion implantation on the film layer to be etched to reach a specific depth; at least one opening is formed in the film layer to be etched in the longitudinal direction perpendicular to the substrate, the opening comprises a first part and a second part, the longitudinal depth of the first part corresponds to a specific depth, the cross section width of the longitudinal lower end of the first part is larger than that of the longitudinal upper end of the second part, the etching rate of the film layer to be etched, which is subjected to ion implantation, is changed by performing etching after the film layer to be etched is subjected to ion implantation, so that at least one opening is formed in the film layer to be etched, wherein the cross section width of the longitudinal lower end of the first part is larger than that of the longitudinal upper end of the second part, the problem that residues generated by deep hole etching are difficult to clean is solved, and the requirement of mass production is met.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (18)

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a film layer to be etched on the substrate;
performing ion implantation on the film layer to be etched;
and forming at least one opening in the film layer to be etched in a longitudinal direction perpendicular to the substrate, wherein the opening comprises a first part and a second part, and the cross-sectional width of the longitudinal lower end of the first part is larger than that of the longitudinal upper end of the second part.
2. The method for fabricating a semiconductor structure according to claim 1, further comprising, before the step of performing ion implantation on the film layer to be etched:
and forming a patterned photoresist layer corresponding to the opening on the film layer to be etched so as to inject the ions into the part, corresponding to the opening, in the film layer to be etched.
3. The method for fabricating a semiconductor structure according to claim 1, further comprising, after the performing ion implantation on the film layer to be etched:
and forming a patterned photoresist layer corresponding to the opening on the film layer to be etched.
4. The method of claim 1, wherein a longitudinal cross-section between the first portion and the second portion is formed with a step, and a cross-sectional shape of the first portion includes an inverted trapezoid.
5. The method of claim 1, wherein the opening comprises any one or more of a via, a recess, or a contact hole.
6. The method of manufacturing a semiconductor structure according to claim 1, wherein at least one of the openings is formed in the film layer to be etched in a direction perpendicular to a longitudinal direction of the substrate by a dry etching process.
7. The method for fabricating a semiconductor structure according to claim 1, further comprising, after forming at least one opening in the film layer to be etched in a direction perpendicular to the longitudinal direction of the substrate:
and cleaning the opening to remove residues in the opening.
8. The method for fabricating a semiconductor structure according to claim 1, further comprising, after forming at least one opening in the film layer to be etched in a direction perpendicular to the longitudinal direction of the substrate:
and filling a metal material in the opening.
9. The method of claim 8, wherein the metal material comprises any one of tungsten, copper, or aluminum.
10. The method of claim 1, wherein the ion implanted dopant comprises a non-charged species or a non-charged species.
11. The method of claim 10, wherein the non-charged species comprises argon.
12. The method of claim 10, wherein the electrically charged species comprises boron or phosphorous.
13. The method of claim 1, wherein the material of the film to be etched comprises an oxide.
14. The method of claim 1, wherein the film to be etched further comprises a hard mask layer and an anti-reflection layer stacked in sequence.
15. A semiconductor structure, comprising: the filling block comprises a first part and a second part, wherein the cross section width of the lower end of the first part in the longitudinal direction is larger than that of the upper end of the second part in the longitudinal direction.
16. The semiconductor structure of claim 15, wherein a longitudinal cross-section between the first portion and the second portion is formed with a step, and a cross-sectional shape of the fill block comprises an inverted trapezoid.
17. The semiconductor structure of claim 15, wherein a material of the fill block comprises any of tungsten, copper, or aluminum.
18. A three-dimensional memory comprising an array memory structure and peripheral circuitry, wherein the semiconductor structure of any of claims 15 to 17 is located in the array memory structure and/or the peripheral circuitry, and wherein the fill blocks in the semiconductor structure comprise any one or more of via fill blocks, recess fill blocks, or contact hole fill blocks.
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