CN113808642A - Data access system and method of operating a data access system - Google Patents
Data access system and method of operating a data access system Download PDFInfo
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- CN113808642A CN113808642A CN202010540501.4A CN202010540501A CN113808642A CN 113808642 A CN113808642 A CN 113808642A CN 202010540501 A CN202010540501 A CN 202010540501A CN 113808642 A CN113808642 A CN 113808642A
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- 238000000034 method Methods 0.000 title description 17
- 238000011084 recovery Methods 0.000 claims abstract description 15
- 238000010586 diagram Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 3
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- Microelectronics & Electronic Packaging (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The data access system comprises a flash memory, a first inverter circuit, a block temporary memory, an error checking and correcting circuit, a second inverter circuit and an application circuit. The first inversion circuit inverts a plurality of data stored in a first block of the flash memory to generate a plurality of inverted data. The block temporary storage memory stores a plurality of reverse data. When the error checking and correcting circuit judges that the plurality of pieces of reverse data are correctable, the error checking and correcting circuit corrects at least one piece of reverse data stored in the block temporary storage memory. The second reversing circuit reverses the values of the plurality of reverse data in the block temporary storage memory to generate a plurality of recovery data. The application circuit receives the plurality of restoration data and executes corresponding operation according to the plurality of restoration data.
Description
Technical Field
The present invention relates to a data access system, and more particularly, to a data access system capable of simplifying a data access procedure.
Background
Flash memory (Flash) is widely used in various systems because of its non-volatile (non-volatile) and write-many characteristics. In general, flash memory can only write to blocks that have not yet been written to. Therefore, before writing to the flash memory, it is necessary to determine whether the block to be written has not been written yet; if the block has been previously written with data, the block must be cleared to enable new data to be written. In addition, because the Error rate of the flash memory is high, before writing to the flash memory, an Error Checking and Correcting (ECC) circuit is used to determine whether the block is a bad block. If there are too many bit errors in a block, the error checking and correcting circuit determines the block as an untrusted bad block. At this time, in order to maintain the correctness of the data, the system will additionally look for good blocks (good blocks) in the flash memory to store the data.
In the prior art, since the error checking and correcting circuit often determines the unwritten block as a bad block, a complicated additional circuit is often required for further determination, which complicates the process of accessing the flash memory.
Disclosure of Invention
One embodiment of the present invention provides a data access system. The data access system comprises a flash memory, a first inverter circuit, a block temporary memory, an error checking and correcting circuit, a second inverter circuit and an application circuit.
The flash memory includes a plurality of blocks. The first inversion circuit receives a plurality of first data stored in a block and inverts values of the first data to generate a plurality of first inverted data. The block temporary storage memory is coupled to the first reverse circuit and stores the first reverse data.
The error checking and correcting circuit is coupled to the first inverting circuit and the block temporary memory. The error checking and correcting circuit judges whether the first reverse data are correctable, and corrects at least one piece of first reverse data stored in the block temporary storage when the first reverse data are judged to be correctable. The second inverting circuit is coupled to the block temporary storage memory, receives the first inverted data in the block temporary storage memory, and inverts values of the first inverted data to generate a plurality of first recovery data. The application circuit receives the first recovery data and executes corresponding operation according to the first recovery data.
Another embodiment of the present invention provides a method of operating a data access system. The data access system comprises a flash memory, a block temporary storage memory, an error checking and correcting circuit and an application circuit, wherein the flash memory comprises a plurality of blocks.
The method for operating the data access system comprises the steps that the flash memory outputs a plurality of first data stored in a block, the numerical values of the first data are reversed to generate a plurality of first reverse data, the block temporary storage memory stores the first reverse data, when the error checking and correcting circuit judges that the first reverse data are correctable, the error checking and correcting circuit corrects at least one first reverse data stored in the block temporary storage memory, the numerical values of the first reverse data are reversed to generate a plurality of first recovery data, and the application circuit receives the first recovery data to execute corresponding operation.
Drawings
FIG. 1 is a schematic diagram of a data access system according to an embodiment of the invention.
FIG. 2 is a flow diagram of a method of operating the data access system of FIG. 1 in accordance with one embodiment of the present invention.
FIG. 3 is a flow diagram of another method of operating the data access system of FIG. 1 in accordance with one embodiment of the present invention.
Detailed Description
FIG. 1 is a diagram of a data access system 100 according to an embodiment of the invention. The data access system 100 includes a flash memory 110, inverting circuits 120A, 120B, a block scratch pad memory 130, an error checking and correcting circuit 140, and an application circuit 150.
The first inverting circuit 120A may be coupled to the flash memory 110, the block buffer memory 130 may be coupled to the inverting circuit 120A and the inverting circuit 120B, the error checking and correcting circuit 140 may be coupled to the block buffer memory 130, and the application circuit 150 may be coupled to the inverting circuit 120B.
In some embodiments, the application circuit 150 can access data to the flash memory 110 to perform desired operations. For example, the application circuit 150 may be a Double Data Rate (DDR) memory for providing Data required by the processor, but the invention is not limited thereto. In addition, the flash memory 110 may be, for example but not limited to, a NAND type flash memory, and may include a plurality of blocks BL1 through BLN, where N is a positive integer. When the application circuit 150 wants to use the block BL1 of the flash memory 110 to access data, the application circuit 150 needs to first determine whether the block BL1 is a good block through the error checking and correcting circuit 140. If the block BL1 is a bad block, it indicates that the block BL1 may not be able to correctly store data, and therefore the application circuit 150 selects another block for data access.
Generally, the error checking and correcting circuit 140 can only correct a fixed number of bits of data, for example, in some embodiments, the error checking and correcting circuit 140 can correct a bit with a value of 6 written by mistake as 1 to be 0, in which case, when the error bit exceeds 6 bits, the error checking and correcting circuit 140 will report that the error cannot be corrected. However, in some embodiments, since the predetermined bit values of the blocks BL 1-BLN of the flash memory 110 are all the first values, such as 1, before the blocks BL 1-BLN are not written, if the error checking and correcting circuit 140 directly accesses the data of the block BL1, the block BL1 is directly determined as a bad block because there are too many bits with the value of 1. At this time, it is necessary to determine the number of bits with a value of 1 in the block BL1 in a counting manner, so that the system can determine whether the block BL1 is actually a bad block or an empty block that has not been written. In the prior art, since the circuit configuration for counting is complicated, the entire circuit area is unnecessarily increased.
To simplify the operation of the system, the data access system 100 can reverse the data in the block to be read through the first reverse circuit 120A to avoid the misjudgment of the error checking and correcting circuit 140. For example, if the application circuit 150 wants to access the data of the block BL1, the first inverting circuit 120A first inverts the values of the first data D1A in the block BL1 to generate a plurality of first inverted data D1B, and stores the plurality of first inverted data D1B in the block buffer 130.
Then, the error checking and correcting circuit 140 can determine whether the plurality of first reverse data D1B are correctable, and when the error checking and correcting circuit 140 determines that the plurality of first reverse data D1B have errors but are correctable, the error checking and correcting circuit 140 can correct at least one piece of first reverse data D1B stored in the temporary block memory 130.
In this case, if the block BL1 has not been written, the value of the first data D1A will be 1, and the values of the first inverted data D1B will be 0. Therefore, even in the case where the block BL1 is an empty block, the error checking and correcting circuit 140 does not erroneously recognize the block BL1 as a bad block because there are too many bits with a value of 1 in the data.
After the error checking and correcting circuit 140 completes the error detection and/or correction, the second inverting circuit 120B receives the plurality of first inverted data D1B in the block buffer 130 and inverts the values of the plurality of first inverted data D1B to generate a plurality of first restored data D1C. In this way, the application circuit 150 can receive the first recovery data D1C and perform the corresponding operation according to the first recovery data D1C.
Since the data access system 100 can invert the value of the first data D1A through the first inverting circuit 120A to generate the first inverted data D1B, it can be ensured that the error checking and correcting circuit 140 maintains normal operation without misjudging a good block as a bad block. In addition, in fig. 1, the data access system 100 may further include a comparison circuit 160. The comparing circuit 160 is coupled to the second inverting circuit 120B and can determine whether the first restoring data D1C all have the first value, for example, both are 1, so as to determine whether the block BL1 has not been written.
Since the error checking and correcting circuit 140 does not determine the empty (not yet written) good block as a bad block in the data access system 100, the comparing circuit 160 only needs to detect whether the values of the first restored data D1C in the block temporary memory 130 are all 1, so as to assist the system to determine whether the block BL1 is an empty block, without calculating the number of bits with a value of 1 in detail. Therefore, the structure of the comparison circuit 160 is simpler and the required circuit area is smaller than that of the counting circuit required in the prior art.
In some embodiments, before the application circuit 150 writes the data into the flash memory 110, the error checking and correcting circuit 140 generates a corresponding check code according to each data, so as to perform error detection and correction during reading the data.
In FIG. 1, the data access system 100 may also include a third inverting circuit 120C, a fourth inverting circuit 120D, and a multiplexer 170. The third inverting circuit 120C may be coupled to the application circuit 150 and the error checking and correcting circuit 140. The third inversion circuit 120C inverts the plurality of second data D2A transmitted from the application circuit 150 to generate a plurality of second inverted data D2B. The error checking and correcting circuit 140 generates a plurality of error checking codes CC1A according to the second reverse data D2B. In this way, in the subsequent operation, when the application circuit 150 is going to read the second data D2A from the flash memory 110, after the first inverter 120A inverts the second data D2A, the error checking and correcting circuit 140 can determine whether the inverted data can be corrected according to the error checking code CC1A generated by the second inverted data D2B, so as to ensure that the error checking and correcting circuit 140 can operate correctly.
The multiplexer 170 may be coupled to the third inverter circuit 120C, the error checking and correcting circuit 140, and the fourth inverter circuit 120D. The multiplexer 170 may select a data transmission path according to the control signal SIGctrl to transmit the second reverse data D2B or the error check code CC1A from the third inverter circuit 120C to the fourth inverter circuit 120D, respectively. In this way, the fourth inverting circuit 120D inverts the second inverted data D2B to generate the second restored data D2C, and inverts the ECC CC1A generated by the ECC and correction circuit 140 to generate a plurality of inverted ECC CC 1B. Then, the second recovery data D2C and the corresponding reverse error checking code CC1B are stored in a designated block, such as the block BL2, of the flash memory 110.
Since the data access system 100 can invert the data through the inverting circuit, the error checking and correcting circuit 140 can be prevented from erroneously determining the empty block with all data 1 as a bad block, thereby simplifying the flow of accessing the data, simplifying the comparison circuit 160 for determining the empty block, and reducing the circuit area of the data access system 100.
FIG. 2 is a flow diagram of a method 200 of operating the data access system 100 according to one embodiment of the invention. The method 200 comprises steps S210 to S270,
s210: the flash memory 110 outputs a plurality of first data D1A stored in the first block BL 1;
s220: inverting the values of the plurality of pieces of first data D1A to generate a plurality of pieces of first inverted data D1B;
s230: the block temporary memory 130 stores a plurality of first reverse data D1B;
s240: when the error checking and correcting circuit 140 determines that the plurality of first reverse direction data D1B are correctable, the error checking and correcting circuit 140 corrects at least one first reverse direction data D1B stored in the block temporary memory 130;
s250: inverting the values of the plurality of pieces of first inverted data D1B to generate a plurality of pieces of first restored data D1C;
s260: the comparison circuit 160 determines whether the plurality of first recovery data D1C all have the first value 1, so as to determine whether the block BL1 has not been written;
s270: the application circuit 150 receives the plurality of first recovery data D1C to perform corresponding operations.
Through steps S210 to S270, the method 200 can reverse the first data D1A of the block BL1 in the flash memory 110, so that the error checking and correcting circuit 140 can be prevented from erroneously determining the empty block with all 1 data as a bad block, thereby simplifying the data accessing process. In addition, in order to ensure that the error checking and correcting circuit 140 can correctly detect and correct bit errors, the method 200 may further include other steps to ensure that the corresponding error checking code is stored when the data is stored in the flash memory 110. Fig. 3 is another flowchart of a method 200 for operating the data access system 100 according to an embodiment of the invention, and in fig. 3, the method 200 may further include steps S310 to S350.
S310: inverting the plurality of second data D2A from the applying circuit 150 to generate a plurality of second inverted data D2B;
s320: the error checking and correcting circuit 140 generates a plurality of error checking codes CC1A according to the plurality of pieces of second reverse data D2B;
s330: inverting the plurality of error checking codes CC1A to generate a plurality of inverted error checking codes CC 1B;
s340: inverting the plurality of pieces of second inverted data D2B to generate a plurality of pieces of second restored data D2C;
s350: the plurality of pieces of second restored data D2C and the plurality of reverse error checking and correcting check codes CC1B corresponding to the plurality of pieces of second restored data D2C are stored to the second block BL2 in the flash memory 110.
In this way, before the application circuit 150 writes the data into the flash memory 110, the error checking and correcting circuit 140 can generate a corresponding check code according to the second inverse data D2B, so as to perform error detection and correction on the inverse data of the second restored data D2C when reading the second restored data D2C.
In summary, the data access system and the method for operating the data access system according to the embodiments of the present invention can reverse the data read from the flash memory through the reverse circuit, so that the error checking and correcting circuit can be prevented from erroneously determining the unwritten empty block as a bad block, and the flow of accessing the data can be simplified, and the comparison circuit for determining the empty block can be simplified, and the circuit area of the data access system can be reduced.
The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims of the present invention should fall within the protection scope of the present invention.
Description of the reference numerals
100 data access system
110 flash memory
120A, 120B, 120C, 120D inverter
130: block temporary storage memory
Error checking and correcting circuit 140
150 application circuit
160 comparison circuit
170 multiplexer
D1A first data
D1B first reverse data
D1C first recovery data
D2A second data
D2B second reverse data
D2C second reduction data
CC1A error checking and correcting check code
CC1B reverse error checking and correcting check code
SIGctrl control signal
200 method
S210 to S270, S310 to S350
Claims (10)
1. A data access system, comprising:
a flash memory comprising a plurality of blocks;
the first inversion circuit is coupled to the flash memory and used for receiving a plurality of first data stored in a first block of the blocks and inverting the values of the first data to generate a plurality of first inverted data;
the block temporary storage memory is coupled to the first reverse circuit and used for storing the first reverse data;
an error checking and correcting circuit, coupled to the first reverse circuit and the block temporary storage, for determining whether the first reverse data are correctable, and correcting at least one piece of first reverse data stored in the block temporary storage when the first reverse data are correctable;
the second reversing circuit is coupled to the block temporary storage memory and used for receiving the first reversing data in the block temporary storage memory and reversing the numerical values of the first reversing data to generate a plurality of first recovery data; and
the application circuit is used for receiving the first recovery data and executing corresponding operation according to the first recovery data.
2. The data access system of claim 1, wherein the first data stored in the first block has a first value when the first block has not been written.
3. The data accessing system of claim 2, further comprising a comparing circuit coupled to the second inverting circuit for determining whether the first restore data has the first value to determine whether the first block has not been written.
4. The data access system of claim 1, wherein the application circuit is a double data rate memory.
5. The data access system of claim 1, further comprising a third inverting circuit coupled to the application circuit for inverting the plurality of second data transmitted from the application circuit to generate a plurality of second inverted data.
6. The data access system of claim 5, wherein the error checking and correcting circuit is further coupled to the third inverting circuit for generating error checking codes according to the second inverted data.
7. The data access system of claim 6, further comprising a fourth inverting circuit coupled to the flash memory for inverting the error check codes to generate a plurality of inverted error check codes.
8. The data accessing system of claim 7, further comprising a multiplexer coupled to the third inverting circuit, the error checking and correcting circuit and the fourth inverting circuit for transmitting the second inverted data or the error check codes from the third inverting circuit to the fourth inverting circuit according to a control signal.
9. The data accessing system of claim 8, wherein the fourth inverting circuit is further configured to invert the second inverted data to generate a plurality of second restored data, and store the second restored data and the inverted ECC codes corresponding to the second restored data into a second block of the flash memory.
10. The data access system of claim 1, wherein the flash memory is a NAND type flash memory.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010540501.4A CN113808642A (en) | 2020-06-15 | 2020-06-15 | Data access system and method of operating a data access system |
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| CN202010540501.4A CN113808642A (en) | 2020-06-15 | 2020-06-15 | Data access system and method of operating a data access system |
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| US20090210772A1 (en) * | 2008-02-15 | 2009-08-20 | Mitsuhiro Noguchi | Data memory system |
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| TW201101319A (en) * | 2009-06-29 | 2011-01-01 | A Data Technology Co Ltd | An electronic memory device and correction operation method thereof |
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2020
- 2020-06-15 CN CN202010540501.4A patent/CN113808642A/en active Pending
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| JP2005020063A (en) * | 2003-06-23 | 2005-01-20 | Sharp Corp | Error correction apparatus in digital communication terminal |
| US20090210772A1 (en) * | 2008-02-15 | 2009-08-20 | Mitsuhiro Noguchi | Data memory system |
| CN101923896A (en) * | 2009-06-12 | 2010-12-22 | 威刚科技（苏州）有限公司 | Electronic storage device and error correcting method thereof |
| TW201101319A (en) * | 2009-06-29 | 2011-01-01 | A Data Technology Co Ltd | An electronic memory device and correction operation method thereof |
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| 解彦;周昌义;周盛雨;石磊;: "基于单片SRAM的EDAC电路设计", 微计算机信息, no. 07, 15 July 2011 (2011-07-15) * |
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