CN113795916B - 芯片堆叠封装结构及芯片堆叠封装方法 - Google Patents
芯片堆叠封装结构及芯片堆叠封装方法 Download PDFInfo
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- CN113795916B CN113795916B CN202180002085.5A CN202180002085A CN113795916B CN 113795916 B CN113795916 B CN 113795916B CN 202180002085 A CN202180002085 A CN 202180002085A CN 113795916 B CN113795916 B CN 113795916B
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004806 packaging method and process Methods 0.000 title claims description 42
- 239000004020 conductor Substances 0.000 claims abstract description 55
- 230000004888 barrier function Effects 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 11
- 238000005530 etching Methods 0.000 description 18
- 239000011810 insulating material Substances 0.000 description 16
- 239000004642 Polyimide Substances 0.000 description 10
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 10
- 238000000227 grinding Methods 0.000 description 10
- 229920000052 poly(p-xylylene) Polymers 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 10
- 239000000126 substance Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 238000005498 polishing Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000003486 chemical etching Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 229920000620 organic polymer Polymers 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 238000003631 wet chemical etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
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- Wire Bonding (AREA)
Abstract
本申请涉及能够低成本准确性高地实现芯片堆叠封装的芯片堆叠封装结构以及芯片堆叠封装方法,所述封装结构包括:基底芯片层,包括在正面具有引脚的基底芯片,至少一层堆叠芯片层,依次形成于所述基底芯片层,具有芯片间绝缘层以及贴装于所述芯片间绝缘层且在正面具有多个引脚的至少一个堆叠芯片,所述堆叠芯片的正面朝向基底芯片的正面,以及顶层绝缘层,堆叠于距离所述基底芯片层最远的所述堆叠芯片层;在所述芯片间绝缘层的内部形成有使对应的引脚垂直连通的垂直互连孔,所述对应的引脚指规定的需要进行电连接的引脚,在所述垂直互连孔的内部,形成有将对应的引脚电连接的导电材料层,所述堆叠芯片在贴装于所述芯片间绝缘层之后被减薄减小。
Description
技术领域
本申请涉及半导体封装技术领域,具体而言,涉及芯片堆叠封装结构及芯片堆叠封装方法。
背景技术
在半导体工业中,为了提高芯片的运算能力并使芯片小型化,对电子部件,例如晶体管、二极管、电阻器和电容器等的体积和集成度的要求越来越高,目前芯片尺寸已经小到纳米级。另外,人工智能、物联网、5G、自动驾驶、高性能云计算等技术快速发展,需要实现多种芯片短距离地互连。
为了解决上述问题,3D集成(三维集成)技术受到越来越多的关注和重视。在3D集成技术中,将多层芯片在垂直方向上堆叠,通过预先形成的穿透硅材料的TSV硅通孔将多层芯片之间互连,由此实现多层芯片之间的电信号连接。并且,在3D集成技术中,使用TSV硅通孔实现多层芯片之间互连,并且为了进一步小型化和薄型化,还对芯片进行减薄。
由于在各芯片上预先形成TSV硅通孔,在组装中需要将芯片上的TSV硅通孔准确地对准,使得作业复杂。另外,减薄后的芯片易碎,所以超薄芯片的取放成为比较严重的技术问题。因此,对导致成本提升以及垂直方向上芯片的对准困难。
发明内容
本申请提供一种芯片堆叠封装结构及方法,能够低成本准确性高地实现超薄多芯片的封装。
本申请提供一种芯片堆叠封装结构,包括:基底芯片层,包括在正面具有引脚的基底芯片;至少一层堆叠芯片层,依次形成于所述基底芯片层,具有芯片间绝缘层以及贴装于所述芯片间绝缘层且在正面具有多个引脚的至少一个堆叠芯片;所述堆叠芯片的正面朝向基底芯片的正面;以及顶层绝缘层,堆叠于距离所述基底芯片层最远的所述堆叠芯片层;在所述芯片间绝缘层的内部形成有使对应的引脚垂直连通的垂直互连孔,所述对应的引脚指规定的需要进行电连接的引脚,在所述垂直互连孔的内部,形成有将对应的引脚电连接的导电材料层;所述堆叠芯片在贴装于所述芯片间绝缘层之后被减薄减小,暴露出所述堆叠芯片的引脚的部分区域,以实现堆叠芯片通过引脚与其他芯片进行垂直连接。
可选的,在上述的芯片堆叠封装结构中,在所述垂直互连孔内还具有阻挡层,所述阻挡层形成于所述垂直互连孔的内壁与所述导电材料层之间,防止所述导电材料层的形成材料进入所述芯片间绝缘层的内部。
可选的,在上述的芯片堆叠封装结构中,所述基底芯片层是晶圆或由多个所述基底芯片形成的面板。
可选的,在上述的芯片堆叠封装结构中,俯视观察下,所述基底芯片和所述堆叠芯片处于使对应的引脚在堆叠方向上垂直相对的规定的位置。
可选的,在上述的芯片堆叠封装结构中,所述基底芯片的引脚嵌入与所述基底芯片层相邻的堆叠芯片层的芯片间绝缘层中,所述堆叠芯片的所述引脚嵌入该堆叠芯片所处的堆叠芯片层的芯片间绝缘层中。
可选的,在上述的芯片堆叠封装结构中,所述堆叠芯片层包括两层以上。
本申请提供一种芯片堆叠封装方法,包括:堆叠芯片层形成步骤,在基底芯片层上形成至少一层堆叠芯片层,所述堆叠芯片层包括芯片间绝缘层和至少一个堆叠芯片;堆叠芯片减薄减小步骤,每当形成一层堆叠芯片层,对所述一层堆叠芯片层所包括的堆叠芯片进行减薄减小,暴露出所述堆叠芯片的引脚的部分区域;垂直互连孔形成步骤,在所述堆叠芯片减薄减小步骤后,形成使对应的引脚垂直连通的垂直互连孔,所述对应的引脚指规定的需要进行电连接的引脚;导电材料层形成步骤,在所述垂直互连孔内形成使对应的引脚电连接的导电材料层;以及顶层绝缘层形成步骤,在所述堆叠芯片层上形成顶层绝缘层。
可选的,在上述的芯片堆叠封装方法中,在垂直互连孔形成步骤与导电材料层形成步骤之间还包括在所述垂直互连孔内形成阻挡层的阻挡层形成步骤,所述阻挡层通过沉积形成于在所述垂直互连孔的内壁,防止在所述导电材料层形成步骤中导电材料层的形成材料进入所述芯片间绝缘层的内部。
可选的,在上述的芯片堆叠封装方法中,在导电材料层形成步骤与顶层绝缘层形成步骤之间,还包括判断步骤,判断是否全部的所述堆叠芯片层均已形成,在所述判断步骤中判断为所述堆叠芯片层未全部形成的情况下,返回堆叠芯片层形成步骤,在所述判断步骤中判断为所述堆叠芯片层都已形成的情况下,进入所述顶层绝缘层形成步骤。
可选的,在上述的芯片堆叠封装方法中,在所述堆叠芯片减薄减小步骤与所述垂直互连孔形成步骤之间,还包括在所述堆叠芯片层上形成覆盖所述堆叠芯片的临时绝缘层的临时绝缘层形成步骤。
可选的,在上述的芯片堆叠封装方法中,在所述导电材料层形成步骤之后,还包括除去多余的导电材料以及全部或部分所述临时绝缘层的除去步骤。
可选的,在上述的芯片堆叠封装方法中,所述基底芯片的引脚嵌入与所述基底芯片层相邻的堆叠芯片层的芯片间绝缘层,所述堆叠芯片的引脚嵌入该堆叠芯片所处的堆叠芯片层的芯片间绝缘层中。
可选的,在上述的芯片堆叠封装方法中,形成两层以上的所述堆叠芯片层。
附图说明
为了更清楚地说明本申请的技术方案,下面将对其中所需要使用的附图作简单地介绍,应当理解,以下附图仅示出了本申请的某些实现方式,因此不应被看作是对范围的限定,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它相关的附图。
图1为本公开提供的芯片堆叠封装结构的剖视示意图。
图2为本公开提供的芯片堆叠封装方法的流程图。
图3为形成堆叠芯片层的步骤的示意图。
图4为堆叠芯片的减薄减小的步骤的示意图。
图5为形成临时绝缘层的步骤的示意图。
图6是形成垂直互连孔的步骤的示意图。
图7是形成阻挡层的步骤的示意图。
图8是形成导电材料层的步骤的示意图。
图9是除去了多余的导电材料以及临时绝缘层后的层叠构造的示意图。
图10是形成有第二层堆叠芯片层的层叠结构的示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本申请一部分实施例,而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。
因此,以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围,而是仅仅表示本申请的选定实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步定义和解释。
在本申请的描述中,需要说明的是,术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,或者是该发明产品使用时惯常摆放的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。此外,术语“第一”、“第二”、“第三”等仅用于区分描述,而不能理解为指示或暗示相对重要性。
此外,术语“水平”、“竖直”、“悬垂”等术语并不表示要求部件绝对水平或悬垂,而是可以稍微倾斜。如“水平”仅仅是指其方向相对“竖直”而言更加水平,并不是表示该结构一定要完全水平,而是可以稍微倾斜。
术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
首先,参照图1,对本申请提供的一种芯片堆叠封装结构进行说明。芯片堆叠封装结构可以包括一层基底芯片层和一层堆叠芯片层,也可以包括一层基底芯片层和两层堆叠芯片层,还可以包括一层基底芯片层和三层以上堆叠芯片层。在此,以包括一层基底芯片层和两层堆叠芯片层的情况为例进行说明。
图1是包括一层基底芯片层和两层堆叠芯片层的芯片堆叠封装结构10的剖视示意图。该封装结构10主要包括基底芯片层100、堆叠芯片层200、堆叠芯片层300以及位于堆叠芯片层300的上方的顶层绝缘层700。
基底芯片层100可以是由芯片生产厂家制作完成的基底芯片110(以下简称为芯片110),也可以是由芯片生产厂家制作完成的晶圆在经过切割之后形成的芯片110重新组装而成的面板。将芯片的形成有电路或器件的一面称为芯片的正面,即芯片的功能面,将其相反面称为芯片的背面。基底芯片110可以为一个,也可以为多个,在图1中示出具有一个基底芯片的情况。芯片110的引脚从芯片110的正面突出。
堆叠芯片层200包括芯片间绝缘层210(以下,简称为绝缘层210)和堆叠芯片220(以下,简称为芯片220)。
芯片220可以为一个,也可以为两个以上,在此示出具有两个芯片221和芯片222的情况。芯片220的引脚从芯片220的正面突出。芯片220的正面与芯片110的正面相对,两芯片的对应的引脚垂直相对,在此具体为芯片221的引脚221a与芯片110的引脚110a垂直相对,芯片222的引脚222b与芯片110的引脚110b垂直相对,所说的“垂直相对”包括在层叠方向上两引脚完全重叠的情况,也包括在层叠方向上两引脚局部重叠的情况,在此所说的“对应的引脚”指规定的需要进行电连接(即,根据电路设计需要进行电连接)的引脚。在图1中示出在层叠方向上对应的引脚局部重叠的情况。
芯片220的厚度为5-50μm,优选为5-20μm,进一步优选为5-10μm。未贴装前的芯片220的厚度为100μm以上,该厚度确保芯片具有一定的强度,在贴装作业时不会因外力而破裂。在厚度为100μm以上的芯片220贴装于绝缘层210上之后再进行芯片220的减薄减小,减薄指使芯片厚度降低,减小指使芯片的平面尺寸减小以暴露出芯片220的四周引脚的部分区域,以实现芯片220通过引脚与其他芯片进行垂直连接,减薄减小的方式可以是机械磨削、精细研磨、化学机械抛光、湿法化学蚀刻、干法蚀刻中的一种或者几种。
在机械减薄的情况下,可以采用机械磨削、精细研磨、化学机械抛光等中的一种或者几种。作为一个例子,将贴装有芯片220的封装结构通过研磨装置或化学机械抛光设备对芯片220的背面进行磨削、研磨和/或抛光等,从而将芯片220的厚度减薄。
在湿法化学蚀刻减薄减小的情况下,利用蚀刻装置并使用蚀刻液对芯片220的背面和/或侧边进行蚀刻,将芯片220的厚度减薄并且将平面尺寸减小。具体地说,作为蚀刻液主要成分为氢氧化钾,还可以含有其他的加速剂等化合物。将贴装有芯片220的封装结构的整个结构或者仅芯片220的背面浸泡在容置有上述的化学蚀刻液的蚀刻槽中,对芯片220的背面和/或侧边进行蚀刻,例如借助掩模进行蚀刻,由此将芯片220的厚度减薄且将平面尺寸减小。另外,在进行化学蚀刻时,可以对蚀刻液进行搅拌或者加热等,由此使蚀刻的速度变快,缩短蚀刻时间。
绝缘层210由绝缘材料形成,能够列举聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、环氧树脂等有机聚合物中的一种或者几种,也可以是芯片封装中常用的其它聚合物,绝缘层210的厚度不作特别限定。
芯片110的引脚110a~110f和芯片220的引脚221a、221b、222a、222b嵌入绝缘层210,在绝缘层210的内部具有使对应的引脚(在此为引脚110a和引脚221a,以及引脚222b与引脚110b)垂直连通的垂直互连孔410。在垂直互连孔410的内部具有将对应的引脚(引脚110a和引脚221a,以及引脚110b和引脚222b)电连接的导电材料层610,在垂直互连孔410的内壁与导电材料层610之间具有阻挡层510,阻挡层510由能够阻挡导电材料层形成材料因沉积而扩散到绝缘层或基板的形成材料例如硅或者SiO2中的材料形成,能够列举Ta、TaN等。
导电材料层610形成于引脚110a、引脚110b、引脚221a、引脚222b的上表面以及垂直互连孔410内的阻挡层510的内壁面,将对应的引脚电连接。导电材料层610的材料,能够列举铜、铝等导电金属材料,在此不特别限定。
在堆叠芯片层200的上方具有堆叠芯片层300。堆叠芯片层300包括芯片间绝缘层310(以下,简称为绝缘层310)和堆叠芯片320(以下,简称为芯片320)。
芯片320可以为一个,也可以为两个以上,在此示出一个芯片320的情况。芯片320的引脚从芯片320的正面突出。芯片320的正面朝下,与芯片110的正面相对,芯片320的引脚320b与引脚110f垂直相对,芯片320的引脚320a与芯片222的引脚222a垂直相对,在图1中示出在层叠方向上对应的引脚局部重叠的情况。
芯片320的厚度为5-50μm,优选为5-20μm,进一步优选为5-10μm。未贴装前的芯片320的厚度为100μm以上,该厚度确保芯片具有一定的强度,在贴装作业时不会因外力而破裂。在厚度为100μm以上的芯片320贴装于绝缘层310上之后再进行芯片320的减薄减小,减薄指使芯片厚度降低,减小指使芯片的平面尺寸减小以暴露出芯片320的四周引脚的部分区域,以实现芯片320通过引脚与其他芯片进行垂直连接,减薄减小的方式可以是机械磨削、精细研磨、化学机械抛光、湿法化学蚀刻、干法蚀刻中的一种或者几种。
绝缘层310由绝缘材料形成,能够列举聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、环氧树脂等有机聚合物中的一种或者几种,也可以是芯片封装中常用的其它聚合物,绝缘层310的厚度不作特别限定。
芯片320的引脚嵌入绝缘层310,在绝缘层310和/或绝缘层210的内部具有使对应的引脚垂直连通的垂直互连孔420,即使引脚110f与引脚320b垂直连通的垂直互连孔420以及使引脚222a与引脚320a垂直连通的垂直互连孔420。在垂直互连孔420的内部具有将对应的引脚电连接的导电材料层620,在垂直互连孔420的内壁与所述导电材料层620之间具有阻挡层520,阻挡层520由能够阻挡导电材料层的形成材料因沉积而扩散到绝缘层或基板的形成材料例如硅或者SiO2中的材料形成,能够列举Ta、TaN等。
导电材料层620形成于引脚320a、320b、110f、222a的上表面以及垂直互连孔420内的阻挡层520的内壁面,将对应的引脚电连接。导电材料层620的形成材料,能够列举铜、铝等导电金属材料,在此不特别限定。
顶层绝缘层700由绝缘材料形成,能够列举聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、环氧树脂等有机聚合物中的一种或者几种,也可以是芯片封装中常用的其它聚合物,顶层绝缘层700的厚度不作特别限定。
接着参照图2~图10对本申请提供的芯片堆叠封装方法进行说明,该芯片堆叠封装方法可以制造仅包括一层基底芯片层和一层堆叠芯片层的封装结构,也可以制造包括一层基底芯片层和两层堆叠芯片层的封装结构,还可以制造包括一层基底芯片层和三层以上堆叠芯片层的封装结构。
下面,以制造包括一层基底芯片层和两层堆叠芯片层的封装结构为例,具体说明芯片堆叠封装方法,该芯片堆叠封装方法包括下述的步骤S10~S90。
步骤S10,在基底芯片层上形成至少一层堆叠芯片层。
该基底芯片层100可以是晶圆,也可以是由芯片组成的面板,将形成基底芯片层100的芯片称为基底芯片110(以下简称为芯片110),在封装结构中芯片110可以为一个,也可以为两个以上。
如图3所示,以芯片110的正面朝上的方式将基底芯片层100固定。
在本说明书中,芯片的正面指形成有电路或器件的一侧的面,即芯片的功能面,将其相反面称为芯片的背面。芯片110具有形成于正面且从正面突出的多个引脚110a~110f以及未图示的电路和/或器件。
在被固定的基底芯片层100上用绝缘材料形成堆叠芯片层200的芯片间绝缘层210(以下,简称为绝缘层210),绝缘层210的绝缘材料,能够列举聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、环氧树脂等有机聚合物中的一种或者几种,也可以是芯片封装中常用的其它聚合物,并且绝缘材料可以是液体状的,也可以是卷膜式的绝缘材料。绝缘材料的供给方式,可以选择旋涂、喷涂和压膜等方式,在此,绝缘层210的厚度不作特别限定。
接着,使用芯片贴装设备等以使堆叠芯片220(以下简称为芯片220)以正面朝下的方式向绝缘层210表面贴装芯片220。
芯片220可以是一个,也可以是多个,在此,以包括芯片221和芯片222的情况为例进行说明,在统称芯片221和芯片222时,仅称为芯片220。芯片220具有形成于正面的多个引脚以及未图示的电路和/或器件,在图3中示出了芯片221的引脚221a和引脚221b、芯片222的引脚222a和引脚222b。与芯片110同样,芯片220的引脚从芯片220的正面突出。
芯片220的贴装位置是根据电路设计而确定的位置,是使对应的引脚垂直相对的位置,在为使芯片221的引脚221a与芯片110的引脚110a垂直相对以及使芯片222的引脚222b与芯片110的引脚110b垂直相对的位置,在图3中示出在上下方向上对应的引脚局部重叠的情况。
步骤S20,对堆叠芯片进行减薄减小。
通常贴装前的芯片的厚度为100μm以上,该厚度确保芯片具有一定的强度,在贴装作业时不会因外力而破裂。但是,随着对3D集成结构小型化以及薄型化的要求越来越高,要求芯片的厚度更薄,芯片的平面尺寸更小,在此所说的芯片的平面尺寸指俯视观察下芯片的尺寸,在俯视观察芯片为长方形的情况下为长度尺寸和宽度尺寸。
在此,如图4所示,将贴装于绝缘层210上的芯片220的用点化线与实线包围的部分去掉来将芯片220减薄减小。减薄指使芯片厚度降低,减小指使芯片的平面尺寸减小以暴露出芯片220的四周引脚的部分区域,减薄减小的方式可以是机械磨削、精细研磨、化学机械抛光、湿法化学蚀刻、干法蚀刻中的一种或者几种。
在机械减薄的情况下,可以采用机械磨削、精细研磨、化学机械抛光等中的一种或者几种。作为一个例子,将贴装有芯片220的封装结构通过研磨装置或化学机械抛光设备对芯片220的背面进行磨削、研磨和/或抛光等,从而将芯片220的厚度减薄。
在湿法化学蚀刻减薄减小的情况下,利用蚀刻装置并使用蚀刻液对芯片220的背面和/或侧边进行蚀刻,将芯片220的厚度减薄并且将平面尺寸减小。具体地说,作为蚀刻液主要成分为氢氧化钾,还可以含有其他的加速剂等化合物。将贴装有芯片220的封装结构的整个结构或者仅芯片220的背面浸泡在容置有上述的化学蚀刻液的蚀刻槽中,对芯片220的背面和/或侧边进行蚀刻,例如借助掩模进行蚀刻,由此将芯片220的厚度减薄且将平面尺寸减小。另外,在进行化学蚀刻时,可以对蚀刻液进行搅拌或者加热等,由此使蚀刻的速度变快,缩短蚀刻时间。
另外,由于通过步骤S10形成的封装结构的芯片220的引脚嵌入绝缘层210中,因此在进行机械减薄减小时,能够避免芯片220因受到外力而脱落。
通过上述机械减薄减小或者化学减薄减小之后,芯片220的厚度变为5-50μm,优选为5-20μm,进一步优选为5-10μm,芯片的平面尺寸减小到主视观察引脚的一部分从芯片220的侧面突出。
在进行机械减薄减小或者化学蚀刻减薄减小之后,对减薄减小后的封装结构进行清洗、干燥等工序,以除去封装结构上的粉尘、蚀刻液等。在此省略详细说明。
步骤S30,在堆叠芯片层200上形成临时绝缘层310。
如5所示,使用绝缘材料在减薄后的芯片220(具体为芯片221和芯片222)上形成临时绝缘层310,构成该临时绝缘层310的绝缘材料,能够列举聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、环氧树脂等有机聚合物中的一种或者几种,也可以是芯片封装中常用的其它聚合物,并且绝缘材料可以是液体状的,也可以是卷膜式的绝缘材料。绝缘材料的供给方式,可以选择旋涂、喷涂和压膜等方式,在此,临时绝缘层310的厚度不作限定。
通过在减薄减小了的芯片层220上形成临时绝缘层310,对芯片220进行保护,由此能够避免芯片220在下述的垂直互连孔的形成过程中因外力而破损。
步骤S40,形成使对应的引脚连通的垂直互连孔。
如图6所示,利用曝光装置、激光装置或蚀刻装置,通过曝光、激光打孔或干蚀刻,从临时绝缘层310侧在芯片221的引脚221a与芯片110的引脚110a垂直相对的位置形成贯通至芯片110的引脚110a来使芯片221的引脚221a与芯片110的引脚110a垂直连通的垂直互连孔410,即使对应的引脚连通的垂直互连孔。在此,所说的“垂直连通”指,芯片221的引脚221a的上表面以及侧面和芯片110的引脚110a的上表面在垂直互连孔内露出。由于通过曝光、激光打孔或干蚀刻是本领域常用的孔形成方式,在此不具体说明。并且,形成使对应的引脚,即芯片222的引脚222b与芯片110的引脚110b垂直连通的垂直互连孔410。
步骤S50,在垂直互连孔410的内壁形成阻挡层510。
为了避免后述的导电材料层形成材料扩散到绝缘层或基板的形成材料例如硅或者SiO2中,如图7所示,使用本领域公知的沉积装置在垂直互连孔410的内壁通过沉积形成阻挡层510,作为阻挡层的形成材料,能够列举Ta、TaN等。另外,关于阻挡层510的厚度,在此不特别限定,只要是能够阻挡导电材料层形成材料扩散的厚度即可。
另外,在阻挡层的沉积过程中,在引脚110a、引脚110b、引脚221a以及引脚222b的表面也会形成阻挡层,在此为了后述的使导电材料层将引脚110a与引脚221a以及引脚110b与引脚222b导通,需要除去110a、引脚110b、引脚221a以及引脚222b的表面的阻挡层。除去阻挡层的方法能够列举曝光、干蚀刻等。
步骤S60,形成将对应的引脚电连接的导电材料层610。
在该步骤中,如图8所示,使用本领域公知的沉积装置通过沉积在封装结构的露出的表面,例如临时绝缘层310的上表面、垂直互连孔410的未被阻挡层510覆盖的内壁面、引脚110a以及引脚221a在垂直互连孔410露出的表面以及阻挡层510的侧面,形成厚度均匀的导电材料层610。关于形成导电材料层的材料,能够列举铜、铝等导电金属材料,在此不特别限定。关于导电材料层610的厚度不特别限定,只要能够将对应的引脚电导通的厚度即可。导电材料可以将互连孔空间全部充满,也可以不充满互连孔空间,仅实现对应引脚的互连即可,剩余空间可以由接下来的绝缘层材料填满。
步骤S70,除去多余的导电材料以及临时绝缘层310。
导电材料只要将对应的引脚电导通即可,为了避免多余的导电材料引起的短路等不良,需要除去多余的导电材料。另外,关于临时绝缘层310,可以全部除去也可以部分除去,另外,也可以不除去临时绝缘层310而作为后述的绝缘层。在图9中示出将临时绝缘层310全部除去的情况。
步骤S80,判断是否还要形成堆叠芯片层,如果是,则返回步骤S10,如果不需要形成堆叠芯片层,则进入步骤S90。
在此,由于要形成具有两层堆叠芯片层的封装结构,因此在步骤S80中判断为是,则返回步骤10。
在图10中示出形成有第二层堆叠芯片层300的封装结构,省略第二层堆叠芯片层300的各步骤的图示,一并参照图3~图10进行说明。
在步骤S10中,以通过步骤S70形成的封装结构,在远离基底芯片层100的一侧利用绝缘材料形成堆叠芯片层300的芯片间绝缘层310(以下,简称为绝缘层310),关于绝缘层310的绝缘材料以及形成方法,除了绝缘层310的绝缘材料进入导电材料层610的内侧以外,与绝缘层210相同,在此省略具体说明。
接着,使用芯片贴装设备使堆叠芯片320(以下简称为芯片320)的正面朝下的方式向绝缘层310贴装芯片320。芯片320可以是一个,也可以是多个,在此,以一个芯片320的情况为例进行说明。芯片320具有形成于正面的多个引脚以及未图示的电路和/或器件,,芯片320的形成有电路和/或器件的区域处于被多个引脚包围形成的区域内,在图10中示出了芯片320的引脚320a和引脚320b。与芯片110同样,芯片320的引脚从芯片320的正面突出。
芯片320的贴装位置是根据电路设计而确定的位置,使引脚320b与引脚110f垂直相对且引脚320a与引脚222a垂直相对的位置。
关于芯片320的贴装方法,与芯片220相同,在此省略详细说明。
接着,在步骤S20,将芯片320减薄减小。与芯片220减薄减小同样,通过机械减薄减小或者化学减薄减小之后,芯片320的厚度变为5-50μm,优选为5-20μm,进一步优选为5-10μm,减小指使芯片320的平面尺寸减小以暴露出芯片320的四周引脚的部分区域。
然后,在步骤S30,在第二层堆叠芯片层300上形成临时绝缘层,该临时绝缘层的形成材料以及形成方法与临时绝缘层310相同,在此省略说明。
在步骤S40中,分别形成使引脚320b与引脚110f连通的垂直互连孔以及使引脚320a与引脚222a连通的垂直互连孔。该垂直互连孔的形成步骤与垂直互连孔410相同,在此省略说明。
然后,在步骤S50中,在垂直互连孔的内壁形成阻挡层520,该步骤与形成阻挡层510的步骤相同,在此省略说明。接着,在步骤S60,形成将对应的引脚电连接的导电材料层620,该步骤与导电材料层610相同,在此省略说明。
接着,在步骤S70中,除去多余的导电材料以及临时绝缘层,由此形成图10所示的封装结构。
接着,在步骤S80,判断是否要要形成堆叠芯片层。在此判断该为不需要再形成堆叠芯片层,则进入步骤S90。
步骤S90,在堆叠封装结构上形成作为顶层绝缘层的绝缘层700。
顶层绝缘层的绝缘层700的形成材料以及形成方法与堆叠芯片层的绝缘层大致相同,由此获得图1所示的芯片堆叠封装结构。
通过本实施方式的芯片堆叠封装方法获得的芯片堆叠封装结构,可以通过进一步形成连接层来实现与其他电子元件的连接。
本申请提供一种芯片堆叠封装结构,包括:基底芯片层,包括在正面具有引脚的基底芯片,至少一层堆叠芯片层,依次形成于所述基底芯片层,具有芯片间绝缘层以及贴装于所述芯片间绝缘层且在正面具有多个引脚的至少一个堆叠芯片,所述堆叠芯片的正面朝向基底芯片的正面,以及顶层绝缘层,堆叠于距离所述基底芯片层最远的所述堆叠芯片层;在所述芯片间绝缘层的内部形成有使对应的引脚垂直连通的垂直互连孔,所述对应的引脚指规定的需要进行电连接的引脚,在所述垂直互连孔的内部,形成有将对应的引脚电连接的导电材料层,所述堆叠芯片在贴装于所述芯片间绝缘层之后被减薄减小,暴露出所述堆叠芯片的引脚的部分区域,以实现所述堆叠芯片通过引脚与其他芯片进行垂直连接。由于堆叠芯片在贴装于芯片间绝缘层之后被减薄减小,所以在芯片贴装作业时为厚度相对厚而具有一定强度的芯片,能够避免贴装作业时芯片因来自机械手等的外力而破裂,从而能够提供成品率且成本低的超薄芯片堆叠封装结构。
本申请提供一种芯片堆叠封装方法,包括:堆叠芯片层形成步骤,在基底芯片层上形成至少一层堆叠芯片层,所述堆叠芯片层包括芯片间绝缘层和至少一个堆叠芯片;堆叠芯片减薄减小步骤,每当形成一层堆叠芯片层,对所述一层堆叠芯片层所包括的堆叠芯片进行减薄减小,暴露出所述堆叠芯片的引脚的部分区域;垂直互连孔形成步骤,在所述堆叠芯片减薄减小步骤后,形成使对应的引脚垂直连通的垂直互连孔,所述对应的引脚指规定的需要进行电连接的引脚;导电材料层形成步骤,在所述垂直互连孔内形成使对应的引脚电连接的导电材料层;以及顶层绝缘层形成步骤,在所述堆叠芯片层上形成顶层绝缘层。由于每当形成一层堆叠芯片层,对该一层堆叠芯片层所包括的堆叠芯片进行减薄减小,所以在芯片贴装作业时为厚度相对厚而具有一定强度的芯片,能够避免贴装作业时芯片因来自机械手等的外力而破裂,从而能够实现成品率且成本低的超薄芯片堆叠封装方法。
以上所述,仅为本申请的各种实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应所述以权利要求的保护范围为准。
工业实用性
本申请提供的芯片堆叠封装结构及方法应用于三维集成封装技术领域,能够低成本准确性高地实现超薄多芯片的堆叠封装。
Claims (13)
1.一种芯片堆叠封装结构,包括:
基底芯片层,包括在正面具有引脚的基底芯片,
至少一层堆叠芯片层,依次形成于所述基底芯片层,具有芯片间绝缘层以及贴装于所述芯片间绝缘层且在正面具有多个引脚的至少一个堆叠芯片,所述堆叠芯片的正面朝向基底芯片的正面,以及
顶层绝缘层,堆叠于距离所述基底芯片层最远的所述堆叠芯片层;
在所述芯片间绝缘层的内部形成有使对应的引脚垂直连通的垂直互连孔,所述对应的引脚指规定的需要进行电连接的引脚,
在所述垂直互连孔的内部,形成有将对应的引脚电连接的导电材料层,
所述堆叠芯片在贴装于所述芯片间绝缘层之后被减薄减小,暴露出所述堆叠芯片的引脚的部分区域,以实现所述堆叠芯片通过引脚与其他芯片进行垂直连接,
所述基底芯片的引脚嵌入与所述基底芯片层相邻的堆叠芯片层的芯片间绝缘层中,所述堆叠芯片的所述引脚嵌入该堆叠芯片所处的堆叠芯片层的芯片间绝缘层中。
2.根据权利要求1所述的芯片堆叠封装结构,其中,
在所述垂直互连孔内还具有阻挡层,所述阻挡层形成于所述垂直互连孔的内壁与所述导电材料层之间,防止所述导电材料层的形成材料进入所述芯片间绝缘层的内部。
3.根据权利要求1所述的芯片堆叠封装结构,其中,
所述基底芯片层是晶圆或由多个所述基底芯片形成的面板。
4.根据权利要求2所述的芯片堆叠封装结构,其中,
所述基底芯片层是晶圆或由多个所述基底芯片形成的面板。
5.根据权利要求1至4中任一项所述的芯片堆叠封装结构,其中,
俯视观察下,所述基底芯片和所述堆叠芯片处于使对应的引脚在堆叠方向上垂直相对的规定的位置。
6.根据权利要求1至4中任一项所述的芯片堆叠封装结构,其中,
所述堆叠芯片层包括两层以上。
7.一种芯片堆叠封装方法,包括:
堆叠芯片层形成步骤,在基底芯片层上形成至少一层堆叠芯片层,所述堆叠芯片层包括芯片间绝缘层和至少一个堆叠芯片,
堆叠芯片减薄减小步骤,每当形成一层堆叠芯片层,对所述一层堆叠芯片层所包括的堆叠芯片进行减薄减小,暴露出所述堆叠芯片的引脚的部分区域,
垂直互连孔形成步骤,在所述堆叠芯片减薄减小步骤后,形成使对应的引脚垂直连通的垂直互连孔,所述对应的引脚指规定的需要进行电连接的引脚,
导电材料层形成步骤,在所述垂直互连孔内形成使对应的引脚电连接的导电材料层,以及
顶层绝缘层形成步骤,在所述堆叠芯片层上形成顶层绝缘层;
所述基底芯片的引脚嵌入与所述基底芯片层相邻的堆叠芯片层的芯片间绝缘层,所述堆叠芯片的引脚嵌入该堆叠芯片所处的堆叠芯片层的芯片间绝缘层中。
8.根据权利要求7所述的芯片堆叠封装方法,其中,
在垂直互连孔形成步骤与导电材料层形成步骤之间还包括在所述垂直互连孔内形成阻挡层的阻挡层形成步骤,
所述阻挡层通过沉积形成于在所述垂直互连孔的内壁,防止在所述导电材料层形成步骤中导电材料层的形成材料进入所述芯片间绝缘层的内部。
9.根据权利要求7所述的芯片堆叠封装方法,其中,
在导电材料层形成步骤与顶层绝缘层形成步骤之间,还包括判断步骤,判断是否全部的所述堆叠芯片层均已形成,
在所述判断步骤中判断为所述堆叠芯片层未全部形成的情况下,返回堆叠芯片层形成步骤,在所述判断步骤中判断为所述堆叠芯片层都已形成的情况下,进入所述顶层绝缘层形成步骤。
10.根据权利要求8所述的芯片堆叠封装方法,其中,
在导电材料层形成步骤与顶层绝缘层形成步骤之间,还包括判断步骤,判断是否全部的所述堆叠芯片层均已形成,
在所述判断步骤中判断为所述堆叠芯片层未全部形成的情况下,返回堆叠芯片层形成步骤,在所述判断步骤中判断为所述堆叠芯片层都已形成的情况下,进入所述顶层绝缘层形成步骤。
11.根据权利要求7至10中任一项所述的芯片堆叠封装方法,其中,
在所述堆叠芯片减薄减小步骤与所述垂直互连孔形成步骤之间,还包括在所述堆叠芯片层上形成覆盖所述堆叠芯片的临时绝缘层的临时绝缘层形成步骤。
12.根据权利要求11所述的芯片堆叠封装方法,其中,
在所述导电材料层形成步骤之后,还包括除去多余的导电材料以及全部或部分所述临时绝缘层的除去步骤。
13.根据权利要求7至10中任一项所述的芯片堆叠封装方法,其中,
形成两层以上的所述堆叠芯片层。
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