CN113795048B

CN113795048B - Power processing method, communication device, chip and module equipment thereof

Info

Publication number: CN113795048B
Application number: CN202111260458.7A
Authority: CN
Inventors: 杨扬; 朱志辉; 谭舒
Original assignee: Unisoc Chongqing Technology Co Ltd
Current assignee: Unisoc Chongqing Technology Co Ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2023-12-26
Anticipated expiration: 2041-10-27
Also published as: CN113795048A

Abstract

The application discloses a power processing method, a communication device, a chip and module equipment thereof. The method comprises the following steps: receiving a first primary synchronization signal PSS of a cell to be accessed; performing correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence; determining a first shift factor according to the first correlation power sequence; and carrying out shift processing on the first related power sequence according to the first shift factor to obtain a first node power sequence. By implementing the method provided by the embodiment of the application, the shift factor can be calculated in real time according to the received PSS, so that the accuracy of the power sequence of the first node is improved, the position of the PSS of the cell to be accessed is determined, and further the downlink synchronization with the cell to be accessed is completed.

Description

Power processing method, communication device, chip and module equipment thereof

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a power processing method, a communications device, a chip, and a module device thereof.

Background

In the cell search process, the terminal device may receive a primary synchronization signal (primary synchronization signal, PSS) from a cell to be accessed, and determine a location of the PSS to obtain a physical layer identifier of the cell to be accessed and complete downlink synchronization. The terminal device may perform correlation operation on the PSS received from the cell to be accessed and the local PSS, so as to determine the position of the PSS of the cell to be accessed through the position of the node power value exceeding the threshold value. Because the bit width of the correlation power sequence obtained after the correlation operation is wider, a shifting factor is generally configured by software to shift the correlation power sequence, and the shifted node power value is stored. However, the shifting factor configured by the software is difficult to consider different scenes, and the shifted node power value may be inaccurate, so that the position of the cell PSS to be accessed cannot be determined through the node power value exceeding the threshold value in the node power values, and further the downlink synchronization with the cell to be accessed cannot be completed.

Therefore, how to improve the accuracy of the node power value in the shift storage process becomes a hot spot problem in the current research.

Disclosure of Invention

The application discloses a power processing method, a communication device, a chip and module equipment thereof, which can calculate a shift factor in real time according to a received PSS, thereby improving the accuracy of a first node power sequence, determining the position of a cell PSS to be accessed, and further completing downlink synchronization with the cell to be accessed.

In a first aspect, the present application provides a power processing method, the method comprising: receiving a first primary synchronization signal PSS of a cell to be accessed; performing correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence; determining a first shift factor according to the first correlation power sequence; and carrying out shift processing on the first related power sequence according to the first shift factor to obtain a first node power sequence.

In one implementation, a maximum power value in the first related power sequence is obtained; and determining a first shifting factor based on the maximum power value.

In one implementation, a second shifting factor is determined according to the first node power sequence; updating the first shift factor according to the first shift factor and the second shift factor to obtain an updated first shift factor; and receiving a second PSS of the cell to be accessed; performing correlation operation on the second PSS and a local PSS to obtain a second correlation power sequence; and performing shift processing on the third related power sequence according to the updated first shift factor to obtain a second node power sequence; wherein the third correlation power sequence is the sum of the first correlation power sequence and the second correlation power sequence.

In one implementation, the second shifting factor is updated according to the second node power sequence.

In one implementation manner, the first related power sequence is shifted according to the second shifting factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; carrying out arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; and updating the second shifting factor according to the fourth node power sequence.

In one implementation manner, a maximum power value in the first node power sequence is obtained; and determining the second shifting factor according to the maximum power value.

In one implementation, the updated first shift factor is a sum of the second shift factor and the first shift factor.

In a second aspect, the present application provides a communication device for implementing the means of the method of the first aspect and any one of its possible implementations.

In a third aspect, the present application provides a communication device comprising a processor for performing the method of the first aspect and any one of its possible implementations.

In a fourth aspect, the present application provides a communications device comprising a processor and a memory for storing computer-executable instructions; the processor is configured to invoke the program code from the memory to perform the method of the first aspect and any possible implementation thereof.

In a fifth aspect, the present application provides a chip, where the chip is configured to receive a first primary synchronization signal PSS of a cell to be accessed; performing correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence; determining a first shift factor according to the first correlation power sequence; and carrying out shift processing on the first related power sequence according to the first shift factor to obtain a first node power sequence.

In a sixth aspect, the present application provides a module apparatus, the module apparatus including a communication module, a power module, a storage module, and a chip module, wherein: the power supply module is used for providing electric energy for the module equipment; the storage module is used for storing data and instructions; the communication module is used for carrying out internal communication of the module equipment or carrying out communication between the module equipment and external equipment; the chip module is used for: receiving a first primary synchronization signal PSS of a cell to be accessed; performing correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence; determining a first shift factor according to the first correlation power sequence; and carrying out shift processing on the first related power sequence according to the first shift factor to obtain a first node power sequence.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a communication system according to an embodiment of the present application;

fig. 2 is a flowchart of a power processing method according to an embodiment of the present application;

fig. 2A is a flowchart of a PSS sample counter according to an embodiment of the present disclosure;

FIG. 3 is a flowchart of another power processing method according to an embodiment of the present disclosure;

FIG. 3A is a schematic diagram of a cache according to an embodiment of the present disclosure;

FIG. 3B is a schematic diagram of a storage format of a shift factor according to an embodiment of the present disclosure;

FIG. 3C is a read-write timing diagram of the cache according to the embodiment of the present application;

FIG. 4 is a flowchart of another power processing method according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of another communication device according to an embodiment of the present application;

Fig. 7 is a schematic structural diagram of a module device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic diagram of a communication system according to an embodiment of the present application. As shown in fig. 1, the communication system may include a terminal device 101 and a network device 102. In this embodiment, the terminal device 101 is within the coverage area of the network device 102, and the cell served by the network device 102 includes the cell to be accessed mentioned in this embodiment of the present application, and the oval area in fig. 1 may represent the coverage area of the cell to be accessed. It should be noted that the numbers of the terminal devices 101 and the network devices 102 shown in fig. 1 are only for example, and do not limit the present application.

The terminal device 101 may receive the PSS from the cell to be accessed, and perform correlation operation on the PSS and the local PSS to obtain the first correlation power sequence. Under the condition that the PSS of the cell to be accessed is the first PSS received by the terminal equipment, namely the first PSS is received, the terminal equipment can obtain a first related power sequence by carrying out related operation on the first PSS and the local PSS, and a first shifting factor is determined; and performing shift processing on the first related power sequence according to the first shift factor, thereby obtaining a first node power sequence, and outputting a node power value exceeding a threshold value in the first node power sequence.

In the case that the PSS of the cell to be accessed is a non-first PSS received by the terminal device, that is, a second PSS is received, the terminal device may perform a correlation operation on the second PSS and the local PSS to obtain a second correlation power sequence; the third related power sequence is shifted by acquiring the updated first shifting factor so as to obtain a second node power sequence; and performing shift processing on the first related power sequence by acquiring a second shift factor to obtain a third node power sequence; and performing arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence, thereby outputting the node power value exceeding the threshold value in the fourth node power sequence. The second shift factor may be determined by a first node power sequence, and the third correlation power sequence is a sum of the first correlation power sequence and the second correlation power sequence.

The node power value exceeding the threshold value in the node power sequence (such as the first node power sequence) after the first PSS sample shift processing and the node power value exceeding the threshold value in the node power sequence (such as the fourth node power sequence) after the non-first PSS sample shift processing can be used as candidate positions of the PSS of the cell to be accessed, so that the candidate positions can be further screened, and the positions of the cell to be accessed can be further determined.

The terminal device 101 is an entity on the user side for receiving or transmitting signals, such as a mobile phone. The terminal device may also be referred to as a terminal (terminal), a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), etc. The terminal device may be a mobile phone, a wearable device, a tablet (Pad), a computer with wireless transceiving function, a Virtual Reality (VR) terminal device, an augmented reality (augmented reality, AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned-driving (self-driving), a wireless terminal in teleoperation (remote medical surgery), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation security (transportation safety), a wireless terminal in smart city (smart city), a wireless terminal in smart home (smart home), a terminal device for supporting enhanced Machine type communication (eMTC) and/or long term evolution (long term evolution, LTE) supporting general mobile communication technology, etc. The embodiment of the application does not limit the specific technology and the specific equipment form adopted by the terminal equipment.

Network device 102 is an entity on the network side for transmitting or receiving signals. For example, the network device may be an evolved NodeB (eNB), a transmission point (transmission reception point, TRP), a next generation NodeB (gNB) in an NR system, a base station in other future mobile communication systems, or an access node in a wireless fidelity (wireless fidelity, wiFi) system, etc. The embodiment of the application does not limit the specific technology and the specific device form adopted by the network device.

It should be noted that the technical solution of the embodiment of the present application may be applied to various communication systems. For example: long term evolution (long term evolution, LTE) system, fifth generation (5th generation,5G) mobile communication system, 5G New Radio (NR) system. Optionally, the method of the embodiments of the present application is also applicable to various future communication systems, such as a 6G system or other communication networks.

Referring to fig. 2, fig. 2 is a flowchart of a power processing method according to an embodiment of the present application. The power processing method may be implemented by the above-mentioned terminal device, or may be implemented by a chip in the above-mentioned terminal device. As shown in fig. 2, the power processing method includes, but is not limited to, the following steps S201 to S203.

In step S201, the terminal device receives a first primary synchronization signal PSS of a cell to be accessed.

In the cell search process, in order to obtain the physical identifier of the cell to be accessed and complete downlink synchronization with the cell to be accessed, the terminal equipment may determine the position of the PSS of the cell to be accessed by receiving the PSS of the cell to be accessed and performing a series of operations on the PSS and the local PSS, thereby obtaining the physical identifier of the cell to be accessed and completing downlink synchronization with the cell to be accessed.

The first PSS may be any signal segment in the PSS of the cell to be accessed. Alternatively, the terminal device may receive the PSS segment of the cell to be accessed through a time window with a fixed length (e.g. 5 ms), so as to obtain a first PSS sample (i.e. the first PSS), a second PSS sample (i.e. the second PSS mentioned below), and a third PSS sample. Optionally, the terminal device may receive multiple PSS samples to obtain more PSS data of the cell to be accessed, so that subsequent calculation and screening can be more accurate. For example: if the PSS sample received by the terminal equipment contains peak data of the PSS of the cell to be accessed, the probability of outputting a power node value exceeding a threshold value in the shift processing process of the PSS sample is high; if the PSS sample received by the terminal equipment does not contain the peak data of the PSS of the cell to be accessed, the probability of outputting the node power value exceeding the threshold value in the shift processing process of the PSS sample is small. And through sectional receiving of the PSS of the cell to be accessed, each section of PSS sample and the local PSS can be respectively subjected to related operation, so that the node power value exceeding the threshold value after the operation is reserved, and the node power value smaller than the threshold value is eliminated, thereby being beneficial to determining the power value of the PSS position of the cell to be accessed from the positions of the node power values.

It should be noted that, after receiving the PSS of the cell to be accessed, the terminal device may perform preprocessing on the PSS. Wherein, the preprocessing of the PSS may include: direct Current (DC) cancellation and delay automatic gain control (delayed automatic gain control, DAGC) adjustment to cancel noise and interference in PSS, etc., thereby obtaining clearer PSS; the preprocessing of PSS may further include: the PSS is subjected to inverse fast fourier transform (inverse fast Fourier transform, IFFT) conversion, thereby obtaining an IFFT frequency domain sequence of the PSS.

Alternatively, the terminal device may pre-configure the frequency offset branch for the first PSS. The number of frequency offset branches and the offset thereof can be preconfigured. For example, the terminal device may configure 1 or 3 frequency offset branches for the first PSS; the terminal device may also configure each frequency offset branch to be offset to the left by 5 bits, which is not limited in this application. It should be noted that, the terminal device configures how many frequency offset branches for the first PSS, i.e. how many paths of data (i.e. frequency domain sequences) can be obtained. For example, if the terminal device is configured with 3 frequency offset branches, 3 paths of data can be obtained.

Alternatively, as shown in fig. 2A, the terminal device may determine whether the received PSS is the first PSS sample through the PSS sample counter. The value of the PSS sample counter may be incremented by 1 each time the terminal device receives a PSS sample. Optionally, the terminal device may initialize the value of the PSS sample counter at power-on, and set a number threshold value for the PSS sample counter. For example, when a PSS is received for the first time after the terminal device is started, the PSS may be determined as a first PSS sample; when the terminal device receives the PSS for the second time after the power-on, the PSS may be determined as a second PSS sample, where the second PSS sample belongs to a non-first PSS sample. It should be noted that, when the number of PSS samples received by the terminal device reaches the threshold value of the number of PSS sample counters, the value of the PSS sample counter may be cleared, i.e. the value of the PSS sample counter is initialized again. It can be understood that after the value of the PSS sample counter is cleared, the next PSS sample received by the terminal device may be the first PSS sample.

It should be noted that, since the processing manners of the first PSS sample and the non-first PSS sample are different, the processing manner of the first PSS sample (see the relevant steps in the embodiments corresponding to fig. 2 and 3) and the processing manner of the non-first PSS sample (see the relevant steps in the embodiments corresponding to fig. 4) will be described in detail in the embodiments of the present application.

In step S202, the terminal device performs a correlation operation on the first PSS and the local PSS, to obtain a first correlation power sequence.

The local PSS may be the PSS of the current serving cell of the terminal device or the PSS of the serving cell accessed in history. Optionally, the terminal device may obtain the local PSS by acquiring the PSS stored in the storage device. Alternatively, the local PSS may be a frequency domain sequence, so as to perform a correlation operation between the frequency domain sequence of the local PSS and the frequency domain sequence of the first PSS. It should be noted that, before correlating the local PSS with the PSS received from the cell to be accessed, the local PSS may be preprocessed. For example: a local PSS sequence is generated and zero-padded to reach a required length for correlation with the received PSS in case of insufficient length of the local PSS sequence. For example, when the local PSS is less than 1024 bits in length, the local PSS may be zero-padded up to 1024 bits.

Optionally, network identifier two (network identity2, NID) ⁽²⁾ ) Can be used to indicate the local PSS, the NID ⁽²⁾ The value of (2) may be 0, 1 or 2, i.e. there may be a maximum of 3 local PSS. Wherein the NID is ⁽²⁾ An identifier in the physical cell identity (physical cell identifier, PCI) may be identified. It should be noted that PCI may be used to identify cells at the physical layer. The terminal device may pass through network identifier one (network identity1, NID) ⁽¹⁾ ) And NID ⁽²⁾ PCI is determined. In one implementation, pci=3nid ⁽¹⁾ +NID ⁽²⁾ See for details the description in standard 38.211. Wherein NID1 is obtainable from SSS, NID ⁽²⁾ Can be obtained from PSS. Wherein the network identifier may also be referred to as a network identification code. PCI can be expressed asNID ⁽¹⁾ Can be expressed as +.>NID ⁽²⁾ Can be expressed as +.>

In an exemplary case that there are multiple local PSS, for example, there are 3 local PSS, the terminal device may perform correlation operation on the received first PSS and the 3 local PSS respectively, so as to determine one or more local PSS that is most similar to the received first PSS from the 3 local PSS, that is, there are one or more local PSS corresponding to the node power value exceeding the threshold value after performing the shift processing, so that physical cell identifiers corresponding to the one or more local PSS are obtained through correlation data of the local PSS, so as to determine a possible location of the received first PSS.

In step S203, the terminal device determines a first shifting factor according to the first correlation power sequence.

Since the correlation operation may be a sliding correlation, that is, the terminal device may segment the local PSS frequency domain sequence and perform a correlation operation with the frequency domain sequence of the first PSS. For example, the terminal device may slide the local PSS frequency domain sequence sequentially according to a length of 5ms to perform a correlation operation with the first PSS frequency domain sequence. For example: if the total length of the frequency domain sequence of the local PSS is 15ms, the local PSS may be divided into 3 segments of frequency domain sequences with a length of 5ms, and the 3 segments of frequency domain sequences are respectively correlated with the frequency domain sequence of the first PSS once.

Optionally, in the case that there are 3 local PSS, the first PSS may be respectively slide-related to the first local PSS to obtain a related power sequence 1, slide-related to the second local PSS to obtain a related power sequence 2, and slide-related to the third local PSS to obtain a related power sequence 3; the first correlation power sequence may be a sequence set of a correlation power sequence 1, a correlation power sequence 2, and a correlation power sequence 3. That is, the first correlation power sequence may include three sets of correlation power sequences, and each set of correlation power sequences may include a plurality of power values. And then, respectively carrying out shift processing on each group of related power sequences in the first related power sequences, and further determining one or more groups of related power sequences which are most related to the first PSS, namely one or more local PSSs.

It should be noted that, since the embodiment corresponding to fig. 2 may be a processing manner of the first PSS sample, that is, after the first PSS may initialize the sample counter for the terminal device, the first received PSS sample is received; thus, the terminal device may determine a first shifting factor for the first PSS sample processing according to the first correlation power sequence.

In one implementation, the first related power sequence may include a plurality of power values. The terminal equipment can acquire the maximum power value in the first related power sequence; and determining a first shifting factor based on the maximum power value. Wherein, the calculation formula is as follows:

wherein,for the first shifting factor, normfactor1 is a default value configured by software, sign bit (a) represents a sign extension bit for solving a, and a is a signed number; a in the embodiment of the present application may be a maximum power value in the first related power sequence. The sign extension bit for a is understood to be a value of a to be calculated and extended to a standard bit width. For example: if the value of a is 10 bits, but the standard bit width is 16 bits, the sign extension bit of the value of a needs to be set to 6 bits to satisfy the standard bit width.

In step S204, the terminal device performs shift processing on the first related power sequence according to the first shift factor, to obtain a first node power sequence.

The shifting process is performed on the first correlation power sequence according to the first shifting factor, which may be understood as that each group of correlation power sequences (such as the correlation power sequence 1, the correlation power sequence 2, and the correlation power sequence 3) in the first correlation power sequence is shifted and truncated according to the first shifting factor. For example: and shifting a first group of related power sequences (such as related power sequence 1) in the first related power sequences leftwards or rightwards according to a first shifting factor, and then intercepting the power value of the shifted node position to serve as the node power value corresponding to the first group of related power sequences. It is understood that each set of related power sequences may correspond to a node power value. That is, if there are three sets of related power sequences, i.e., three node power values may exist in the first node power sequence.

It should be noted that, the terminal device determines the first shifting factor through the maximum power value in the first related power sequence, so that the maximum power value after shifting is ensured to be within the processable range of the terminal device, thereby avoiding that the shifting factor determined through other power values in the first related power sequence can cause the power value after shifting to be not within the processable range of the terminal device.

And performing correlation operation on the first PSS received from the cell to be accessed and the local PSS to obtain a first correlation power sequence, determining a first shift factor according to the first correlation power sequence, and performing shift processing on the first correlation power sequence according to the first shift factor to obtain a first node power sequence, thereby outputting a node power value exceeding a threshold value in the first node power sequence, and further being beneficial to determining the position of the cell PSS to be accessed from the positions corresponding to the node power value.

Referring to fig. 3, fig. 3 is a flowchart of another power processing method according to an embodiment of the present application. The power processing method may be implemented by the above-mentioned terminal device, or may be implemented by a chip in the above-mentioned terminal device. As shown in fig. 3, the power processing method includes, but is not limited to, the following steps S301 to S309.

In step S301, the terminal device may receive a first PSS of the cell to be accessed, and perform a correlation operation on the first PSS and a local PSS to obtain a first correlation sequence.

Alternatively, the first correlation sequence may be formulatedA representation; wherein, f0 can be used for representing the value of the frequency offset branch, the value range of f0 can be 0-4, namely, at most 5 frequency offset branches can exist; i may be used to indicate the index of the PSS segment, i.e. which segment in the PSS sample the received first PSS is, i being a positive integer; p may be used to represent NID ⁽²⁾ The value of p can range from 0 to 2, i.e., up to 3 NIDs can be present ⁽²⁾ The method comprises the steps of carrying out a first treatment on the surface of the k1 may be used to represent the value of the data index in the received PSS sample, where k1 is a positive integer.

It should be noted thatThe first correlation sequence may be used to represent the received data. Exemplary, assuming f0 is 2, i is 3, p is 2, and k1 is 3May be used to represent the received data as the third data in the third segment of the PSS samples, with the frequency offset branching of 2, nid ⁽²⁾ 2. It is understood that the first correlation sequence may be different values obtained according to the difference of the k1 values, and then be combined into the first correlation sequence. For example, in case k1 is 3, the above first related sequence may be composed of +.>Composition; wherein (1)>Can be the first data in the received sample data,/or->Can be the second data of the received sample data,/or->And may be the third of the received sample data.

In step S302, the terminal device may power the first correlation sequence to obtain a first correlation power sequence, and obtain a maximum power value in the first correlation power sequence. Specifically, the calculation formula of the first correlation power sequence and the calculation formula of the maximum power value in the first correlation power sequence are as follows:

Wherein,may be a first correlated power sequence, +.>Is the first correlation sequence; maxcorrpwrmay be the maximum power value in the first correlated power sequence. Specifically, power is calculated for the first correlation sequence, which may be understood as calculating power for each data in the first correlation sequence. For example, in the case where k1 is 3, then +.>Power is calculated by the value of (2). It can be understood that the first correlation power sequence may be different correlation power values obtained according to the difference of the k1 values, and then be combined into the first correlation power sequence.

It should be noted that, for the relevant content of step S301 and step S302, refer to the details of step S201 and step S202 in the embodiment of fig. 2, and the detailed description is omitted herein.

In step S303, the terminal device may determine the first shifting factor according to the maximum power value. Wherein, according to the formula in the corresponding embodiment of fig. 2, the value of a is brought into the maximum power value, and the following is obtained:

wherein,for the first shifting factor, normfactor1 is a default value configured by software, and signbit (MaxCotrPwr) may represent the sign extension bit for the maximum power value in the first related power sequence. It should be noted that, the relevant content of step S303 can be referred to the detailed content of step S203 in the embodiment of fig. 2, which is herein Please refer to this embodiment.

In step S304, the terminal device may perform shift processing on the first related power sequence according to the first shift factor, to obtain a first node power sequence. Specifically, the calculation formula of the first node power sequence is as follows:

wherein,may be a first node power sequence, +.>May be the first correlation power sequence described above. It should be noted that, in the process of shifting the first correlation power sequence, if the first shift factor is a positive value, the value of the first correlation power sequence is shifted to the left, i.e. amplified; if the first shift factor is negative, the value of the first correlation power sequence is reduced. Exemplary, if->Has a value of 2, i.eIs 2 ² Multiplying the first correlation power sequence by 4, and amplifying the value of the first correlation power sequence at the moment; if->Has a value of-1, i.e. +.>Is 2 ^-1 The first correlation power sequence is multiplied by 1/2, and the value of the first correlation power sequence is reduced.

It should be noted that, the details of step S204 in the embodiment of fig. 2 can be referred to for the relevant content of step S304, and the disclosure is not repeated here.

Optionally, in step S305, the terminal device may determine the second shifting factor according to the first node power sequence.

Optionally, the first node power sequence may include a plurality of power values; the terminal equipment can acquire the maximum power value in the first node power sequence; and determining a second shifting factor based on the maximum power value. The calculation formula of the maximum power value in the first node power sequence and the calculation formula of the second shift factor are as follows:

wherein MaxTempCorrPwr may be the maximum power value in the first node power sequence,the second shifting factor signhit (MaxTempCorrPwr) may be the sign extension bit representing the maximum power value in the first node power sequence.

It should be noted that, in the processing procedure of the first PSS sample, the maximum power value may be directly obtained from the first node power sequence, and the second shifting factor may be determined according to the maximum power value. In the processing process of the non-first PSS sample, two node power sequences (e.g., the second node power sequence and the third node power sequence) may be obtained by performing shift processing twice, and then performing an arithmetic average operation on the two node power sequences to obtain an averaged node power sequence (e.g., the fourth node power sequence), so as to determine the second shift factor according to the maximum power value in the averaged node power sequence. Reference may be made specifically to the following detailed description of the corresponding embodiment of fig. 4, and this application is not repeated here.

Optionally, in step S306, the terminal device may branch and NID according to the frequency offset ⁽²⁾ And storing the second shifting factor at the indicated position for the next sample.

Alternatively, the terminal device may store the second shifting factor in a buffer. Alternatively, the terminal device may store the second shift factor in a buffer, such as a first buffer, corresponding to the second shift factor. Wherein different caches (e.g., the first cache described above, and the second cache referred to below) may provide writing and reading for the shifting factors (e.g., the first shifting factor and the second shifting factor). Referring to fig. 3A, fig. 3A is a schematic diagram of a cache structure. It should be noted that, in the embodiments of the present application, the size of the cache, the data storage format, and the read-write timing mentioned below are the same.

As can be seen from fig. 3A, the signal lines connecting the caches may include: a clock signal line CLK, a reset signal line rst_n, a chip select signal line CEN, a read/write enable signal line WEN, an address signal line ADDR, and an input data signal line DIN and an output data signal line DOUT. Where the depth of the cache may be 75, i.e. at most 75 shift factors may be stored. It should be noted that a single sample may contain 5 milliseconds of data, each millisecond of data may include up to 5 frequency offset branches and 3 NID ⁽²⁾ . Thus, there may be a maximum of 75 shifting factors in a single sample. The storage format of the 75 shift factors may be as shown in fig. 3B.

Optionally, in step S307, the terminal device may update the first shift factor according to the first shift factor and the second shift factor; and based on frequency offset branching and NID ⁽²⁾ The indicated location stores the updated first shift factor for use by the next sample. In one implementation, the updated first shift factor is a sum of the first shift factor and the second shift factor.

Optionally, the terminal device may store the updated first shifting factor in a cache. Optionally, the terminal device may store the updated first shift factor in a buffer corresponding to the shift factor, for example, a second buffer. Regarding the size of the first buffer and the related content of the data storage format, reference may be made to the details in step S306, which are not described herein.

Referring to fig. 3C, fig. 3C is a timing chart of reading and writing of the cache. It should be noted that, the read-write timing of the cache may be a mechanism of reading the history value and then writing the updated value. When the chip select signal line is low, as shown in FIG. 3C, it can be understood that the current bit is selected, i.e., the current bit is valid. When the read-write enable signal line is high, it can be understood that the current bit is read; when the read/write enable signal line is low, it can be understood that the current bit is written. Therefore, when address ADDR0 appears in the address signal lines, the chip select signal lines may be pulled low, i.e., the shift factor of address ADDR0 is read. After the shift factor of ADDR0 is read, the output data signal line outputs DOUT0. It should be noted that, the output data signal line will not output new data until the next reading is completed, otherwise, the previous data will be output all the time. After the shift factor is updated, the chip select signal line and the read/write enable signal line are pulled low, and at this time, the updated shift factor is input to the input data signal line, i.e., the updated shift factor is written into the original address ADDR0. It should be noted that when the next shift factor is to be processed, the above operation is repeated for the shift factor on ADDR 1.

Step S308, the terminal device determines whether the calculation of each path of data of the first PSS sample is completed, i.e. whether all frequency offset branches and NID are completed ⁽²⁾ Is calculated by the computer. If the calculation of each path of data of the first PSS sample is completed, step S309 is executed; if the calculation of each path of data of the first PSS sample is not completed, continuing the next frequency offset branch and NID ⁽²⁾ In step S301, a step of performing a correlation operation on the first PSS and the local PSS to obtain a first correlation sequence is performed.

In step S309, the terminal device ends the shift processing flow of the correlation power value of the first PSS sample.

By frequency offset branching and NID ⁽²⁾ Each path of data can be determinedThere is a first PSS sample of the path data, i.e., the shift processing for the first PSS sample described above can be performed for the first PSS sample in each path data. After the terminal device completes the shift processing for the first PSS sample in each path of data, the processing of the next PSS sample may be performed.

And performing correlation operation on the received first PSS and the local PSS to obtain a first correlation power sequence, determining a first shift factor according to the maximum power value in the first correlation power sequence, performing shift processing on the first correlation power sequence according to the first shift factor to obtain a first node power sequence, and determining a second shift factor according to the maximum power value in the first node power sequence to update the first shift factor according to the sum of the first shift factor and the second shift factor for use by the next sample.

Referring to fig. 4, fig. 4 is a flowchart of another power processing method according to an embodiment of the present application. The method takes a non-first PSS as a second PSS sample as an example, and describes the processing flow of the second PSS sample. The power processing method may be implemented by the above-mentioned terminal device, or may be implemented by a chip in the above-mentioned terminal device. As shown in fig. 4, the power processing method includes, but is not limited to, the following steps S401 to S411.

Step S401, the terminal device may receive a second PSS of the cell to be accessed, and perform a correlation operation on the second PSS and a local PSS to obtain a second correlation sequence; and then the power of the second correlation sequence is calculated to obtain a second correlation power sequence.

The second PSS may be any non-first PSS sample received by the terminal device, and the second correlation power sequence may be a correlation power sequence obtained by performing a correlation operation between the second PSS and the local PSS. Alternatively, the second correlation sequence may be formulatedA representation; the second correlated power sequence can be used +.>A representation; wherein k2 is a positive integer.

It should be noted that, the details of step S301 and step S302 in the embodiment of fig. 3 may be referred to for the relevant content of step S401, which is not described herein.

In step S402, the terminal device acquires the updated first shifting factor (e.g., referred to as the first shifting factor 1).

Optionally, the terminal device may obtain the first shifting factor 1 from the second buffer. The first shifting factor 1 may be a sum of the first shifting factor and the second shifting factor.

It should be noted that, in the shifting process of any non-first PSS sample, the updated first shifting factor may be determined according to the historical node power sequence. For example, if the non-first PSS sample received by the terminal device is the tenth PSS sample, the updated first shifting factor may be determined according to the first shifting factor and the second shifting factor in the ninth PSS sample.

From the foregoing, it can be seen that for the storage of shift factors (e.g., the second shift factor and the first shift factor 1) the frequency offset and NID can be determined ⁽²⁾ The indicated locations are stored in caches (e.g., first cache and second cache) accordingly. Therefore, when acquiring the shift factor, the frequency offset branch and NID with the current PSS sample can be acquired in the buffer ⁽²⁾ A corresponding shifting factor.

In step S403, the terminal device performs shift processing on the third related power sequence according to the updated first shift factor (i.e. the first shift factor 1) to obtain a second node power sequence. The third correlation power sequence is the sum of the first correlation power sequence and the second correlation power sequence.

Specifically, the calculation formula of the second node power sequence is as follows:

/>

wherein,the current node power sequence, namely the second node power sequence, is given by +.>The related power sequence that currently needs to be shifted, i.e. the third related power sequence described above, may be used. Specifically, the first correlation power sequence and the second correlation power sequence each include a plurality of power values, and the third correlation power sequence is the sum of the corresponding power values of the first correlation power sequence and the second correlation power sequence, which can be understood asIn the process of shifting the third related power sequence, if the first shifting factor 1 is a positive value, shifting to the left, namely amplifying the value of the third related power sequence; if the first shifting factor 1 is negative, the value of the third related power sequence is scaled down. The specific details can be seen from the above detailed description of step S304 in the corresponding embodiment of fig. 3, and the detailed description is omitted herein.

It should be noted that, in the shift process of any non-first PSS sample, the relevant power sequence currently required to be shifted may be determined according to the sum of the relevant power sequence of the historical PSS sample and the relevant power sequence of the received PSS sample. For example, assuming that the PSS sample received by the terminal device is the tenth PSS sample, the correlation power sequence currently required for the shift processing may be a sum of the correlation power sequences of the first nine PSS samples and the correlation power sequence of the tenth PSS sample.

In step S404, the terminal device acquires a second shifting factor.

Optionally, the terminal device may obtain the second shifting factor from the first buffer. Optionally, when acquiring the second shift factor, the terminal device may acquire the frequency offset branch and NID with the current PSS sample in the first buffer ⁽²⁾ Corresponding second shiftA bit factor. Alternatively, the second shifting factor may be usedAnd (3) representing.

It should be noted that, the second shift factor may be a second shift factor stored in the first buffer during the shift process of the historical PSS sample, that is, a second shift factor determined according to the historical PSS sample. For example, assuming that the PSS sample received by the terminal device is the tenth PSS sample, the second shifting factor acquired by the terminal device may be a second shifting factor corresponding to the ninth PSS sample.

In step S405, the terminal device performs a shift process on the first related power sequence according to the second shift factor, to obtain a third node power sequence.

Optionally, the calculation formula of the third node power sequence is as follows:

wherein,can be a historical node power sequence, namely the third node power sequence, namely +.>May be a historical correlated power sequence, i.e. the first correlated power sequence described above. It should be noted that, in the embodiment of the present application, since the non-first PSS sample received by the terminal device is the second PSS sample, that is, the second PSS sample; thus, the historical correlated power sequence may be the first correlated power sequence. It may be appreciated that, if the non-first PSS sample received by the terminal device is the tenth PSS sample, the historical relevant power sequence may be the sum of relevant power sequences of the first nine PSS samples, which is not limited in this application.

Step S406, the terminal device may perform arithmetic average operation on the corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; and determining the maximum power value of the fourth power sequence according to the fourth node power sequence. Alternatively, the maximum power value of the fourth power sequence may be represented by maxacucorrpwr.

It should be noted that, the second node power sequence and the third node power sequence each include a plurality of power values, and the corresponding power values in the two node power sequences may be subjected to arithmetic average operation. For example: if k=6, that is, there are 6 node power values in both the historical sample data and the current sample data, the node power values corresponding to the 6 nodes are added and averaged, for example: and adding the first node power value in the second node power sequence with the first node power value in the third node power sequence, and solving the power average value of the first node, namely the first node power value in the fourth node power sequence.

Optionally, the terminal device may output a node power value exceeding a threshold value in the fourth node power sequence, so as to determine the PSS position of the cell to be accessed according to the node power value exceeding the threshold value. Optionally, the terminal device may further determine a maximum power value of the accumulated node power sequence according to the fourth node power sequence. For example, assuming that k=6, after calculating the average value of the power of 6 nodes, the terminal device may find the maximum power value from the 6 power values, for example: the power value of the second node is the largest, i.e. the power value of the second node is the accumulated largest power value.

Optionally, in step S407, the terminal device may update the second shifting factor (e.g. referred to as the second shifting factor 1) according to the maximum power value of the fourth node power sequence.

Optionally, the calculation formula of the second shift factor1 is as follows:

wherein,the second shift factor1 may be used, and the normfactor2 may be a default value for the software configuration; maxacucorrpwr is the maximum power value in the fourth node power sequence and signbit (MaxAccuCorrPwr) represents the sign extension bit for maxacucorrpwr. The Normfactor2 may be the same as or different from the Normfactor1, and is not limited in this application.

Optionally, in step S408, the terminal device may branch and NID according to the frequency offset ⁽²⁾ The indicated position stores the updated second shift factor (i.e., second shift factor 1) for use with the next sample.

It should be noted that, the details of step S408 can be referred to in the embodiment of fig. 3, and the disclosure is not repeated here.

Optionally, in step S409, the terminal device may update the updated first shift factor (e.g. referred to as the first shift factor 2) according to the updated first shift factor (i.e. the first shift factor 1) and the updated second shift factor (i.e. the second shift factor 1); and based on frequency offset branching and NID ⁽²⁾ The indicated position is stored for use by the next sample, the first shifting factor updated again (i.e. the first shifting factor 2).

It should be noted that the first shift factor 2 may be determined by the first shift factor 1 and the second shift factor 1. That is, the first shift factor, which may be updated by the first shift factor used by the previous PSS sample and the second shift factor updated by the current PSS sample, is updated again, and the updated first shift factor may be used for the shift processing of the next sample. For example, if the terminal device receives the tenth non-first PSS sample, the terminal device may update the first shift factor again according to the first shift factor used by the ninth non-first PSS sample and the second shift factor updated at the tenth non-first PSS sample for use by the eleventh non-first PSS sample.

It should be noted that, the details of step S409 can be referred to in the embodiment of fig. 3, and the detailed description of step S307 is omitted herein.

Step S410, the terminal device determines whether the calculation of each path of data of the non-first PSS sample is completed, i.e. whether all frequency offset branches and NID are completed ⁽²⁾ Is calculated by the computer. If the calculation of each path of data of the non-first PSS sample is completed, step S411 is executed; if the calculation of each path of data of the non-first PSS sample is not completed, continuing the next frequency offset branching and NID ⁽²⁾ In step S401, the second PSS and the local PSS are correlated to obtain a second correlation sequence.

In step S411, the terminal device ends the shift processing flow of the correlation power value of the non-first PSS sample.

It should be noted that, the details of step S308 and step S309 in the embodiment of fig. 3 can be referred to for the relevant content of step S410 and step S411, which are not described herein.

Performing correlation operation on the received second PSS and the local PSS to obtain a second correlation power sequence; acquiring a first shifting factor updated after the shifting process of the last PSS sample, and carrying out shifting process on a third related power sequence determined by the second related power sequence and the historical related power sequence to obtain a second node power sequence; acquiring a second shifting factor of the last PSS sample, and carrying out shifting treatment on the historical related power sequence to obtain a third node power sequence; and determining a fourth node power sequence according to the second node power sequence and the third node power sequence, so as to output a node power value exceeding a threshold value in the fourth node power sequence, and further determining the position of the PSS of the cell to be accessed.

According to the power processing method for the first PSS sample and the non-first PSS sample, the received PSS and the local PSS can be subjected to correlation operation by utilizing the autocorrelation and the cross correlation of the PSS, so that a correlation power sequence is determined, and a shift factor corresponding to each PSS sample is determined in real time according to the maximum power value in the correlation power sequence, so that the correlation power sequence can be subjected to shift processing according to the shift factor updated in real time, and further the shift factor can be dynamically adjusted according to an actual scene and signal quality, so that the shifted power value is more accurate, and the screening of the position of the PSS of a cell to be accessed is facilitated.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a communication device according to an embodiment of the present application. The device can be a terminal device, a device in the terminal device, or a device which can be matched with the terminal device for use. The communication apparatus shown in fig. 5 may include a communication unit 501, a processing unit 502, and a determination unit 503. The processing unit 502 is configured to perform data processing. Wherein:

the communication unit 501 is configured to receive a first primary synchronization signal PSS of a cell to be accessed;

The processing unit 502 is configured to perform a correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

the determining unit 503 is configured to determine a first shifting factor according to the first correlation power sequence;

the processing unit 502 is further configured to perform shift processing on the first related power sequence according to the first shift factor, to obtain a first node power sequence.

In one implementation manner, the processing unit 502 is further configured to obtain a maximum power value in the first related power sequence; the determining unit 503 is further configured to determine a first shifting factor according to the maximum power value.

In one implementation, the determining unit 503 is further configured to determine a second shifting factor according to the first node power sequence; the processing unit 502 is further configured to update the first shift factor according to the first shift factor and the second shift factor, to obtain an updated first shift factor; the communication unit 501 is further configured to receive a second PSS of the cell to be accessed; the processing unit 502 is further configured to perform a correlation operation on the second PSS and a local PSS to obtain a second correlation power sequence; the processing unit 502 is further configured to perform shift processing on the third related power sequence according to the updated first shift factor, to obtain a second node power sequence; wherein the third correlation power sequence is the sum of the first correlation power sequence and the second correlation power sequence.

In one implementation, the processing unit 502 is further configured to update the second shifting factor according to the second node power sequence.

In one implementation manner, the processing unit 502 is further configured to perform a shift process on the first related power sequence according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; the processing unit 502 is further configured to perform an arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; the processing unit 502 is further configured to update the second shifting factor according to the fourth node power sequence.

In one implementation manner, the processing unit 502 is further configured to obtain a maximum power value in the first node power sequence; the determining unit 503 is further configured to determine the second shifting factor according to the maximum power value.

According to the embodiment of the present application, each unit in the communication apparatus shown in fig. 5 may be separately or completely combined into one or several additional units, or some (some) units may be further split into a plurality of units with smaller functions to form a unit, which may achieve the same operation without affecting the implementation of the technical effects of the embodiments of the present application. The above units are divided based on logic functions, and in practical applications, the functions of one unit may be implemented by a plurality of units, or the functions of a plurality of units may be implemented by one unit. In other embodiments of the present application, the communication device may also include other units, and in practical applications, these functions may also be implemented with assistance of other units, and may be implemented by cooperation of multiple units.

The communication device may be, for example: a chip, or a chip module. With respect to each apparatus and each module included in the product described in the above embodiments, it may be a software module, or may be a hardware module, or may be a software module partially, or may be a hardware module partially. For example, for each device or product applied to or integrated in a chip, each module included in the device or product may be implemented in hardware such as a circuit, or at least some modules may be implemented in software program, where the software program runs on a processor integrated in the chip, and the remaining (if any) some modules may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module contained in the device and product can be realized in a hardware mode such as a circuit, different modules can be located in the same component (such as a chip and a circuit module) of the chip module or in different components, or at least part of the modules can be realized in a software program, the software program runs in a processor integrated in the chip module, and the rest (if any) of the modules can be realized in a hardware mode such as a circuit; for each device and product applied to or integrated in the terminal, each module included in the device and product may be implemented by hardware such as a circuit, and different modules may be located in the same component (for example, a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules may be implemented by software programs running on a processor integrated in the terminal, and the rest (if any) of the modules may be implemented by hardware such as a circuit.

The embodiments of the present application and the embodiments of the foregoing methods are based on the same concept, and the technical effects brought by the embodiments are the same, and the specific principles are described with reference to the foregoing embodiments and are not repeated herein.

Referring to fig. 6, fig. 6 is a schematic diagram of a communication device 60 according to an embodiment of the present application. As shown in fig. 6, the communication device 60 may include a transceiver 601 and a processor 602. Optionally, the communication device may further comprise a memory 603. Wherein the transceiver 601, processor 602, and memory 603 may be connected by a bus 604 or otherwise. The bus is shown in bold lines in fig. 6, and the manner in which other components are connected is merely illustrative and not limiting. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 6, but not only one bus or one type of bus.

The coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units, or modules, which may be in electrical, mechanical, or other forms for information interaction between the devices, units, or modules. The specific connection medium between the transceiver 601, the processor 602, and the memory 603 is not limited in the embodiments of the present application.

Memory 603 may include read only memory and random access memory and provide instructions and data to processor 602. A portion of memory 603 may also include non-volatile random access memory.

The processor 602 may be a central processing unit (Central Processing Unit, CPU), the processor 602 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field-programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor, but in the alternative, the processor 602 may be any conventional processor or the like. Wherein:

memory 603 for storing program instructions.

A processor 602 for invoking program instructions stored in memory 603 for:

a transceiver 601 is invoked for receiving a first primary synchronization signal PSS of a cell to be accessed;

the processor 602 is further configured to perform a correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

The processor 602 is further configured to determine a first shifting factor according to the first correlation power sequence;

the processor 602 is further configured to perform a shift process on the first related power sequence according to the first shift factor, to obtain a first node power sequence.

In one implementation, the processor 602 is further configured to obtain a maximum power value in the first related power sequence; the processor 602 is further configured to determine a first shifting factor according to the maximum power value.

In one implementation, the processor 602 is further configured to determine a second shifting factor according to the first node power sequence; the processor 602 is further configured to update the first shift factor according to the first shift factor and the second shift factor, to obtain an updated first shift factor; the transceiver 601 is further configured to receive a second PSS of the cell to be accessed; the processor 602 is further configured to perform a correlation operation on the second PSS and a local PSS to obtain a second correlation power sequence; the processor 602 is further configured to perform shift processing on the third related power sequence according to the updated first shift factor to obtain a second node power sequence; wherein the third correlation power sequence is the sum of the first correlation power sequence and the second correlation power sequence.

In one implementation, the processor 602 is further configured to update the second shifting factor according to the second node power sequence.

In one implementation, the processor 602 is further configured to perform a shifting process on the first related power sequence according to the second shifting factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; the processor 602 is further configured to perform an arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; the processor 602 is further configured to update the second shifting factor according to the fourth node power sequence.

In one implementation, the processor 602 is further configured to obtain a maximum power value in the first node power sequence; the processor 602 is further configured to determine the second shifting factor according to the maximum power value.

In the present embodiment, the method provided by the present embodiment may be implemented by running a computer program (including program code) capable of executing the steps involved in the respective methods as shown in fig. 2, 3 and 4 on a general-purpose computing device such as a computer including a Central Processing Unit (CPU), a random access storage medium (RAM), a read only storage medium (ROM), etc., and a processing element such as a storage element. The computer program may be recorded on, for example, a computer-readable recording medium, and loaded into and run in the above-described computing device through the computer-readable recording medium.

Based on the same inventive concept, the principle and beneficial effects of the communication device for solving the problems provided in the embodiments of the present application are similar to those of the communication device for solving the problems in the embodiments of the method of the present application, and may refer to the principle and beneficial effects of implementation of the method, which are not described herein for brevity.

The embodiment of the application also provides a chip, which can execute the relevant steps of the terminal equipment in the embodiment of the method. The chip is used for: receiving a first primary synchronization signal PSS of a cell to be accessed; performing correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

the chip is further configured to determine a first shifting factor according to the first correlation power sequence;

and the chip is further configured to perform shift processing on the first related power sequence according to the first shift factor, so as to obtain a first node power sequence.

In one implementation manner, the chip is further configured to obtain a maximum power value in the first related power sequence; the chip is further configured to determine a first shifting factor according to the maximum power value.

In one implementation, the chip is further configured to determine a second shifting factor according to the first node power sequence; the chip is further configured to update the first shift factor according to the first shift factor and the second shift factor, to obtain an updated first shift factor; the chip is further configured to receive a second PSS of the cell to be accessed; the chip is further configured to perform a correlation operation on the second PSS and a local PSS to obtain a second correlation power sequence; the chip is further configured to perform shift processing on the third related power sequence according to the updated first shift factor, so as to obtain a second node power sequence; wherein the third correlation power sequence is the sum of the first correlation power sequence and the second correlation power sequence.

In one implementation, the chip is further configured to update the second shifting factor according to the second node power sequence.

In one implementation manner, the chip is further configured to perform shift processing on the first related power sequence according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; the chip is further configured to perform an arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; the chip is further configured to update the second shifting factor according to the fourth node power sequence.

In one implementation manner, the chip is further configured to obtain a maximum power value in the first node power sequence; the chip is further configured to determine the second shifting factor according to the maximum power value.

In one implementation, the chip includes at least one processor, at least one first memory, and at least one second memory; wherein the at least one first memory and the at least one processor are interconnected by a circuit, and instructions are stored in the first memory; the at least one second memory and the at least one processor are interconnected by a line, where the second memory stores data to be stored in the embodiment of the method.

For each device and product applied to or integrated in the chip, each module contained in the device and product can be realized in a hardware mode such as a circuit, or at least part of the modules can be realized in a software program, the software program runs on a processor integrated in the chip, and the rest (if any) of the modules can be realized in a hardware mode such as a circuit.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a module device according to an embodiment of the present application. The module device 70 may perform the steps related to the terminal device in the foregoing method embodiment, where the module device 70 includes: a communication module 701, a power module 702, a memory module 703 and a chip module 704.

Wherein, the power module 702 is used for providing power for the module equipment; the storage module 703 is used for storing data and instructions; the communication module 701 is used for performing internal communication of the module device or for performing communication between the module device and an external device; the chip module 704 is configured to:

receiving a first primary synchronization signal PSS of a cell to be accessed;

performing correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

the chip module 704 is further configured to determine a first shift factor according to the first correlation power sequence;

The chip module 704 is further configured to perform a shift process on the first related power sequence according to the first shift factor, to obtain a first node power sequence.

In one implementation, the chip module 704 is further configured to obtain a maximum power value in the first related power sequence; the chip module 704 is further configured to determine a first shifting factor according to the maximum power value.

In one implementation, the chip module 704 is further configured to determine a second shifting factor according to the first node power sequence; the chip module 704 is further configured to update the first shift factor according to the first shift factor and the second shift factor, to obtain an updated first shift factor; the chip module 704 is further configured to receive a second PSS of the cell to be accessed; the chip module 704 is further configured to perform a correlation operation on the second PSS and a local PSS to obtain a second correlation power sequence; the chip module 704 is further configured to perform shift processing on the third related power sequence according to the updated first shift factor, to obtain a second node power sequence; wherein the third correlation power sequence is the sum of the first correlation power sequence and the second correlation power sequence.

In one implementation, the chip module 704 is further configured to update the second shift factor according to the second node power sequence.

In one implementation manner, the chip module 704 is further configured to perform a shift process on the first related power sequence according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; the chip module 704 is further configured to perform an arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; the chip module 704 is further configured to update the second shift factor according to the fourth node power sequence.

In one implementation, the chip module 704 is further configured to obtain a maximum power value in the first node power sequence; the chip module 704 is further configured to determine the second shifting factor according to the maximum power value.

For each device and product applied to or integrated in the chip module, each module included in the device and product may be implemented by hardware such as a circuit, and different modules may be located in the same component (e.g. a chip, a circuit module, etc.) of the chip module or different components, or at least some modules may be implemented by using a software program, where the software program runs on a processor integrated in the chip module, and the remaining (if any) modules may be implemented by hardware such as a circuit.

Embodiments of the present application also provide a computer readable storage medium having one or more instructions stored therein, the one or more instructions being adapted to be loaded by a processor and to perform the methods provided by the method embodiments described above.

The present application also provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method provided by the method embodiments described above.

It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the described order of action, as some steps may take other order or be performed simultaneously according to the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The modules in the device of the embodiment of the application can be combined, divided and deleted according to actual needs.

Those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be implemented by a program to instruct related hardware, the program may be stored in a computer readable storage medium, and the readable storage medium may include: flash disk, read-Only Memory (ROM), random-access Memory (Random Access Memory, RAM), magnetic or optical disk, and the like.

The foregoing disclosure is merely a preferred embodiment of the present invention, but is not limited thereto. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Claims

1. A method of power processing, the method comprising:

receiving a first primary synchronization signal PSS of a cell to be accessed;

Determining a first shift factor according to the first related power sequence;

performing shift processing on the first related power sequence according to the first shift factor to obtain a first node power sequence;

determining a second shifting factor according to the first node power sequence;

updating the first shifting factor according to the first shifting factor and the second shifting factor to obtain an updated first shifting factor;

receiving a second PSS of the cell to be accessed;

performing correlation operation on the second PSS and the local PSS to obtain a second correlation power sequence;

performing shift processing on a third related power sequence according to the updated first shift factor to obtain a second node power sequence; the third correlated power sequence is the sum of the first correlated power sequence and the second correlated power sequence.

2. The method of claim 1, wherein the first correlated power sequence comprises a plurality of power values; the determining a first shift factor according to the first related power sequence includes:

obtaining the maximum power value in the first related power sequence;

and determining the first shifting factor according to the maximum power value.

3. The method according to claim 1, wherein the method further comprises:

and updating the second shifting factor according to the second node power sequence.

4. A method according to claim 3, wherein said updating said second shift factor according to said second node power sequence comprises:

performing shift processing on the first related power sequence according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each comprise a plurality of power values;

carrying out arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence;

and updating the second shifting factor according to the fourth node power sequence.

5. The method of any of claims 1-4, wherein the first node power sequence comprises a plurality of power values; the determining a second shift factor according to the first node power sequence includes:

obtaining the maximum power value in the first node power sequence;

and determining the second shifting factor according to the maximum power value.

6. The method of any of claims 1-4, wherein the updated first shift factor is a sum of the second shift factor and the first shift factor.

7. A communication device comprising means for performing the method of any of claims 1-6.

8. A communication device comprising a processor;

the processor being configured to perform the method of any one of claims 1 to 6.

9. The communication device of claim 8, wherein the communication device further comprises a memory:

the memory is used for storing a computer program;

the processor is in particular configured to invoke the computer program from the memory for performing the method according to any of the claims 1-6.

10. The utility model provides a module equipment, its characterized in that, module equipment includes communication module, power module, storage module and chip module, wherein:

the power supply module is used for providing electric energy for the module equipment;

the storage module is used for storing data and instructions;

the communication module is used for carrying out internal communication of module equipment or carrying out communication between the module equipment and external equipment;

The chip module is used for:

receiving a first primary synchronization signal PSS of a cell to be accessed;

determining a first shift factor according to the first related power sequence;

receiving a second PSS of the cell to be accessed;