CN113793635B - Storage device and storage apparatus - Google Patents
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- G—PHYSICS
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
Abstract
One or more embodiments of the present specification provide a storage apparatus and a storage device, the storage apparatus including: a non-volatile memory, and peripheral circuitry adapted to the non-volatile memory; the decoder is electrically connected with the peripheral circuit and used for reading target data from the nonvolatile memory through the peripheral circuit and carrying out error correction decoding on the target data.
Description
Technical Field
One or more embodiments of the present disclosure relate to the field of storage technologies, and in particular, to a storage apparatus and a storage device.
Background
With the rapid development of memory technology, more and more high-capacity high-density memory devices are being designed and manufactured. The storage device generally includes two parts, a controller for distributing data transmission and transferring data, and a storage device for storing data, wherein the controller and the storage device perform data transmission through a preset interactive interface. The controller is usually provided with an ECC (Error Correction Coding) module for performing Error detection and Correction on data read from the storage device.
In the related art, as the capacity and density of the storage device increase, higher performance requirements are placed on the ECC module, for example, a strong error correction capability needs to be provided, and sufficient throughput needs to match a data stream, so that the area and power consumption of the ECC module become larger and larger, which not only increases the design cost of the controller, but also may cause blocking on an interactive interface.
Disclosure of Invention
In view of the above, one or more embodiments of the present specification provide a storage apparatus and a storage device.
To achieve the above object, one or more embodiments of the present disclosure provide the following technical solutions:
according to a first aspect of one or more embodiments of the present specification, there is provided a storage apparatus comprising:
a non-volatile memory, and peripheral circuitry adapted to the non-volatile memory;
the decoder is electrically connected with the peripheral circuit and used for reading target data from the nonvolatile memory through the peripheral circuit and carrying out error correction decoding on the target data.
According to a second aspect of one or more embodiments of the present specification, there is provided a storage device including:
a controller, and a storage device as described in the first aspect.
In the technical solution provided in this specification, the decoder originally located in the controller is implemented in the storage device, so that the space occupation of the controller can be reduced, the module layout of the controller can be optimized, and the design cost and power consumption of the controller can be reduced. Meanwhile, the decoder can directly perform data interaction with the storage device without occupying an interaction interface between the controller and the storage device, so that the data reading efficiency of the decoder can be improved, and the data throughput between the controller and the storage device can be improved.
Drawings
FIG. 1 is a schematic diagram of a memory device provided in an exemplary embodiment;
FIG. 2 is a schematic diagram of an exemplary embodiment of a layout of modules within a controller and memory device;
FIG. 3 is a schematic diagram of another exemplary embodiment of an arrangement of modules within a controller and memory device;
FIG. 4 is a schematic diagram of an integration of a memory device according to an exemplary embodiment;
FIG. 5 is a schematic diagram of a peripheral circuit configuration in accordance with an exemplary embodiment;
FIG. 6 is a schematic diagram of another peripheral circuit configuration in accordance with an exemplary embodiment;
FIG. 7 is a hard decoder architecture diagram of an exemplary embodiment;
FIG. 8 is a Tanner graph corresponding to a check matrix of an example embodiment;
fig. 9 is a diagram of a soft information transfer in an example embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with one or more embodiments of the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of one or more embodiments of the specification, as detailed in the claims which follow.
It should be noted that: in other embodiments, the steps of the corresponding methods are not necessarily performed in the order shown and described herein. In some other embodiments, the method may include more or fewer steps than those described herein. Moreover, a single step described in this specification may be broken down into multiple steps for description in other embodiments; multiple steps described in this specification may be combined into a single step in other embodiments.
The storage devices widely used nowadays mainly include mechanical hard disks using ferromagnetic materials as storage media and SSDs (Solid State disks) using FLASH memories as storage media. In the SSD, taking the NAND flash memory as an example, the reliability of the NAND flash memory may be reduced due to the error code mechanisms such as interference and charge leakage during the read/write process. In addition, the NAND flash memory may have defects (e.g., defective memory cells, etc.), and further defects may occur due to wear of flash memory particles during use of the NAND flash memory, and the presence of the defects may cause errors in stored data. Also, in the mechanical hard disk, data errors may be caused by abrasion of a mechanical structure, entrance of dust into the mechanical hard disk, or failure of a magnetic head responsible for reading data from a storage medium. It is therefore desirable to ensure the reliability of data replication through error detection and correction techniques. Conventional error detection and correction requires proper data encoding and data decoding. And encoding the input data by using a specific ECC strategy through an ECC encoding module, and performing error correction decoding on the encoded data by using an ECC decoding module corresponding to the ECC encoding module to finally obtain corrected data.
The ECC decoding module generally consists of a hard decoder (hard decoder) and a soft decoder (soft decoder), and the hard decoder and the soft decoder can perform ECC decoding independently or cooperatively. The hard decoder and the soft decoder may be collectively referred to as a decoder (ECC decoder). Taking the SSD as an example, the ECC decoding module in the related art is integrated in the controller of the SSD, which results in complicated design and increased cost of the controller. Meanwhile, no matter the decoder is a hard decoder or a soft decoder, when data to be decoded needs to be read from a nonvolatile memory such as a NAND flash memory serving as a storage device, the data needs to pass through an interactive interface between the SSD controller and the storage device, which may cause data congestion and reduce the transmission rate of the data for the interactive interface.
In order to solve the above problems, the present specification provides a technical solution to shift a decoder originally implemented in a controller to a storage device.
In an exemplary embodiment of the present description, a storage device 11 as shown in fig. 1 is presented. The apparatus includes a Non-volatile memory (Non-volatile memory) 110, a Peripheral circuit (Peripheral circuit) 120 adapted to the Non-volatile memory, and a decoder 130 for reading target data from the Non-volatile memory through the Peripheral circuit 120 and performing error correction decoding.
In the present embodiment, the decoder 130 is directly electrically connected to the peripheral circuit 120, and the peripheral circuit 120 reads the required data to be decoded, i.e. the target data, from the nonvolatile memory 110. Thus, the decoder 130 when decoding will no longer need to read the data to be decoded stored in the non-volatile memory 110 through the interactive interface between the controller of the SSD and the storage device 11, but directly through the peripheral circuit 120. Through the data transmission mode, the interactive interface only needs to transmit the data decoded by the decoder 130 to the controller for subsequent processing, and the data congestion of the interactive interface is relieved. Also, as shown in fig. 2, by transferring the decoder 130 from the controller 21 to the storage device 11, a large area occupied by the decoder 130 in the controller 21 is released, thereby contributing to a reduction in design cost and power consumption of the controller 21. When the present embodiment is implemented based on an SSD, the nonvolatile memory 110 may be a flash memory array.
In an exemplary embodiment of the present application, as shown in fig. 3, in consideration of the area limitation of the nonvolatile memory, a part of the decoder 130, i.e., the hard decoder 1301, located in the controller 21 may be transferred to the storage device 11 to be implemented, while the soft decoder 1302 in the controller 21 is reserved. Since the hard decoder 1301 and the soft decoder 1302 in the decoder 130 work together, but the layout positions may be relatively independent, in this embodiment, the decoder 130 is composed of the hard decoder 1301 located in the storage device and the soft decoder 1302 located in the controller 21, and data transmission is performed between the hard decoder 1301 and the soft decoder 1302 through the interactive interface between the controller 21 and the storage device 11. By transferring the hard decoder of the decoder 130 from the controller 21 to the storage device 11, only the soft decoder 1302 is reserved in the controller 21, and the layout of the decoder 130 inside the controller 21 can be adjusted from the left side of fig. 3 to the right side of fig. 3, wherein the hard decoder 1301 in the dotted line part is transferred from the controller 21 to the storage device 11. The area released in the controller can be used for realizing other functions of the SSD controller, and also can reduce the occupied area of the decoder 130 in the controller 21, and reduce the design cost and power consumption of the controller 21.
Similarly, in another exemplary embodiment of the present application, only the soft decoder may be transferred to the storage device to be implemented, and the hard decoder may be retained in the controller, so that the space provided by the storage device may also be utilized to reduce the space occupied by the decoder in the controller.
Since ECC decoding is performed after data format is converted into code domain, the principle of error detection and correction for data stored in solid state disk, mechanical hard disk, or other types of nonvolatile memory is the same, and can be performed by the decoder with the same mechanism, so a storage device similar to that in fig. 1 can also be applied to mechanical hard disk or other types of storage devices.
In an exemplary embodiment of the present specification, the nonvolatile memory may be a 3D flash memory (3D flash), for example, a 3D NAND flash memory. The 3D flash memory changes the arrangement mode of the flash memory array from the original two-dimensional space arrangement into the longitudinal multi-layer stacking, and can effectively improve the data volume which can be contained in a unit area. Due to the high density of the 3D flash memory, the 3D flash memory can still provide enough surface space to accommodate the decoder integrated on its surface after integrating the peripheral circuitry adapted to the 3D flash memory. In the integration manner shown in fig. 4, the decoder 130 set may be vertically integrated in one area of the top of the 3D flash array 410, and the peripheral circuit 120 may be integrated in another area of the 3D flash array 410. When the 3D flash memory is mounted on a circuit board, the surface to which it is soldered is referred to as the bottom surface, while the other surface parallel to the bottom surface provides a larger surface area available for integrated peripheral circuits and decoders, and this surface is referred to as the top surface. This integration skillfully utilizes the space at the top of the 3D flash array, and since the decoder 130 is located On the top surface of the 3D flash array 410 at this time, it can be called an On-chip ECC decoder.
Of course, the space at the top of the non-volatile memory can be used for integrating only the hard decoder or the soft decoder, and the rest of the ECC decoding module is kept in the controller for implementation. Even one or several groups of soft decoders and hard decoders can be realized in the storage device, the data to be decoded, namely the target data from the storage device is decoded, then the decoded result of the preamble is sent to a subsequent decoding module in the controller, the module can also be composed of several hard decoders matched with the soft decoders, and the subsequent decoding step is carried out on the basis of the decoded result of the preamble through the subsequent decoding module, so that the decoding of the target data is completed.
In an exemplary embodiment of the present specification, the electrical connection of the decoder 130 and the peripheral circuit 120 may be implemented in the manner as shown in fig. 5. FIG. 5 shows a peripheral circuit and decoder 130 integrated on a flash array 506, wherein the peripheral circuit may include: a Toggle/ONFI interface (Toggle/ONFI interface) 501 for inputting and outputting data signals, an Address decoder (Address decoder) 502 for selecting a memory cell, and a Page buffer (Page buffer) 503 for buffering read or written data. The flash array 506 is electrically connected to the decoder 130 through the page buffer 503. When the decoder 130 reads data from the flash memory array 506, the target data from the flash memory array 506 is first buffered by the page buffer 503, and then the buffered target data is read from the page buffer 503 by the decoder 130 for decoding.
In another exemplary embodiment of the present specification, the electrical connection of the decoder 130 and the peripheral circuit 120 may be implemented in the manner as shown in fig. 6. Fig. 6 shows the aforementioned peripheral circuit 120 and decoder 130 integrated on the flash memory array 506, which is different from the implementation in fig. 5 in that the peripheral circuit 120 further includes an extended buffer (extended buffer) 604, the extended buffer 604 is electrically connected to the page buffer 503, and the target data read from the flash memory array 506 is buffered by the page buffer 503, at this time, the target data to be decoded is buffered in the extended buffer 604, when data is decoded from the flash memory array 506, the extended buffer 604 is equivalent to a special area for specially buffering the data to be decoded, and at this time, the existence of the extended buffer 604 can improve the decoding efficiency. In order to avoid the expansion buffer 604 from being idle when no target data is decoded from the flash memory array 506, the expansion buffer 604 may be used as an additional buffer area of the page buffer 503, which is equivalent to enlarging the page buffer 503 to achieve an acceleration of the write performance.
The ECC hard decoder in this specification may employ any hard decoder technique in the related art, and this specification does not limit this. For ease of understanding, a specific implementation of an ECC hard decoder is described below in conjunction with FIG. 7. As shown in fig. 7, the hard decoder may include: a Read buffer (Read buffer) 701, a Code parity check matrix (Code parity check matrix) 702, a Syndrome calculator (Syndrome calculation) 703, and a Correction selector (Correction selection) 704.
The read buffer 701 reads data to be decoded stored in the nonvolatile memory through the peripheral circuit, and the data to be decoded is buffered in the read buffer 701 for decoding. In addition, the read buffer 701 and the controller may perform data interaction through an interaction interface as described above. The code parity check matrix 702 is a nonvolatile memory in which code information for decoding is stored. The syndrome calculator 703 performs an operation on the data to be decoded read from the read buffer 701 based on the code information stored in the code parity check matrix 702 to generate a syndrome associated with the data to be decoded. The correction selector 704 selectively corrects the erroneous bits of the data to be decoded according to the syndrome generated by the syndrome calculator 703, generates a corrected hard decoding result, and generates identification information that matches the hard decoding result, which may include information of the number of attempts of hard decoding, whether error correction decoding is successful, and the like.
The ECC decoding module can also comprise a scrambler and a descrambler. The scrambler is used for adding scrambling codes to the data signals to inhibit long connection of '0' or '1' in the signals so as to facilitate the extraction of the signals, and the descrambler is used for restoring the scrambled data into original unscrambled data. The scrambler in the ECC decoding module may be disposed in the controller, and the data is scrambled by the scrambler when the controller writes the data into the storage device. In an exemplary embodiment of the present specification, when the decoder is transferred from the controller to be implemented in the storage device, both the scrambler and the descrambler are implemented following the transfer of the decoder to the storage device. In another exemplary embodiment of the present specification, when the hard decoder is transferred from the controller to the storage device, the descrambler may be transferred from the controller to the storage device, and at this time, the scrambler is retained in the controller as in the soft decoder. Wherein the descrambler may be implemented in a hard decoder. In the process of hard decoding the data, the hard decoder firstly reads the scrambled data from the storage device, the descrambler in the hard decoder restores the data to be decoded, and then the hard decoder hard decodes the data to be decoded.
After the data to be decoded is decoded by the hard decoder integrated in the storage device, the decoding may fail in consideration of the performance limitation of the hard decoder. In order to solve the above problem, in case of failure of error correction decoding, the soft decoder may further perform decoding to improve the probability of successful decoding. The decoding process between the hard decoder and the soft decoder may be independent of each other. In order to improve the decoding efficiency and success probability, when the hard decoder confirms that the decoding of the hard decoder fails, soft information (soft information) required by the soft decoder can be generated by the hard decoder and sent to the soft decoder, so that the soft decoder continues to perform error correction decoding on the target data processed by the hard decoder through the soft information. In an exemplary embodiment of the present specification, when the hard decoder is implemented in the storage device, and the soft decoder in the controller is reserved, the above-mentioned soft information generated by the hard decoder needs to be transmitted via an interactive interface between the storage device and the controller, so as to be transmitted to the soft decoder. In an exemplary embodiment of the present specification, the identification information generated by the correction selector 704 may further include soft information required by the soft decoder if the hard decoder fails in error correction decoding.
In the following, an ECC decoder using LDPC codes as a coding strategy is taken as an example, and a specific implementation of generating soft information required by a soft decoder through a hard decoder is described. Commonly used ECC coding schemes include LDPC (Low Density Parity Check) Code, BCH Code, BTC (Block Turbo Code), CTC (Convolutional Turbo Code), and the like. According to different correction requirements, a proper ECC coding strategy can be configured, and an appropriate ECC codec can be designed. The LDPC code becomes the most advanced coding strategy of the SSD controller at present with excellent performance, and the performance thereof is close to the shannon limit (the shannon limit of a channel or shannon capacity refers to the maximum transmission rate of error-free transmission on a channel with random error occurrence). In the hardware of the ECC decoding module layout shown in the left side of fig. 3, when the LDPC coding strategy is adopted, the soft decoder needs to continuously perform multiple read operations on the storage device through the interactive interface in the related art to sample the voltage value with the required fine granularity, so as to generate the soft information required for the soft decoding. In the embodiment of the present specification, when the soft information is generated by the hard decoder, the hard decoder may transmit the soft information including the hard decoding result to the soft decoder at one time through the interactive interface, and the soft decoder further performs error correction decoding on the basis of the hard decoding result through the soft information generated by the hard decoder, at this time, the soft decoder may complete decoding depending on the soft information generated by the hard decoder, and the soft decoder does not need to sample the storage device, thereby avoiding multiple reads of the storage device by the soft decoder, and relieving data congestion of the interactive interface.
When the above embodiment is applied to the ECC decoding module shown in the right side of fig. 2, since the soft decoder is located in the storage device, the data transmitted between the soft decoder, the hard decoder, and the nonvolatile memory does not need to pass through the interactive interface between the storage device and the controller, and only the final decoding result needs to be sent to the controller through the interactive interface for the next operation. The scheme can also relieve the data congestion of the interactive interface.
The decoding algorithm of the LDPC code is divided into a hard decision algorithm and a soft decision algorithm, wherein the hard decision algorithm is mainly BF (bit flipping) algorithm, and the principle is as follows: when the check equation is not satisfied, it indicates that at this time, an error must occur in a bit, and the probability of the error occurring in the bit that does not satisfy the maximum number of check equations among all the bits that may occur in error is the largest. And at each iteration, the bit with the maximum error probability is turned over and the updated code word is used for decoding again. Hard decision algorithms are easily implemented in hardware.
The soft decision algorithm mainly includes a BP (Belief Propagation) algorithm and a series of algorithms for improving the BP algorithm, such as an LLR-BP (Logarithm Likelihood Ratio-Belief Propagation) algorithm. The LLR-BP algorithm is a simplified algorithm of the BP algorithm, and reduces hardware resources and calculation time through a log-likelihood ratio.
For example, if the check matrix H is used for correction as shown in formula (1), the corresponding Tanner graph connection information is shown in fig. 8. In the Tanner graph, variable nodes correspond to columns of an LDPC code check matrix H, check nodes correspond to rows in the LDPC code check matrix H, and non-zero elements of the LDPC code check matrix H correspond to connecting lines in the Tanner graph. In the check matrix H, the column weight refers to the number of non-zero elements in each column, the row weight refers to the number of non-zero elements in each row, and the regular LDPC code is a code with all equal column weights and row weights; if not, it is called an irregular LDPC code. In FIG. 8, there are 5 check nodes, each with C1～C5It is shown that there are 10 variable nodes, each of which is B1～B10And (4) showing.
Assume that the encoded vector is
Then transmitted through the channel, and the vector transmitted by the channel received by the decoder is
All variable nodesB i Receiving corresponding received valuey i . The vector C and the check matrix H must satisfy the system of linear equations
. Received vectorYMay contain errors resulting in
。
Whether the BP algorithm or the LLR-BP algorithm is improved, the iterative process can be described as:
the first iteration: each variable node transmits a reliability message to all the check nodes adjacent to the variable node, and the reliability message is a value transmitted by a channel; each check node receives the reliability information transmitted by the variable node and then processes the reliability information, and then returns a new reliability information to the adjacent variable node, thereby completing the first iteration; and judging, if the check equation is satisfied, directly outputting a judgment result without iteration, and otherwise, performing second iteration.
And (3) second iteration: and each variable node processes the reliability message transmitted by the check node when the first iteration is completed, and sends a new message to the check node after the processing is completed. And after the decoding is finished, judging the decoding, if the check equation is met, ending the decoding, otherwise, repeating the iteration for multiple times, and judging each time until the set maximum trial times are reached, wherein the decoding fails. In each iteration process, no matter the information transmitted to the check node by the variable node or the information transmitted to the variable node by the check node, the information transmitted to the sender by the receiver in the previous iteration should not be included, so as to ensure that the transmitted information is opposite to the information obtained by the receiver node.
Based on the above iterative process, the basic steps of the BP decoding algorithm are as follows:
firstly, calculating the initial probability of each variable node after channel transmissionp i (1) Andp i (0) then, for each variable node, the confidence information passed to its neighboring check nodes is obtained, as shown in the following formula (2):
where the superscript indicates the number of iterations.
Second, processing check node to find the secondlCheck node in sub-iteration processiTo the variable nodes adjacent theretojThe confidence information of (2) is shown in the following formula (3):
thirdly, processing variable nodes and solving the variable nodes in the first iteration processjTo check nodes adjacent theretoiThe confidence information of (2) is shown in the following formula (4):
whereinK ij Is a correction factor, such that each time calculated
。
Fourthly, recalculating the confidence information of each variable node according to the information fed back by the check node, as shown in the following formula (5):
whereinK j Is also a correction factor, such that each time calculated
。
And step five, decoding and judging: if it is not
Then the code value at this point is decided to be 1; otherwise, the code value at this point is judged.
Compared with the BP algorithm, the reliability information transmitted in the LLR-BP decoding algorithm is not probability information any more but likelihood probability information, and the basic decoding steps of the LLR-BP decoding algorithm are as follows:
firstly, adopting initialization means, the variable node receives channel transmission information, whereiny n In order to receive the data, the data is transmitted,σgiven by the channel characteristics, as shown in equation (6) below.
Second, updating check node information in horizontal direction, namely finding check node informationHFor each point of the matrix other than 0, the corresponding information is calculated, and the following formula (7) can be referred to as the calculation formula:
thirdly, in the vertical direction, variable node information is updated, namely, variable node information is foundHFor each row of the matrix, the corresponding information is calculated for the point not equal to 0, and the following formula (8) can be referred to:
fourthly, updating the posterior probability, namely updating each value of the received signal for subsequent decision, wherein the calculation formula can refer to the following formula (9):
fifthly, decoding judgment is carried out, each bit of the received signal is judged according to the updated log likelihood ratio information, and if the result is greater than 0, the result is judged to be 0; otherwise, the result is judged to be 1.
The conditions for finishing iteration of the BP decoding algorithm and the LLR-BP decoding algorithm are as follows: vector generated after decodingXSatisfy the requirement of
(ii) a Or the maximum number of attempts has been reached, and in case both conditions are met, the result of the decision is takenXAnd outputting, and if the two conditions are not met, continuing the steps II, III and IV.
Assume that the encoded original data is
The original data satisfy
. Wherein the check matrixHNamely the matrix described in formula (1), the Tanner graph corresponding to the matrix is shown in fig. 8, and the check matrixHIs stored in the code parity check matrix 702 of the hard decoder as shown in fig. 7. Vector of raw dataCAfter transmission, an error occurs, and the data to be decoded including the error is set as
. The vector to be decoded is first hard decoded using a hard decoder as described in fig. 7. The correction selector 704 is based on the check matrixHAnd the vector to be decodedY 1And generating a syndrome. And generating confidence information according to the check nodes which do not meet the connection information of the Tanner graph in the syndrome and the relation between the variable nodes and the check nodes, and sequencing the variable nodes according to the confidence. And selecting the variable node with the lowest confidence coefficient (namely, the highest possibility of errors) for flipping, and flipping the corresponding bit in the data to be decoded corresponding to the variable node in the read buffer. This forms one attempt of hard decoding. The modified data vector to be decoded is used to calculate a new syndrome, which is further analyzed to select the bits to be flipped, and the above steps are repeated until the generated vector satisfies
The decoding of the hard decoder is successful; alternatively, the iteration reaches a maximum number of attempts and the hard decoder fails decoding.
Suppose thatmOn the other hand, the vector generated is
And is and
whereinmThe maximum number of attempts of the hard decoder, and at this time, it is judged that the hard decoder fails in error correction decoding. Since the hard decoder cannot complete the full decoding of the data to be decoded, requiring the soft decoder to further decode the results, the correction selector 704 in the hard decoder needs to generate identification information containing the soft information required by the soft decoder.
On the basis of the error correction decoding failure of the hard decoder, in an exemplary embodiment, assuming that the decoding algorithm of the soft decoder is the BP algorithm, the soft information required by the soft decoder when decoding is confidence information. The confidence information generated by the correction selector 704 is assumed to be due to a hard decoder decoding failure
Where the superscript (0) indicates that the number of iterations of the soft decoder is 0. The hard decoder sends the confidence information to the soft decoder. Since the initial confidence information is provided by the hard decoder, the soft decoder may not need to read the data information located in the storage device, as described above with respect to the BP decoding algorithm steps, the first step, the initialization step, of the BP decoding algorithm will be to generate the above-described confidence information by the hard decoder
Instead of the calculation result in equation 2, as the initial probability in the soft decoding step, the subsequent decoding step is performed. For example, assume the raw data
Confidence information generated by a hard decoder
The confidence information is brought into the initial probability, and the confidence information of each variable node after the soft decoder is iterated once through the steps of two, three and four
On the basis of (1), update to
Decoding judgment is carried out on the updated confidence coefficient information, if the probability value of the confidence coefficient information of a certain bit
Then the code value at this point is decided to be 1; otherwise, the code value at this point is 0. Assume that the updated confidence information is
And performing decoding judgment on the probability information to obtain the following first iteration decoding result
. Due to the fact that
If so, it indicates that the iteration is not successful, and since the maximum number of attempts for soft decoding is not reached, two to five steps of the BP decoding step need to be repeated until the decoding result satisfies the requirement
Or is orThe number of iterations exceeds the maximum number of attempts and the soft decoding fails.
In another exemplary embodiment, the decoding algorithm of the soft decoder is an LLR-BP algorithm, and the soft information required for decoding by the soft decoder is log-likelihood ratio information. The correction selector 704 in the hard decoder needs to generate the soft information needed by the soft decoder due to the hard decoder decoding failure. In this example, the soft decoder decoding algorithm is the LLR-BP algorithm, so the soft information generated by the correction selector 704 is the log-likelihood ratio information, which is assumed to be
. The hard decoder sends the log-likelihood ratio information to the soft decoder. Similar to the soft decoder using the BP decoding algorithm, the initialization information calculated according to equation 6 is used with log likelihood ratio information generated by the hard decoder
Instead, the subsequent steps are continued. In that
The iteration is performed on the basis. The iterative process is similar to that of soft decoding using the BP decoding algorithm.
For example, assume the raw data
Initial log-likelihood ratio information for soft decoder iterations is generated by hard decoding
Soft decoder in
On the basis of the above-mentioned algorithm, the second, third and fourth steps of LLR-BP decoding algorithm are repeatedxAfter the iteration, the log likelihood ratio information of each variable node is updated to
When decoding judgment is performed on the log-likelihood ratio information, a decoding result corresponding to the log-likelihood ratio information is found
Satisfy the requirement of
If so, the soft decoding is judged to be successful, and the soft decoding result is the vector
。
For example, viaxAfter the iteration, the log likelihood ratio information of each variable node is updated to
Performing a decoding step according to the decision on the log-likelihood ratio information if the first step isiLog likelihood ratio of bits
If yes, the bit is judged to be 0; otherwise, the result is 1, and the following result is obtainedxSub-iterative decoding results
At this time, satisfy
Therefore, the soft decoding is successful, and the soft decoding result is
。
Both of the above exemplary embodiments enable the generation of soft information by the hard decoder that is required for soft decoder decoding. When the hard decoder fails in error correction decoding, the correction selector 704 in the hard decoder performs not only a selection check function in the decoding process of the hard decoder but also a function of generating soft information required for the soft decoder. In an exemplary embodiment of the present specification, when the hard decoder is transferred from the controller to the storage device and the soft decoder is retained in the controller, the soft information may be included in the identification information and transmitted to the soft decoder through an interactive interface on the controller, and the soft decoder performs further soft decoding based on the hard decoding result.
A CRC (Cyclic Redundancy Check) system may also be included in the controller and may be used to implement a CRC Check. CRC checking is a channel coding technique that generates a short fixed bit check code based on data such as network packets or computer files, and is used primarily to detect or check errors that may occur after data transmission or storage. For example, CRC systems may utilize the principles of division and remainder to achieve error detection. After decoding is completed, the soft decoder can send the decoded code word to the CRC system for checking to detect whether the data decoded by the soft decoder still has errors.
In one embodiment of the present specification, the hard decoder may manage the state of the hard decoder through a state machine, and perform corresponding operations accordingly. For example, when the state machine is in the first state, indicating that data needs to be read from the memory device and decoded, the hard decoder reads the data buffered in the page buffer and begins decoding. For another example, when the state machine is in the second state, indicating that the hard decoder successfully decodes, the hard decoder stops decoding, and sends a decoding result of successful error correction decoding to the subsequent processing device. And when the state machine is in the third state, the decoding failure of the hard decoder is indicated, the hard decoder stops decoding and generates soft information required by the soft decoder, and the soft information containing the hard decoding result is sent to the soft decoder for further decoding.
Fig. 9 shows a process of transferring soft information from a hard decoder 1301 in a storage device to a soft decoder 1302 in a controller for an exemplary embodiment of the specification. Since the soft information is already generated by the hard decoder 1301, the soft information does not need to be generated by the soft decoder 1302 through the soft information generation module 921, and time for the soft information generation module 921 to read and sample the nonvolatile memory of the storage device multiple times in order to obtain the soft information can be saved. In some cases, the soft decoder 1302 may not even include the soft information generation module 921, thereby saving the design overhead of the soft decoder 1302 and reducing the space occupied by the soft decoder 1302 in the controller 21. Through the interactive interface, the hard decoder 1301 may send the generated soft information containing the hard decoding result to the soft decoder 1302, where the error is further reduced by iterative decoding of the soft decoder 1302. The presence of hard decoder 1301 may relieve the burden on soft decoder 1302 to some extent, thereby speeding up overall decoding speed.
The memory device may integrate multiple decoders, which may operate in parallel. For example on top of a 3D flash memory, multiple decoders may be integrated simultaneously. Compared with the case of integrating only one decoder, under the condition that the total data volume is not changed, the parallel integration of the plurality of decoders can convert the serial decoding task of the original single decoder into the parallel processing of the plurality of decoders, so that the decoding task shared by each decoder is less, the plurality of decoders can simultaneously decode, the time consumed by decoding can be saved, and the decoding efficiency is improved.
Furthermore, if the hard decoders are transferred to the storage device for implementation, and the soft decoders remain in the controller, the number of hard decoders may also be increased in the storage device, the hard decoders also working in parallel. For example, a plurality of hard decoders are integrated on the top of a 3D flash memory, and in this case, due to parallel work, each hard decoder shares fewer decoding tasks, so that the maximum number of attempts of each hard decoder can be increased on the basis of increasing the number of hard decoders, so as to perform more rounds of iteration, which is equivalent to allocating more time to decode each read result than before, so as to improve the error correction decoding capability, and on the basis of improving the decoding capability of the hard decoder, the probability of successful decoding of data to be decoded by the hard decoder increases, thereby relieving the decoding pressure of the soft decoder.
In one or more embodiments of the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The terminology used in the description of the one or more embodiments is for the purpose of describing the particular embodiments only and is not intended to be limiting of the description of the one or more embodiments. As used in one or more embodiments of the present specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in one or more embodiments of the present description to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of one or more embodiments herein. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
The above description is only for the purpose of illustrating the preferred embodiments of the one or more embodiments of the present disclosure, and is not intended to limit the scope of the one or more embodiments of the present disclosure, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the one or more embodiments of the present disclosure should be included in the scope of the one or more embodiments of the present disclosure.
Claims (9)
1. A memory device, comprising:
a non-volatile memory, and peripheral circuitry adapted to the non-volatile memory;
the decoder is electrically connected with the peripheral circuit and is used for reading target data from the nonvolatile memory through the peripheral circuit and carrying out error correction decoding on the target data;
under the condition that the decoder is a hard decoder, an interactive interface is arranged between the storage device and a controller in the storage equipment to which the storage device belongs, and the controller comprises a soft decoder; the hard decoder is further to:
and under the condition of failure of error correction decoding, generating soft information required by the soft decoder, and sending the soft information to the soft decoder through the interactive interface so that the soft decoder performs error correction decoding on the target data which is original or processed by the hard decoder through the soft information.
2. The apparatus of claim 1, wherein the peripheral circuit comprises:
a page buffer electrically connected to the non-volatile memory for buffering data read from the non-volatile memory;
wherein the decoder is electrically connected to the page buffer, and reads the cached target data from the page buffer.
3. The apparatus of claim 1, wherein the peripheral circuit comprises:
the page buffer is electrically connected with the nonvolatile memory and is used for caching the data to be decoded read from the nonvolatile memory;
an extension buffer electrically connected to the page buffer for buffering data read from the page buffer;
wherein the decoder is electrically connected to the extension buffer and reads the buffered target data from the extension buffer.
4. The apparatus of claim 1, wherein the decoder is a hard decoder and/or a soft decoder.
5. The apparatus of claim 4, wherein the hard decoder has a state machine built therein, the state machine managing state information of the hard decoder according to the performed operation of the hard decoder, the state information indicating a subsequent performed operation of the hard decoder.
6. The apparatus of claim 4, wherein the hard decoder comprises:
a descrambling module, configured to descramble the target data;
a hard decoding module, configured to perform error correction decoding on the descrambled target data.
7. The apparatus of claim 1, wherein the peripheral circuitry is vertically integrated in a first region of a top surface of the non-volatile memory, and the decoder is vertically integrated in a second region of the top surface of the non-volatile memory.
8. The apparatus of claim 1, wherein the non-volatile memory is a 3D flash memory.
9. A storage device, comprising:
a controller, and a storage device as claimed in any one of claims 1 to 8.
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