CN113782605A - Semiconductor device, manufacturing method thereof and electronic equipment - Google Patents

Semiconductor device, manufacturing method thereof and electronic equipment Download PDF

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Publication number
CN113782605A
CN113782605A CN202010526119.8A CN202010526119A CN113782605A CN 113782605 A CN113782605 A CN 113782605A CN 202010526119 A CN202010526119 A CN 202010526119A CN 113782605 A CN113782605 A CN 113782605A
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Prior art keywords
gate
peripheral
grid
semiconductor device
etching
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Inventor
郭炳容
杨涛
李俊峰
王文武
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Priority to CN202010526119.8A priority Critical patent/CN113782605A/en
Publication of CN113782605A publication Critical patent/CN113782605A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductor manufacturing, wherein the semiconductor device is used for controlling the resistance value of a gate electrode, inhibiting the generation of leakage current and improving the refreshing performance of the semiconductor device. The semiconductor device comprises a substrate and a gate stack embedded in the substrate, wherein a gate electrode of the gate stack comprises an upper gate, a lower gate and a peripheral gate. The upper grid is of an inverted U-shaped structure, the peripheral grid is of a U-shaped structure, the upper grid covers the top surface and the upper parts of the side surfaces of the lower grid, and the peripheral grid covers the bottom surface and the lower parts of the side surfaces of the lower grid. The bottom surface of the upper grid is connected with the top surface of the peripheral grid. The invention also provides a manufacturing method for manufacturing the semiconductor device. The semiconductor device provided by the invention is applied to electronic equipment.

Description

Semiconductor device, manufacturing method thereof and electronic equipment
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the same, and an electronic device.
Background
A buried trench semiconductor device (BCAT) is a semiconductor device in which a gate stack (word line) is buried in a substrate. Such a semiconductor device has a relatively high integration level and is widely used in an integrated circuit.
In the manufacturing process of the buried channel type semiconductor device, a trench needs to be opened downwards from the surface of a substrate, and a gate stack is formed in the trench. Since the integration of the buried channel semiconductor device is high, the distance between the gate stack and the contact node is short, which may cause a problem of leakage current, thereby affecting the refresh characteristics of the semiconductor device.
Disclosure of Invention
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein a gate electrode is formed by a lower gate, an upper gate with a U-shaped structure and a peripheral gate with a U-shaped structure, and the generation of leakage current is inhibited by changing the resistance value of the gate electrode so as to improve the refreshing performance of the semiconductor device.
In order to achieve the above object, the present invention provides a semiconductor device including a substrate and a gate stack embedded in the substrate, a gate electrode of the gate stack including an upper gate, a lower gate and a peripheral gate; the upper grid is of an inverted U-shaped structure, the peripheral grid is of a U-shaped structure, the upper grid covers the top surface and the upper parts of the side surfaces of the lower grid, and the peripheral grid covers the bottom surface and the lower parts of the side surfaces of the lower grid; the bottom surface of the upper grid is connected with the top surface of the peripheral grid.
Compared with the prior art, the semiconductor device provided by the invention has the advantages that the gate electrode is formed by the lower gate, the n-shaped upper gate and the U-shaped peripheral gate, and the resistance value of the gate electrode can be adjusted by forming the n-shaped upper gate on the lower gate. That is, the gate electrode having the resistance value can satisfy not only conductivity but also a strong gate control capability to effectively suppress generation of leakage current and improve refresh performance of the semiconductor device.
In addition, when forming the n-shaped upper gate on the lower gate, the peripheral gate needs to be etched back, so that in practical application, the distance from the peripheral gate to the contact node formed in the substrate on one side of the gate stack can be increased, and at this time, the generation of leakage current can be suppressed, and the refresh performance of the semiconductor device can be improved.
Furthermore, when the n-shaped upper gate is formed on the lower gate, only the peripheral gate needs to be etched back, and the lower gate does not need to be etched back, that is, the height of the lower gate does not become small, and accordingly, the resistance of the lower gate does not become small, and at this time, the generation of leakage current can be suppressed, so as to improve the refresh performance of the semiconductor device.
The present invention also provides a method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a gate stack in an embedded manner in a substrate, a gate electrode of the gate stack including an upper gate, a lower gate and a peripheral gate; the upper grid is of an inverted U-shaped structure, the peripheral grid is of a U-shaped structure, the upper grid covers the top surface and the upper parts of the side surfaces of the lower grid, and the peripheral grid covers the bottom surface and the lower parts of the side surfaces of the lower grid; the bottom surface of the upper grid is connected with the top surface of the peripheral grid.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as those of the semiconductor device in the technical scheme, and the details are not repeated herein.
The invention also provides electronic equipment comprising the semiconductor device provided by the invention.
Compared with the prior art, the electronic device provided by the invention has the same beneficial effects as the semiconductor device in the technical scheme, and the detailed description is omitted.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art semiconductor device;
FIG. 2 is a schematic diagram of another prior art semiconductor device;
fig. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure after forming a trench on a substrate according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram illustrating an insulating layer and a barrier layer formed in a trench according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram after forming a lower gate according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram after etching back according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram after forming an upper gate according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram after forming a cap pattern and a contact node according to an embodiment of the present invention.
Wherein: 10. a substrate, 11, a trench, 12, a gate stack, 120, an insulating layer, 121, a peripheral gate, 122, a metal gate, 13, a contact node, 14, a cap pattern; 15, doped polysilicon of I-shaped structure
20. Substrate, 21. gate stack, 210. gate electrode, 2100. lower gate, 2101. upper gate, 2102. peripheral gate, 22. contact node, 23. trench, 211. insulating layer, 2110. recess, 24. cap pattern;
H. and (4) height difference.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Various schematic diagrams of embodiments of the invention are shown in the drawings, which are not drawn to scale. Wherein certain details are exaggerated and possibly omitted for clarity of understanding. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In addition, in the present invention, directional terms such as "upper" and "lower" are defined with respect to a schematically placed orientation of components in the drawings, and it is to be understood that these directional terms are relative concepts, which are used for relative description and clarification, and may be changed accordingly according to the change of the orientation in which the components are placed in the drawings.
In the present invention, unless expressly stated or limited otherwise, the term "coupled" is to be interpreted broadly, e.g., "coupled" may be fixedly coupled, detachably coupled, or integrally formed; may be directly connected or indirectly connected through an intermediate.
Fig. 1 shows a schematic structural diagram of a semiconductor device in the prior art. As shown in fig. 1, the semiconductor device is a buried channel type semiconductor device, and includes a substrate 10, a trench 11 formed downward from a surface of the substrate 10, and a gate stack 12 formed in the trench 11. It should be understood that the gate stack 12 here is actually a word line in a buried channel semiconductor device, and a contact node 13 is formed in the substrate at one side of the trench 11, which contact node 13 may be a storage contact node or a bit line contact node.
The gate stack 12 includes an insulating layer 120 and a gate electrode, which may include a peripheral gate 121 and a metal gate 122. Wherein the insulating layer 120 is formed on the inner sidewall and the bottom wall of the trench 11. The peripheral gate 121 is formed on the inner sidewall and the bottom wall of the insulating layer 120. The metal gate 122 is formed in a space surrounded by the inner sidewall and the inner bottom wall of the peripheral gate 121. It is to be understood that the gate stack 12 is generally formed at a lower portion of the trench 11, and after the gate stack 12 is formed, an insulating material such as silicon dioxide is filled in the trench 11 above the gate stack 12 to form the cap pattern 14.
As a result of analyzing the structure of the semiconductor device, it is found that the distance between the contact node 13 and the gate electrode becomes shorter as the number of transistors integrated on the substrate 10 becomes larger, and even if the outer sidewall of the gate electrode is provided with the insulating layer 120, the insulating layer 120 becomes thinner as the degree of integration becomes higher. In other words, the distance between the contact node 13 and the gate electrode in the semiconductor device becomes short, and the insulating layer 120 separating the contact node 13 and the gate electrode becomes thin, and therefore, a problem of leakage current may be caused.
In view of the above technical problems, the prior art proposes another semiconductor device. Fig. 2 is a schematic diagram of another semiconductor device in the prior art. As shown in fig. 2, a doped polysilicon 15 of a line structure is added between the cap pattern 14 and the gate stack 12, as compared to the structure of the semiconductor device described in fig. 1. At this time, the gate electrode can be separated from the contact node 13 by the doped polysilicon 15 of the in-line structure, and generation of a leakage current can be suppressed to some extent. However, in practical applications, it has been found that when the gate electrode is turned on, the in-line structure of the doped polysilicon 15 carriers diffuses into the active region more easily than the peripheral gate 121 and the metal gate 122, which may cause short-circuiting between conductors.
In view of the above technical problems, embodiments of the present invention provide a semiconductor device. Fig. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. As shown in fig. 3, the semiconductor device includes a substrate 20 and a gate stack 21 embedded in the substrate 20, a gate electrode 210 of the gate stack 21 includes a lower gate 2100, an upper gate 2101, and a peripheral gate 2102, the upper gate 2101 is n-shaped, the peripheral gate 2102 is U-shaped, the upper gate 2101 covers the upper portion of the top surface and the side surface of the lower gate 2100, and the peripheral gate 2102 covers the lower portion of the bottom surface and the side surface of the lower gate 2100. The bottom surface of the upper gate 2101 meets the top surface of the peripheral gate 2102.
The above substrate 20 may be a bulk Silicon substrate, a Silicon-On-Insulator (SOI) substrate, a Germanium-On-Insulator (GOI) substrate, a Silicon Germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG).
In practical applications, the trench 23 may be formed downward from the surface of the substrate 20, and the gate stack 21 is formed in the trench 23, and may be formed in a lower portion of the trench 23.
The gate stack 21 may include an insulating layer 211, the insulating layer 211 is formed on the sidewall and the bottom wall of the trench 23, and the height of the insulating layer 211 formed on the sidewall of the trench 23 may be identical to or slightly higher than the height of the gate electrode 210. The insulating layer 211 may be a silicon oxide layer, a thermal oxide layer, a high-k dielectric layer, or the like. The insulating layer 211 may separate the gate electrode 210 from the substrate 20 to prevent carriers of the gate electrode 210 from diffusing into the substrate 20.
After the insulating layer 211 is formed, a peripheral gate 2102 is formed on the sidewall and the bottom wall of the insulating layer 211, and the top surface of the peripheral gate 2102 formed on the sidewall of the insulating layer 211 may be flush with, slightly higher than, or slightly lower than the top surface of the insulating layer 211. The peripheral gate electrode 2102 is an ion diffusion barrier layer of the electrode 210. The peripheral gate 2102 may be titanium nitride or tungsten nitride, but is not limited thereto.
After the peripheral gate 2102 is formed, a lower gate 2100 is formed in a space formed by the peripheral gate 2102, and the lower gate 2100 fills the space formed by the peripheral gate 2101. The top surface of the lower gate 2100 may be formed to be flush with or slightly higher than the top surface of the peripheral gate 2102. The bottom gate 2100 may be tungsten, but is not limited thereto.
After bottom gate 2100 is formed, peripheral gate 2102 is etched back such that the top surface of peripheral gate 2102 is lower than the top surface of bottom gate 2100.
The upper gate 2101 is formed on the outer side surface of the lower gate 2100 and the top surface of the peripheral gate 2102. That is, the n-shaped upper gate 2101 is formed. The upper gate 2101 may be doped with polysilicon, but is not limited thereto.
Compared with the gate electrode formed by only the lower gate and the peripheral gate in the prior art, the gate electrode 210 formed by the lower gate 2100, the upper gate 2101 and the peripheral electrode 2109 has the advantages that the resistance value of the gate electrode 210 can be adjusted by the upper gate 2101, the gate control energy of the gate electrode 210 with the resistance value is strong, the generation of leakage current can be inhibited, and the refreshing performance of the semiconductor device is improved.
Since the peripheral gate 2102 needs to be back-etched before the upper gate 2101 of the ═ n-shaped structure is formed, the distance H between the top surface of the back-etched peripheral gate 2102 and the contact node 22 formed at one side of the gate stack 21 is increased, and the increase of H is advantageous for suppressing the generation of a leakage current to improve the refresh performance of the semiconductor device. As an example, H may be 15 to 25 nm, in practical applications, for example, greater than at least 5 nm, compared to the distance between the in-line structure doped polysilicon 15 (see fig. 2 in particular) and the contact node 13.
Furthermore, before forming the n-shaped upper gate 2101, only the peripheral gate 2102 is etched back, and the lower gate 2100 is not etched back. That is, the volume of the lower gate 2100 is not reduced, and it is understood that the cross-sectional area of the lower gate 2100 is a certain value. At this time, the height of the bottom gate 2100 is not reduced, and the resistance of the bottom gate is not lowered. Therefore, the lower gate 2100 having a resistance not lowered can also suppress generation of a leakage current to improve the refresh performance of the semiconductor device.
In addition, only the peripheral gate 2102 is etched back before the n-shaped upper gate 2101 is formed, but the lower gate 2100 is not etched back, so that the uniformity of the top surface of the peripheral gate 2102 after etching back can be ensured, and at this time, the uniformity of the contact between the n-shaped upper gate 2101 and the peripheral gate 2102 can be ensured, thereby further inhibiting the generation of leakage current and improving the refresh performance of the semiconductor device.
The upper gate 2101 of the n-shaped structure may completely surround the upper portion of the lower gate 2100, that is, the upper gate 2101 of the n-shaped structure may isolate the lower gate 2100 from the contact node 22. It is to be understood that the conductive property of the upper gate 2101 is weaker than that of the lower gate 2100, and at this time, the generation of a leakage current can also be suppressed to improve the refresh performance of the semiconductor device.
The n-shaped upper gate 2101 is relatively thinner than the n-shaped upper gate in the prior art, and the carriers of the n-shaped upper gate 2101 are relatively less prone to diffuse into the active region, thereby avoiding short circuit between conductors. As an example, the thickness of the upper gate 2101 of the n-shaped structure is 10 to 100 nm.
After forming the gate stack 21 in the trench 23 described above, a cap pattern 24 may also be formed in the trench 23 above the gate stack 21.
In the process of etching back the peripheral gate 2102, a groove 2110 may be further formed in the inner side wall of the insulating layer 211, and the upper gate 2101 is clamped in the groove 2110, so that the contact tightness between the upper gate 2101 and the insulating layer 211 is enhanced, the gate control capability of the gate electrode 210 is improved, and generation of leakage current is suppressed.
An embodiment of the present invention further provides a method for manufacturing a semiconductor device, and fig. 4 is a flowchart illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention. As shown in fig. 4, the method for manufacturing a semiconductor device includes:
s10, providing a substrate. It is to be understood that the substrate may be a bulk Silicon substrate, a Silicon-On-Insulator (abbreviated as SOI) substrate, a Germanium-On-Insulator (abbreviated as GOI) substrate, a Silicon Germanium substrate, a group III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective epitaxial growth (abbreviated as SEG).
S11, forming a gate stack in the substrate in an embedded mode, wherein the gate electrode of the gate stack comprises an upper gate, a lower gate and a peripheral gate; the upper grid is of an inverted U-shaped structure, the peripheral grid is of a U-shaped structure, the upper grid covers the top surface and the upper parts of the side surfaces of the lower grid, and the peripheral grid covers the bottom surface and the lower parts of the side surfaces of the lower grid; the bottom surface of the upper grid is connected with the top surface of the peripheral grid.
The manufacturing method of the semiconductor device provided by the embodiment of the invention has the same technical effects as the semiconductor device provided by the embodiment of the invention, and details are not repeated herein.
For ease of understanding, a specific example of a method of fabricating a semiconductor device is provided below, it being understood that the following example is for explanation only and not for limitation.
Referring to fig. 5, a substrate 20 is provided, and trenches 23 are formed from the surface of the substrate 20 down. It should be understood that in order to ensure the gating stability of the gate stack 21 formed in the trench 23, the variation in width per unit of the notch to the bottom of the trench 23 is substantially equal to 0.
Referring to fig. 6, an insulating layer 211 may be formed on the inner sidewall and the bottom wall of the trench 23. The top surface of insulating layer 211 may be flush with the notch of trench 23 or slightly below the notch of trench 23.
Referring to fig. 6, a peripheral gate 2102 is formed in the trench 23, and the peripheral gate 2102 has an open hollow structure, that is, the peripheral gate 2102 may be formed on inner sidewalls of a groove bottom and a lower portion of the trench 23. The process of forming the peripheral gate 2102 may be, but is not limited to, an electroplating and/or deposition process. After the peripheral gate 2102 is formed, annealing, chemical mechanical planarization, or the like may be performed.
Referring to fig. 7, a lower gate 2100 is formed in a hollow portion of a peripheral gate 2102 through an opening of the peripheral gate 2102. The top surface of the preliminarily formed lower gate 2100 may be higher than the top surface of the peripheral gate 2102, or the top surface of the peripheral gate 2102 may be covered. At this time, a chemical mechanical planarization process may be employed such that the top surface of the lower gate 2100 is flush with the top surface of the peripheral gate 2102. It is to be understood that after the lower gate 2100 is formed, an annealing process may be performed.
Referring to fig. 8, peripheral gate 2102 is etched back so that the top surface of lower gate 2100 is exposed from peripheral gate 2102. A wet or dry etch process may be used to etch back peripheral gate 2102.
As an example: when the bottom gate 2100 is tungsten, the top gate 2101 is doped polysilicon, and the peripheral gate 2102 is tungsten nitride or titanium nitride. Only the peripheral gate 2102 is etched back by wet etching without etching backIn the case of tungsten, an etching solution having a high selectivity to tungsten may be used. For example, it may be H2O2Etching solution, H2O2The volume ratio of the etching solution may be 1% to 37%, and the etching temperature may be 25 ℃ to 100 ℃, where the etching temperature is actually the temperature of the etching solution.
As another example: when the bottom gate 2100 is tungsten, the top gate 2101 is doped polysilicon, and the peripheral gate 2102 is tungsten nitride or titanium nitride. Etching back only the peripheral gate 2102 without etching back tungsten using, for example, a plasma dry etch with NF as an etching gas3He and H2The RF electric field applied in the chamber is 100W to 300W to plasmatize the etching gas and etch back the peripheral gate 2102 with the plasma. During the etching process, the temperature in the chamber is maintained at 100 ℃ to 300 ℃. Because of the high selectivity of the etching gas to tungsten, only the peripheral gate 2102 is etched back, and the lower gate 2100 is not etched back.
It should be further explained that a small amount of bottom gate 2100 can be etched back at the same time or subsequently during etching back of peripheral gate 2102 or after etching back of peripheral gate 2102, so as to ensure the contact tightness between top gate 2101 and bottom gate 2100 subsequently deposited on the side of bottom gate 2100. And the inner sidewall of the insulating layer 211 may also be etched using wet etching or dry etching to form the groove 2110. The upper gate 2101 may be stuck in the groove 2110 upon a subsequent formation of the upper gate.
Referring to fig. 9, an upper gate 2101 is formed on a lower gate 2100. At this time, the bottom surface of the upper gate 2101 is engaged with the top surface of the peripheral gate 2102, and the top surface and the side surface of the upper gate 2101 enclose the exposed portion of the lower gate 2100.
As an example: an upper gate 2101 is formed on the lower gate 2100 using a deposition process. When the upper gate 2101 is formed of doped polysilicon, the following process may be employed:
an amorphous silicon layer is first deposited on the lower gate 2100, and the temperature during the deposition is controlled to 400 to 530 c and the pressure is controlled to 10 mtorr to 10 torr. After depositing to form amorphous silicon layer, doping arsenic and boron to make the doped amorphous silicon layerIs N-type. Using SiH4Or Si2H6The doped amorphous silicon layer is converted into doped polysilicon, the temperature of the stage is controlled to be 100-450 ℃, and the time can be about 5 minutes.
As a possible implementation manner, after the gate stack 21 is formed on the substrate 20, the method for manufacturing the semiconductor device further includes:
referring to fig. 10, a cap pattern 24 is formed within the trench 23 and over the gate stack 21. At least one contact node 22 is formed in the substrate 20, and a height difference H between a bottom surface of the contact node 22 and a top surface of the barrier layer 2102 is within a second predetermined range.
The embodiment of the invention also provides electronic equipment which comprises the semiconductor device provided by the embodiment of the invention. The electronic device may be a communication device or a terminal device, etc., but is not limited thereto. Further, the terminal device comprises a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligence device, a mobile power supply and the like. The communication device includes a base station and the like, but is not limited thereto.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (16)

1. The semiconductor device is characterized by comprising a substrate and a gate stack embedded in the substrate, wherein a gate electrode of the gate stack comprises an upper gate, a lower gate and a peripheral gate; the upper grid is of an inverted U-shaped structure, the peripheral grid is of a U-shaped structure, the upper grid covers the top surface and the upper parts of the side surfaces of the lower grid, and the peripheral grid covers the bottom surface and the lower parts of the side surfaces of the lower grid; the bottom surface of the upper grid is connected with the top surface of the peripheral grid.
2. The semiconductor device of claim 1, wherein the lower gate is metal and the upper gate is doped polysilicon; the peripheral gate is made of titanium nitride or tungsten nitride.
3. The semiconductor device according to claim 1, wherein the lower gate is tungsten.
4. The semiconductor device of claim 1, wherein the gate stack is a word line and a cap pattern is formed on the upper gate.
5. The semiconductor device of claim 1, wherein the gate stack further comprises an insulating layer formed between the substrate and the gate electrode.
6. The semiconductor device according to claim 1, wherein the peripheral gate electrode is an ion diffusion barrier layer.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a gate stack in the substrate in an embedded manner, wherein a gate electrode of the gate stack comprises an upper gate, a lower gate and a peripheral gate; the upper grid is of an inverted U-shaped structure, the peripheral grid is of a U-shaped structure, the upper grid covers the top surface and the upper parts of the side surfaces of the lower grid, and the peripheral grid covers the bottom surface and the lower parts of the side surfaces of the lower grid; the bottom surface of the upper grid is connected with the top surface of the peripheral grid.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the forming a gate stack in an embedded manner in the substrate comprises:
etching the peripheral grid electrode to enable the upper surface of the peripheral grid electrode to be positioned below the upper surface of the lower grid electrode;
and forming the upper gate with an inverted U-shaped structure on the lower gate and the etched peripheral gate.
9. The method of manufacturing a semiconductor device according to claim 8, wherein after the forming of the upper gate of the ≈ shape structures on the lower gate and the etched peripheral gate, the method further comprises:
forming a cap pattern on the upper gate.
10. The method of manufacturing a semiconductor device according to claim 8, wherein the etching the peripheral gate includes:
and etching the peripheral grid by adopting a wet etching process.
11. The method of claim 10, wherein the peripheral gate is titanium nitride or tungsten nitride, and the etching the peripheral gate by the wet etching process comprises:
by means of H2O2Etching the peripheral grid electrode by using an etching solution; the temperature of the etching solution is 25-100 ℃; the volume concentration of the etching solution is 1-37%.
12. The method of manufacturing a semiconductor device according to claim 8, wherein the etching the peripheral gate includes:
and forming the peripheral grid by adopting a plasma dry etching process.
13. The method according to claim 12, wherein the peripheral gate is made of titanium nitride or tungsten nitride, and the dry etching the peripheral gate using plasma comprises:
providing a cavity for accommodating the substrate;
introducing etching gas into the cavity, wherein the etching gas is NF3He and H2The mixed gas of (3);
controlling the temperature in the cavity to be 100-300 ℃;
and providing a radio frequency electric field of 100W to 300W into the cavity, wherein the radio frequency electric field enables the etching gas to be in a plasma state so as to etch the peripheral grid.
14. The method for manufacturing a semiconductor device according to claim 8, wherein the upper gate is doped polysilicon; the upper gate forming a n-shaped structure on the lower gate and the etched peripheral gate includes:
forming an amorphous silicon layer on the lower grid and the etched peripheral grid; the temperature when the amorphous silicon layer is formed is 400 ℃ to 530 ℃, and the pressure when the amorphous silicon layer is formed is 10 mTorr to 10 Torr;
processing the amorphous silicon layer to form a doped amorphous silicon layer;
using SiH4Or Si2H6Processing the doped amorphous silicon layer to form doped polycrystalline silicon; the temperature for forming the doped polysilicon is 100 ℃ to 450 ℃, and the time for forming the doped polysilicon is less than or equal to 5 minutes.
15. An electronic device comprising the semiconductor device according to any one of claims 1 to 6.
16. The electronic device of claim 15, wherein the electronic device comprises a communication device or a terminal device.
CN202010526119.8A 2020-06-09 2020-06-09 Semiconductor device, manufacturing method thereof and electronic equipment Pending CN113782605A (en)

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US20080211057A1 (en) * 2007-01-04 2008-09-04 Samsung Electronics Co., Ltd. Semiconductor having buried word line cell structure and method of fabricating the same
US20100213541A1 (en) * 2009-02-24 2010-08-26 Samsung Electronics Co., Ltd. Semiconductor device having recess channel structure
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