CN113782581A - Display panel, manufacturing method thereof and display device - Google Patents
Display panel, manufacturing method thereof and display device Download PDFInfo
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- CN113782581A CN113782581A CN202111122015.1A CN202111122015A CN113782581A CN 113782581 A CN113782581 A CN 113782581A CN 202111122015 A CN202111122015 A CN 202111122015A CN 113782581 A CN113782581 A CN 113782581A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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- G—PHYSICS
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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Abstract
The invention provides a display panel, a manufacturing method thereof and a display device, wherein the display panel comprises: the display device comprises a substrate base plate, a first display area and a second display area, wherein the light transmittance of the second display area is larger than that of the first display area, and the second display area comprises a plurality of pixel areas and light transmission areas positioned among the pixel areas; and the multiple groups of sub-pixels with different colors are positioned in the multiple pixel areas, each group of sub-pixels comprises at least two sub-pixels with the same color, each group of sub-pixels comprises at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate base plate is positioned in the orthographic projection of the at least two anodes on the substrate base plate. The invention can solve the problem that the visual experience of a user is influenced by the display difference between the camera area and the normal display area in the related technology.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, and a display device.
Background
The OLED (Organic Light-Emitting Diode) screen is widely concerned by its advantages of self-luminescence, low power consumption, lightness, thinness, flexibility, gorgeous color, high contrast, fast response speed, etc., and is a representative of the next generation Display, and gradually replaces the LCD (Liquid Crystal Display) screen. At present, a comprehensive screen is a relatively popular design concept, and leads fashion trend. In order to further improve the screen occupation ratio, the camera is hidden under the screen to become a brand new technology which is developed by various manufacturers at present, and the biggest challenge of the technology is how to improve the transmittance of the screen.
In the related art, in order to increase the transmittance of the screen, the display PPI (pixel density) of the camera area is reduced, but the display of the camera area and the display of the normal display area are different, which affects the visual experience of the user.
Disclosure of Invention
The invention aims to provide a display panel, a manufacturing method thereof and a display device, which realize high transmittance of a camera area on the premise of ensuring that the PPI displayed by the camera area is not changed, so as to solve the problem that the visual experience of a user is influenced by the display difference between the camera area and a normal display area.
In order to achieve the above purpose, the invention provides the following technical scheme:
a first aspect of the present invention provides a display panel comprising: the display device comprises a substrate base plate, a first display area and a second display area, wherein the light transmittance of the second display area is larger than that of the first display area, and the second display area comprises a plurality of pixel areas and light transmission areas positioned among the pixel areas; and the multiple groups of sub-pixels with different colors are positioned in the multiple pixel areas, each group of sub-pixels comprises at least two sub-pixels with the same color, each group of sub-pixels comprises at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate base plate is positioned in the orthographic projection of the at least two anodes on the substrate base plate.
Optionally, the number of the at least one pixel driving circuit is one, and an orthogonal projection of the one pixel driving circuit on the substrate base plate is located within an orthogonal projection of the at least two anodes on the substrate base plate.
Optionally, the pixel driving circuit includes at least two sub-driving circuits, the at least two sub-driving circuits correspond to the at least two sub-pixels with the same color one to one, the at least two sub-driving circuits correspond to the at least two anodes one to one, each sub-driving circuit is located between the corresponding anode and the substrate of the display panel, an orthogonal projection of each sub-driving circuit on the substrate is located in an orthogonal projection of the corresponding anode on the substrate, the at least two sub-driving circuits are connected by a first transparent routing, and the at least two anodes are connected by a second transparent routing.
Optionally, the first transparent trace and the second transparent trace are disposed in the same layer or in different layers, and at least a portion of the first transparent trace and at least a portion of the second transparent trace are located in the light-transmitting area.
Optionally, the at least two same color sub-pixels are staggered by a predetermined distance in a first direction; or
The at least two same color sub-pixels are aligned in a first direction.
Optionally, the one pixel driving circuit includes:
the storage capacitor comprises a first storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;
one end of the first storage capacitor is connected with a power line, and the other end of the first storage capacitor is connected with a first node;
a control electrode of the first transistor is connected with a first gate signal line or a third gate signal line, a first electrode of the first transistor is connected with the first node, and a second electrode of the first transistor is connected with an initialization voltage level signal line;
a control electrode of the second transistor is connected with a second gating signal line or a fourth gating signal line, a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a third node;
a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a second node, and a second electrode of the third transistor is connected to the third node;
a control electrode of the fourth transistor is connected with the second gating signal line or a fourth gating signal line, a first electrode of the fourth transistor is connected with the second node, and a second electrode of the fourth transistor is connected with a data line;
a control electrode of the fifth transistor is connected with the first light-emitting control signal line or the second light-emitting control signal line, a first electrode of the fifth transistor is connected with the second node, and a second electrode of the fifth transistor is connected with the power line;
a control electrode of the sixth transistor is connected with the first light-emitting control signal line or the second light-emitting control signal line, a first electrode of the sixth transistor is connected with the fourth node, and a second electrode of the sixth transistor is connected with the third node;
a control electrode of the seventh transistor is connected to the second gating signal line or the fourth gating signal line, a first electrode of the seventh transistor is connected to the fourth node, and a second electrode of the seventh transistor is connected to the initialization voltage level signal line.
Optionally, the at least two sub-driving circuits comprise: a first sub-driving circuit and a second sub-driving circuit, the at least two anodes including a first anode and a second anode, the first sub-driving circuit corresponding to the first anode, the second sub-driving circuit corresponding to the second anode;
the first sub driving circuit includes the first storage capacitor, the third transistor, the fourth transistor, and the fifth transistor, and the second sub driving circuit includes the first transistor, the second transistor, the sixth transistor, and the seventh transistor; or
The first sub driving circuit includes the first storage capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor, and the second sub driving circuit includes the fifth transistor and the sixth transistor; or
The first sub driving circuit includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second sub driving circuit includes the first storage capacitor and the third transistor; or
The first sub driving circuit includes the first transistor, the second transistor, the fourth transistor, and the seventh transistor, and the second sub driving circuit includes the first storage capacitor, the third transistor, the fifth transistor, and the sixth transistor.
Optionally, the display panel further includes: a first signal line and a second signal line, the first signal line including: a first light emission control signal line and a second gate control signal line, the second signal line including: a second light emission control signal line and a fourth gate control signal line;
in the second display area, the first light-emitting control signal is connected with a control electrode of the fifth transistor, the second gating signal is connected with a control electrode of the second transistor, the second light-emitting control signal line is located in the first display area and is not located in the second display area, and the fourth gating signal line is located in the first display area and is not located in the second display area; or
In the second display area, the second light emission control signal is connected to a control electrode of the fifth transistor, the fourth gating signal line is connected to a control electrode of the second transistor, the first light emission control signal line is located in the first display area and is not located in the second display area, and the second gating signal line is located in the first display area and is not located in the second display area.
Optionally, the display panel further includes: a data line connected to the second pole of the fourth transistor and a power line connected to the second pole of the fifth transistor.
A second aspect of the present invention provides a method for manufacturing a display panel, the display panel including: a substrate including a first display region and a second display region, the second display region having a light transmittance greater than a light transmittance of the first display region, the method comprising:
forming a plurality of pixel regions and a light transmission region between the plurality of pixel regions in the second display region; the multiple groups of sub-pixels with different colors are located in the multiple pixel areas, each group of sub-pixels comprises at least two sub-pixels with the same color, each group of sub-pixels comprises at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate base plate is located in the orthographic projection of the at least two anodes on the substrate base plate.
A third aspect of the present invention provides a display device including the display panel described above.
The embodiment of the invention has the following beneficial effects:
according to the embodiment of the invention, one pixel driving circuit is split into at least two sub-driving circuits, so that the pixel driving circuit in the camera area is reduced by at least one time, and the high transmittance of the camera area is realized on the premise of ensuring that the PPI displayed in the camera area is not changed.
Drawings
Fig. 1 is a schematic view of a position of a camera area in the related art;
FIG. 2 is a diagram illustrating a PPI display in a camera area according to the related art;
FIG. 3 is a schematic diagram of a driving circuit and an anode of a camera area;
FIG. 4 is a schematic diagram of another drive circuit and anode for a camera area;
fig. 5 is a schematic diagram of a driving circuit and an anode of a camera area according to an embodiment of the present invention;
fig. 6 is a connection diagram of a first sub-driving circuit according to an embodiment of the invention;
fig. 7 is a connection diagram of a second seed driving circuit according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a third sub-driver circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a fourth sub-driving circuit according to an embodiment of the present invention;
fig. 10 is a connection diagram of a fifth seed driving circuit according to an embodiment of the invention;
FIG. 11 is a diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 12 is a schematic diagram showing the connection of the emission control signal and the gate control signal corresponding to FIG. 6 to the sub-driving circuits;
FIG. 13 is a schematic diagram showing the connection between the emission control signal and the gate control signal corresponding to FIG. 6 and the sub-driving circuits;
FIG. 14 is a schematic cross-sectional view corresponding to FIG. 6;
FIG. 15 is a cut-away view of a same color sub-pixel provided by an embodiment of the invention;
FIG. 16 is a schematic view of a manufacturing process of a display panel according to an embodiment of the present invention;
FIG. 17 is a cut-away view of another same color sub-pixel provided by embodiments of the present invention;
FIG. 18 is a diagram illustrating the connection between the emission control signal and the gate control signal corresponding to FIG. 7 and the sub-driving circuits;
FIG. 19 is a schematic cross-sectional view corresponding to FIG. 7;
FIG. 20 is a cut-away view of still another same color sub-pixel provided by embodiments of the present invention;
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
It is a great trend to hide the camera module under the display region, but in the related art, the PPI displayed in the camera region is a low PPI, such as 200PPI, while the PPI displayed in the normal display region is usually between 400-600 PPI. As shown in fig. 1 and fig. 2, fig. 1 is a schematic diagram of a position of a camera area in the prior art, and fig. 2 is a schematic diagram of a PPI displayed in the camera area in the prior art.
Fig. 3 is a schematic diagram of a driving circuit and an anode of a camera area. As shown in fig. 3, the display area of the display screen includes a normal display area and a camera area. If install the camera module in normal display area, and do not adjust the drive circuit and the positive pole overall arrangement in normal display area, then because drive circuit and positive pole are lightproof, the outside light that the camera module can be gathered is less, and normal display area is non-transparent to the camera module. The camera area in fig. 3 comprises a transition area and a transparent area. Only the anode is arranged in the transparent area, and the driving circuit is not arranged, so that more external light can be collected by the camera module, and the transparent area is transparent to the camera module. Because the driving circuit of the transparent region is arranged in the transition region, and the driving circuit is connected with the anode through the transparent wires, when the transparent region is larger or the PPI is higher, the number of the wires is very large, and great impact is brought to the design, the process and the cost.
Fig. 4 is a schematic diagram of another driving circuit and an anode of a camera area, as shown in fig. 4, in a transmissive area, the driving circuit of a pixel is not moved but placed under the anode for shielding, but the existing mature driving circuit has high requirement on space, and the driving circuit cannot be completely shielded by the anode, so that the transmittance and diffraction effects are not ideal.
The invention provides a display panel, a manufacturing method thereof and a display device, and aims to solve the problem that the visual experience of a user is influenced by the display difference between a camera area and a normal display area in the related art.
An embodiment of the present invention provides a display panel, including: the display device comprises a substrate base plate, a first display area and a second display area, wherein the light transmittance of the second display area is larger than that of the first display area, and the second display area comprises a plurality of pixel areas and light transmission areas positioned among the pixel areas;
and the multiple groups of sub-pixels with different colors are positioned in the multiple pixel areas, each group of sub-pixels comprises at least two sub-pixels with the same color, each group of sub-pixels comprises at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate base plate is positioned in the orthographic projection of the at least two anodes on the substrate base plate.
Illustratively, the number of the at least one pixel driving circuit is one, and the orthographic projection of the one pixel driving circuit on the substrate base plate is positioned in the orthographic projection of the at least two anodes on the substrate base plate.
Illustratively, the one pixel driving circuit includes at least two sub-driving circuits, the at least two sub-driving circuits correspond to the at least two sub-pixels with the same color one to one, and the at least two sub-driving circuits correspond to the at least two anodes one to one, each sub-driving circuit is located between a corresponding anode and the substrate of the display panel, an orthographic projection of each sub-driving circuit on the substrate is located in an orthographic projection of a corresponding anode on the substrate, the at least two sub-driving circuits are connected by a first transparent routing, and the at least two anodes are connected by a second transparent routing.
Illustratively, the first transparent trace and the second transparent trace are disposed in the same layer or in different layers, and at least a portion of the first transparent trace and at least a portion of the second transparent trace are located in the light-transmitting area.
Illustratively, the at least two same color sub-pixels are staggered by a predetermined distance in a first direction; or
The at least two same color sub-pixels are aligned in a first direction.
Illustratively, the pixel driving circuit includes: the storage capacitor comprises a first storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;
one end of the first storage capacitor is connected with a power line, and the other end of the first storage capacitor is connected with a first node;
a control electrode of the first transistor is connected with a first gate signal line or a third gate signal line, a first electrode of the first transistor is connected with the first node, and a second electrode of the first transistor is connected with an initialization voltage level signal line;
a control electrode of the second transistor is connected with a second gating signal line or a fourth gating signal line, a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a third node;
a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a second node, and a second electrode of the third transistor is connected to the third node;
a control electrode of the fourth transistor is connected with the second gating signal line or a fourth gating signal line, a first electrode of the fourth transistor is connected with the second node, and a second electrode of the fourth transistor is connected with a data line;
a control electrode of the fifth transistor is connected with a first light-emitting control signal line, a first electrode of the fifth transistor is connected with the second node, and a second electrode of the fifth transistor is connected with a power line;
a control electrode of the sixth transistor is connected with a first light-emitting control signal line, a first electrode of the sixth transistor is connected with a fourth node, and a second electrode of the sixth transistor is connected with the third node;
a control electrode of the seventh transistor is connected to the second gating signal line or the fourth gating signal line, a first electrode of the seventh transistor is connected to the fourth node, and a second electrode of the seventh transistor is connected to the initialization voltage level signal line.
Illustratively, the at least two sub-driving circuits include: a first sub-driving circuit and a second sub-driving circuit, the at least two anodes including a first anode and a second anode, the first sub-driving circuit corresponding to the first anode, the second sub-driving circuit corresponding to the second anode;
the first sub driving circuit includes the first storage capacitor, the third transistor, the fourth transistor, and the fifth transistor, and the second sub driving circuit includes the first transistor, the second transistor, the sixth transistor, and the seventh transistor; or
The first sub driving circuit includes the first storage capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor, and the second sub driving circuit includes the fifth transistor and the sixth transistor; or
The first sub driving circuit includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second sub driving circuit includes the first storage capacitor and the third transistor; or
The first sub driving circuit includes the first transistor, the second transistor, the fourth transistor, and the seventh transistor, and the second sub driving circuit includes the first storage capacitor, the third transistor, the fifth transistor, and the sixth transistor.
Illustratively, the display panel further includes: a first signal line and a second signal line, the first signal line including: a first light emission control signal line and a second gate control signal line, the second signal line including: a second light emission control signal line and a fourth gate control signal line; wherein,
in the second display area, the first light-emitting control signal is connected with a control electrode of the fifth transistor, the second gating signal is connected with a control electrode of the second transistor, the second light-emitting control signal line is located in the first display area and is not located in the second display area, and the fourth gating signal line is located in the first display area and is not located in the second display area; or
In the second display area, the second light emission control signal is connected to a control electrode of the fifth transistor, the fourth gating signal line is connected to a control electrode of the second transistor, the first light emission control signal line is located in the first display area and is not located in the second display area, and the second gating signal line is located in the first display area and is not located in the second display area.
Illustratively, the display panel further includes a data line connected to the second pole of the fourth transistor and a power line connected to the second pole of the fifth transistor.
Fig. 5 is a schematic diagram of a driving circuit and an anode of a camera area according to an embodiment of the present invention, and as shown in fig. 5, the display panel includes a first display area and a second display area, and a light transmittance of the second display area is greater than a light transmittance of the first display area. The first display area is a normal display area, and the second display area is a camera area. The second display area is provided with a plurality of pixel areas, each pixel area comprises a plurality of groups of sub-pixels with different colors, each group of sub-pixels comprises at least two sub-pixels with the same color, and each group of sub-pixels comprises a pixel driving circuit and at least two anodes. The pixel driving circuit of the camera area is not moved to other positions, but the original pixel driving circuit is divided into two sub-driving circuits, and the two sub-driving circuits correspond to two sub-pixels with the same color one by one. The two sub-driving circuits are electrically connected through a first transparent wire. The two sub-driving circuits correspond to the two anodes one by one. Each sub-driving circuit is located between the corresponding anode and the substrate base plate of the display panel, and the orthographic projection of each sub-driving circuit on the substrate base plate is located in the orthographic projection of the corresponding anode on the substrate base plate. The two anodes are electrically connected by a second transparent trace. The first transparent wire and the second transparent wire are arranged on the same layer or different layers.
Fig. 6 is a connection schematic diagram of a first sub-driver circuit according to an embodiment of the present invention, fig. 7 is a connection schematic diagram of a second sub-driver circuit according to an embodiment of the present invention, fig. 8 is a connection schematic diagram of a third sub-driver circuit according to an embodiment of the present invention, fig. 9 is a connection schematic diagram of a fourth sub-driver circuit according to an embodiment of the present invention, and fig. 10 is a connection schematic diagram of a fifth sub-driver circuit according to an embodiment of the present invention. Referring to fig. 6 to 10, two same color sub-pixels are staggered by a predetermined distance in a first direction; or two same color sub-pixels are aligned in a first direction.
The connection method of the sub-driving circuit of the present invention is only an exemplary connection method, but not limited thereto.
Fig. 11 is a schematic diagram of a pixel driving circuit according to an embodiment of the present invention, and as shown in fig. 11, the pixel driving circuit includes: a first storage capacitor Cst, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
One end of the first storage capacitor Cst is connected to the power line ELVDD, and the other end of the storage capacitor Cst is connected to the first node N1;
a control electrode of the first transistor T1 is connected to the first gate signal line or the third gate signal line, a first electrode of the first transistor T1 is connected to the first node N1, a second electrode of the first transistor T1 is connected to the initialization voltage level signal line Vinit, wherein,
a control electrode of the second transistor T2 is connected to a second gating signal line or a fourth gating signal line, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to a third node N3;
a control electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to a second node N2, and a second electrode of the third transistor T3 is connected to the third node N3;
a control electrode of the fourth transistor T4 is connected to the second gating signal line or the fourth gating signal line, a first electrode of the fourth transistor T4 is connected to the second node N2, and a second electrode of the fourth transistor T4 is connected to the Data line Data.
A control electrode of the fifth transistor T5 is connected to the first emission control signal line EM, a first electrode of the fifth transistor T5 is connected to the second node N2, and a second electrode of the fifth transistor T5 is connected to the power supply line ELVDD;
a control electrode of the sixth transistor T6 is connected to the first emission control signal line EM, a first electrode of the sixth transistor T6 is connected to a fourth node N4, and a second electrode of the sixth transistor T6 is connected to the third node N3;
a control electrode of the seventh transistor T7 is connected to the second or fourth gating signal line, a first electrode of the seventh transistor T7 is connected to the fourth node N4, and a second electrode of the seventh transistor T7 is connected to the initialization voltage level signal line Vinit.
The pixel driving circuit shown in fig. 11 is divided into a first sub-driving circuit and a second sub-driving circuit, the at least two anodes include a first anode and a second anode, the first sub-driving circuit corresponds to the first anode, and the second sub-driving circuit corresponds to the second anode.
The first sub driving circuit includes a first storage capacitor Cst, a third transistor T3, a fourth transistor T4, and a fifth transistor T5, and the second sub driving circuit includes a first transistor T1, a second transistor T2, a sixth transistor T6, and a seventh transistor T7. T3, T4, T5 and Cst are shielded by the first anode, T1, T2, T6 and T7 are shielded by the second anode, ITO is adopted to connect N1, T1 and T2, Ioff can be reduced, low frequency is benefited, Data writing is not affected, and high frequency image quality is not affected.
Alternatively, the first sub driving circuit includes a first storage capacitor Cst, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a seventh transistor T7, and the second sub driving circuit includes a fifth transistor T5 and a sixth transistor T6. T1, T2, T3, T4, T7 and Cst are sheltered by the first anode, and T5 and T6 are sheltered by the second anode, so that the number of transverse routing lines can be reduced, meanwhile, Data writing is not affected, and high-frequency image quality is not affected.
Alternatively, the first sub driving circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and the second sub driving circuit includes a first storage capacitor Cst and the third transistor T3. T1, T2, T4, T5, T6 and T7 are shielded by anode 1, and T3 and Cst are shielded by anode 2, so that the number of transverse traces can be reduced, and Ioff of T1T 2 is reduced, which is beneficial to low frequency.
Alternatively, the first sub driving circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, and a seventh transistor T7, and the second sub driving circuit includes a first storage capacitor Cst, a third transistor T3, a fifth transistor T5, and a sixth transistor T6. T1, T2, T4 and T7 are shielded by the first anode, and T3, T5, T6 and Cst are shielded by the second anode, so that the number of transverse traces can be reduced, and Ioff of T1 and T2 is reduced, which is beneficial to low frequency.
Fig. 12 is a schematic diagram of connection between the emission control signal and the gate control signal corresponding to fig. 6 and the sub-driving circuit, and with reference to fig. 6, 11 and 12, the display panel of the present invention further includes: a first signal line and a second signal line, the first signal line including: a first emission control signal line EM1 and a second Gate control signal line Gate2, the second signal line including: a second emission control signal line EM2 and a fourth Gate control signal line Gate4.
Referring to fig. 12(a), in the second display region, the second emission control signal EM2 is connected to the Gate of the fifth transistor T5, the fourth Gate control signal line Gate4 is connected to the Gate of the second transistor T2, the first emission control signal line EM1 is located in the first display region and is not located in the second display region, and the second Gate control signal line Gate2 is located in the first display region and is not located in the second display region.
Referring to fig. 12(b), in the second display region, the first emission control signal EM1 is connected to the Gate of the fifth transistor T5, the second Gate control signal Gate2 is connected to the Gate of the second transistor T2, the second emission control signal line EM2 is located in the first display region and is not located in the second display region, and the fourth Gate control signal line Gate4 is located in the first display region and is not located in the second display region.
Referring to fig. 12(c), in the second display region, the first emission control signal EM1 is connected to the Gate of the fifth transistor T5, the second Gate control signal Gate2 is connected to the Gate of the second transistor T2, the second emission control signal line EM2 is disconnected, and the fourth Gate control signal line Gate4 is disconnected.
The display panel, its characterized in that still includes: a data line connected to the second pole of the fourth transistor and a power line connected to the second pole of the fifth transistor.
FIG. 13 is a schematic diagram showing the connection between the emission control signal and the gate control signal corresponding to FIG. 6 and the sub-driving circuits; referring to fig. 6, 11 and 13, wherein the first sub driving circuit includes a first storage capacitor Cst, a third transistor T3, a fourth transistor T4 and a fifth transistor T5, and the second sub driving circuit includes a first transistor T1, a second transistor T2, a sixth transistor T6 and a seventh transistor T7. T3, T4, T5 and Cst are shielded by the first anode, T1, T2, T6 and T7 are shielded by the second anode, ITO is adopted to connect N1, T1 and T2, Ioff can be reduced, low frequency is benefited, Data writing is not affected, and high frequency image quality is not affected.
According to the embodiment of the invention, one pixel driving circuit is split into at least two sub-driving circuits, so that the pixel driving circuit in the camera area is reduced by at least one time, and the high transmittance of the camera area is realized on the premise of ensuring that the PPI displayed in the camera area is not changed.
The embodiment of the invention provides a manufacturing method of a display panel, wherein the display panel comprises the following steps: a substrate including a first display region and a second display region, the second display region having a light transmittance greater than a light transmittance of the first display region, the method comprising:
forming a plurality of pixel regions and a light transmission region between the plurality of pixel regions in the second display region; the multiple groups of sub-pixels with different colors are located in the multiple pixel areas, each group of sub-pixels comprises at least two sub-pixels with the same color, each group of sub-pixels comprises at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate base plate is located in the orthographic projection of the at least two anodes on the substrate base plate.
Illustratively, the number of the at least one pixel driving circuit is one, and the orthographic projection of the one pixel driving circuit on the substrate base plate is positioned in the orthographic projection of the at least two anodes on the substrate base plate.
Illustratively, the one pixel driving circuit includes at least two sub-driving circuits, the at least two sub-driving circuits correspond to the at least two sub-pixels with the same color one to one, and the at least two sub-driving circuits correspond to the at least two anodes one to one, each sub-driving circuit is located between a corresponding anode and the substrate of the display panel, an orthographic projection of each sub-driving circuit on the substrate is located in an orthographic projection of a corresponding anode on the substrate, the at least two sub-driving circuits are connected by a first transparent routing, and the at least two anodes are connected by a second transparent routing.
Illustratively, the first transparent trace and the second transparent trace are formed by a one-time patterning process.
Fig. 14 is a schematic cross-sectional view corresponding to fig. 6, fig. 15 is a schematic cross-sectional view of a sub-pixel of the same color according to an embodiment of the present invention, and fig. 16 is a schematic manufacturing flow diagram of a display panel according to an embodiment of the present invention; refer to fig. 14, 15, 16.
The manufacturing method of the display panel provided by the embodiment of the invention comprises the following steps: manufacturing a semiconductor layer on a substrate; and manufacturing a first insulating layer on the semiconductor layer. The substrate base plate can be a glass base plate or a quartz base plate.
Specifically, a layer of semiconductor material and an insulating material are sequentially deposited on a substrate, a layer of photoresist is coated on the insulating material, and the photoresist is exposed by adopting a half-tone or gray-tone mask plate to form a photoresist unreserved region, a photoresist partial reserved region and a photoresist complete reserved region, wherein the photoresist complete reserved region corresponds to a region where a pattern of an etching barrier layer is located, and the photoresist unreserved region corresponds to a region except for the pattern of an active layer; developing, completely removing the photoresist in the photoresist unreserved region, keeping the thickness of the photoresist in the photoresist completely-reserved region unchanged, reserving part of the photoresist in the photoresist partially-reserved region, and completely etching away the semiconductor material in the photoresist unreserved region by an etching process to form a pattern of the active layer; ashing the photoresist in the photoresist partial reserved area, etching the insulating material in the photoresist partial reserved area through an etching process to form a pattern of an etching barrier layer, and stripping the residual photoresist.
Manufacturing a first gate layer on the first insulating layer; in particular, sputtering or thermal evaporation may be used to deposit a thickness of about
The gate metal layer may be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and the like, and an alloy thereof, and the gate metal layer may be a single-layer structure or a multi-layer structure such as Cu \ Mo, Ti \ Cu \ Ti, Mo \ Al \ Mo, and the like. Coating a layer of photoresist on the gate metal layer, and exposing the photoresist by using a mask plate to form a photoresist unreserved region and a photoresist reserved region, wherein the photoresist reserved region corresponds to the region where the graphs of the gate line and the gate electrode are located, and the photoresist unreserved region corresponds to the region except the graphs; developing, completely removing the photoresist in the photoresist unreserved region, and keeping the thickness of the photoresist in the photoresist reserved region unchanged; and completely etching the gate metal film in the region where the photoresist is not reserved by an etching process, and stripping the residual photoresist to form the patterns of the gate line and the gate electrode.
Manufacturing a second insulating layer on the first gate layer; specifically, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method may be used to deposit a thickness of
Gate insulating layer of (2), gate insulationThe layer may be selected from an oxide, nitride or oxynitride, with the corresponding reactant gas being SiH4、NH3、N2Or SiH2Cl2、NH3、N2。
Manufacturing a first transparent wire on the second insulating layer;
manufacturing a third insulating layer, a second gate layer and a fourth insulating layer on the second insulating layer;
forming via holes in the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer;
and manufacturing a source electrode and a drain electrode on the fourth insulating layer, wherein the source electrode and the drain electrode are connected to the semiconductor layer through the via hole, and the source electrodes of two pixel driving sub-circuits for driving two sub-pixels with the same color are both connected to the first transparent wiring, or the drain electrodes for driving two sub-pixels with the same color are both connected to the first transparent wiring.
Specifically, magnetron sputtering, thermal evaporation or other film forming methods can be used to deposit a layer with a thickness of about one layer on the substrate on which the fourth insulating layer is formed
The source-drain metal layer of (2) may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy thereof. The source and drain metal layers can be of a single-layer structure or a multi-layer structure, such as Cu \ Mo, Ti \ Cu \ Ti, Mo \ Al \ Mo and the like. Coating a layer of photoresist on the source drain metal layer, and exposing the photoresist by using a mask plate to form a photoresist unreserved region and a photoresist reserved region, wherein the photoresist reserved region corresponds to the region where the patterns of the source electrode and the drain electrode are located, and the photoresist unreserved region corresponds to the region except the patterns; developing, completely removing the photoresist in the photoresist unreserved region, and keeping the thickness of the photoresist in the photoresist reserved region unchanged; and completely etching the source drain metal layer of the region where the photoresist is not reserved by an etching process, and stripping the residual photoresist to form a drain electrode and a source electrode.
And manufacturing a fifth insulating layer on the fourth insulating layer.
And manufacturing a third transparent wire on the fifth insulating layer, wherein the third transparent wire is a data line or a power line.
Specifically, a layer with a thickness of about a thickness can be deposited on the substrate on which the fifth insulating layer is formed by magnetron sputtering, thermal evaporation or other film forming methods
The metal layer of (3) may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals. Coating a layer of photoresist on the metal layer, and exposing the photoresist by adopting a mask plate to form a photoresist unreserved region and a photoresist reserved region by the photoresist, wherein the photoresist reserved region corresponds to a region where a graph of the data line is located, and the photoresist unreserved region corresponds to a region except the graph; developing, completely removing the photoresist in the photoresist unreserved region, and keeping the thickness of the photoresist in the photoresist reserved region unchanged; and completely etching the source drain metal layer of the region where the photoresist is not reserved by an etching process, and stripping the residual photoresist to form the drain electrode data line.
And manufacturing a sixth insulating layer and an anode on the fifth insulating layer.
Fig. 17 is a cut-away view of another same-color sub-pixel provided in an embodiment of the present invention, and fig. 17 is different from fig. 15 in that only one layer of transparent traces is fabricated.
FIG. 18 is a diagram illustrating the connection between the emission control signal and the gate control signal corresponding to FIG. 7 and the sub-driving circuits; fig. 19 is a schematic cross-sectional view corresponding to fig. 7. FIG. 20 is a cut-away view of still another same color sub-pixel provided by embodiments of the present invention; both sections are B because the transverse trace runs partially Gate1 and partially Gate 2.
A third aspect of the present invention provides a display device including the display panel described above.
The display device includes but is not limited to: radio frequency unit, network module, audio output unit, input unit, sensor, display unit, user input unit, interface unit, memory, processor, and power supply. It will be appreciated by those skilled in the art that the above described configuration of the display device does not constitute a limitation of the display device, and that the display device may comprise more or less of the components described above, or some components may be combined, or a different arrangement of components. In the embodiment of the present invention, the display device includes, but is not limited to, a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.
The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet personal computer and the like, wherein the display device further comprises a flexible circuit board, a printed circuit board and a back plate.
In the embodiments of the methods of the present invention, the sequence numbers of the steps are not used to limit the sequence of the steps, and for those skilled in the art, the sequence of the steps is not changed without creative efforts.
It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiments, since they are substantially similar to the product embodiments, the description is simple, and the relevant points can be referred to the partial description of the product embodiments.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (11)
1. A display panel, comprising:
the display device comprises a substrate base plate, a first display area and a second display area, wherein the light transmittance of the second display area is larger than that of the first display area, and the second display area comprises a plurality of pixel areas and light transmission areas positioned among the pixel areas;
and the multiple groups of sub-pixels with different colors are positioned in the multiple pixel areas, each group of sub-pixels comprises at least two sub-pixels with the same color, each group of sub-pixels comprises at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate base plate is positioned in the orthographic projection of the at least two anodes on the substrate base plate.
2. The display panel according to claim 1, wherein the at least one pixel driving circuit is one in number, and an orthogonal projection of the one pixel driving circuit on the substrate base is located within an orthogonal projection of the at least two anodes on the substrate base.
3. The display panel of claim 2, wherein the one pixel driving circuit comprises at least two sub-driving circuits, the at least two sub-driving circuits correspond to the at least two sub-pixels with the same color one to one, the at least two sub-driving circuits correspond to the at least two anodes one to one, each sub-driving circuit is located between the corresponding anode and the substrate of the display panel, an orthogonal projection of each sub-driving circuit on the substrate is located in an orthogonal projection of the corresponding anode on the substrate, the at least two sub-driving circuits are connected by a first transparent trace, and the at least two anodes are connected by a second transparent trace.
4. The display panel according to claim 3, wherein the first transparent traces and the second transparent traces are disposed in the same layer or in different layers, and at least a portion of the first transparent traces and at least a portion of the second transparent traces are located in the light-transmitting area.
5. The display panel according to claim 1, wherein the at least two same color sub-pixels are staggered by a predetermined distance in a first direction; or
The at least two same color sub-pixels are aligned in a first direction.
6. The display panel according to claim 2, wherein the one pixel driving circuit comprises:
the storage capacitor comprises a first storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;
one end of the first storage capacitor is connected with a power line, and the other end of the first storage capacitor is connected with a first node;
a control electrode of the first transistor is connected with a first gate signal line or a third gate signal line, a first electrode of the first transistor is connected with the first node, and a second electrode of the first transistor is connected with an initialization voltage level signal line;
a control electrode of the second transistor is connected with a second gating signal line or a fourth gating signal line, a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a third node;
a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a second node, and a second electrode of the third transistor is connected to the third node;
a control electrode of the fourth transistor is connected with the second gating signal line or a fourth gating signal line, a first electrode of the fourth transistor is connected with the second node, and a second electrode of the fourth transistor is connected with a data line;
a control electrode of the fifth transistor is connected with the first light-emitting control signal line or the second light-emitting control signal line, a first electrode of the fifth transistor is connected with the second node, and a second electrode of the fifth transistor is connected with the power line;
a control electrode of the sixth transistor is connected with the first light-emitting control signal line or the second light-emitting control signal line, a first electrode of the sixth transistor is connected with the fourth node, and a second electrode of the sixth transistor is connected with the third node;
a control electrode of the seventh transistor is connected to the second gating signal line or the fourth gating signal line, a first electrode of the seventh transistor is connected to the fourth node, and a second electrode of the seventh transistor is connected to the initialization voltage level signal line.
7. The display panel of claim 6, wherein the at least two sub-driving circuits comprise: a first sub-driving circuit and a second sub-driving circuit, the at least two anodes including a first anode and a second anode, the first sub-driving circuit corresponding to the first anode, the second sub-driving circuit corresponding to the second anode;
the first sub driving circuit includes the first storage capacitor, the third transistor, the fourth transistor, and the fifth transistor, and the second sub driving circuit includes the first transistor, the second transistor, the sixth transistor, and the seventh transistor; or
The first sub driving circuit includes the first storage capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor, and the second sub driving circuit includes the fifth transistor and the sixth transistor; or
The first sub driving circuit includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second sub driving circuit includes the first storage capacitor and the third transistor; or
The first sub driving circuit includes the first transistor, the second transistor, the fourth transistor, and the seventh transistor, and the second sub driving circuit includes the first storage capacitor, the third transistor, the fifth transistor, and the sixth transistor.
8. The display panel of claim 7, further comprising: a first signal line and a second signal line, the first signal line including: a first light emission control signal line and a second gate control signal line, the second signal line including: a second light emission control signal line and a fourth gate control signal line; the method is characterized in that:
in the second display area, the first light-emitting control signal is connected with a control electrode of the fifth transistor, the second gating signal is connected with a control electrode of the second transistor, the second light-emitting control signal line is located in the first display area and is not located in the second display area, and the fourth gating signal line is located in the first display area and is not located in the second display area; or
In the second display area, the second light emission control signal is connected to a control electrode of the fifth transistor, the fourth gating signal line is connected to a control electrode of the second transistor, the first light emission control signal line is located in the first display area and is not located in the second display area, and the second gating signal line is located in the first display area and is not located in the second display area.
9. The display panel according to claim 8, further comprising: a data line connected to the second pole of the fourth transistor and a power line connected to the second pole of the fifth transistor.
10. A method of making a display panel, the display panel comprising: a substrate including a first display region and a second display region, the second display region having a light transmittance greater than a light transmittance of the first display region, the method comprising:
forming a plurality of pixel regions and a light transmission region between the plurality of pixel regions in the second display region; the multiple groups of sub-pixels with different colors are located in the multiple pixel areas, each group of sub-pixels comprises at least two sub-pixels with the same color, each group of sub-pixels comprises at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate base plate is located in the orthographic projection of the at least two anodes on the substrate base plate.
11. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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