CN113782547B

CN113782547B - Telescopic substrate

Info

Publication number: CN113782547B
Application number: CN202111002484.XA
Authority: CN
Inventors: 林恭正
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-11-10
Filing date: 2021-08-30
Publication date: 2023-08-15
Anticipated expiration: 2041-08-30
Also published as: CN113782547A

Abstract

The invention discloses a retractable substrate, which comprises a patterned substrate, a plurality of device parts and a plurality of circuit parts. The device is located on the patterned substrate. Each device portion includes an active region and a peripheral region surrounding the active region. Each device part comprises a first active element and a second active element which are arranged in the active region. The circuit part is positioned on the patterned substrate and connected with the corresponding device part.

Description

Telescopic substrate

Technical Field

The present invention relates to a retractable substrate, and more particularly, to a retractable substrate suitable for a display device.

Background

With the high development of electronic technology, electronic products are continuously promoted to be new. In order to make the electronic product applicable to various fields, the characteristics of being stretchable, light and thin and having an unlimited shape are increasingly paid attention to. That is, electronic products are increasingly required to have different shapes according to different application modes and application environments, so the electronic products need to have stretchability.

However, in the stretched state, the electronic product may be broken structurally due to the stress, and even further cause the disconnection of the internal circuit. Therefore, how to provide stretchable electronic products with good manufacturing yield (yield) and product reliability (reliability) is an urgent issue.

Disclosure of Invention

The invention provides a telescopic substrate, which can solve the problem that an active element is damaged after the telescopic substrate is stretched.

At least one embodiment of the present invention provides a retractable substrate. The retractable substrate comprises a patterned substrate, a plurality of device parts and a plurality of circuit parts. The device is located on the patterned substrate. Each device portion includes an active region and a peripheral region surrounding the active region. Each device portion includes a first active element disposed in the active region and a second active element. The circuit part is positioned on the patterned substrate and connected with the corresponding device part.

Drawings

FIG. 1A is a schematic top view of a retractable substrate according to an embodiment of the present invention;

FIG. 1B is a schematic top view of the stretchable substrate of FIG. 1A after stretching;

FIG. 2 is a schematic diagram of a strain gauge simulation of the retractable substrate of FIG. 1B;

FIG. 3A is a schematic top view of a retractable substrate according to an embodiment of the present invention;

FIG. 3B is a schematic top view of the retractable substrate of FIG. 3A with parts omitted;

FIG. 3C is a schematic top view of the retractable substrate of FIG. 3A with parts omitted;

FIG. 3D is a schematic cross-sectional view of the retractable substrate of FIG. 3A;

FIG. 3E is an equivalent circuit diagram of a sub-pixel according to an embodiment of the invention;

FIG. 4 is a schematic top view of a retractable substrate according to an embodiment of the present invention;

fig. 5 is a schematic top view of a retractable substrate according to an embodiment of the invention.

Symbol description

10. 20, 30, 40: retractable base plate

100 patterning substrate

200 device part

300 line portion

310 signal line

400 connecting portion

410 reinforcing structure

AR active region

BL buffer layer

CHa, CHb, CHc, CHd, CHe, CHf semiconductor layer

CL1 first conductive layer

CL2 second conductive layer

CL3 third conductive layer

Da. Db, dc, dd, de, df drain electrode

DL1 first data line

DL2 second data line

DL3 third data line

Ga. Gb, gc, gd, ge, gf grid electrode

GI. ILD (dielectric layer)

Length L

L1:first LED

L2:second light-emitting diode

L3:third light-emitting diode

PD1, PD2, PD3, PD4, PD5, PD6: a pad

PL planar layer

PL1 first power line

PL2 second power line

PR peripheral region

Sa, sb, sc, sd, se, sf source electrode

SE1 first switch element

SE2 second switching element

SE3 third switching element

SP1 first subpixel

SP2 second subpixel

SP3 third subpixel

SGL signal line

SL: scanning line

TH: through hole

T1 first active device

T2, the second active element

T3 third active device

V: via hole

W, W1 width W2

Detailed Description

Fig. 1A is a schematic top view of a retractable substrate 10 according to an embodiment of the invention.

Referring to fig. 1A, the retractable substrate 10 includes a patterned substrate 100, a plurality of device portions 200, and a plurality of circuit portions 300. In this embodiment, the retractable base plate 10 further includes a connection portion 400.

The patterned substrate 100 is made of a soft material, for example, the material of the patterned substrate 100 may include Polyimide (PI), polyethylene naphthalate (polyethylene naphthalate; PEN), polyethylene terephthalate (polyethylene terephthalate; PET), polycarbonate (PC), polyethersulfone (polyether sulfone; PES) or polyarylate (polyacrylate), other suitable materials, or a combination of at least two of the foregoing materials, but the present invention is not limited thereto.

In the present embodiment, the patterned substrate 100 has a plurality of through holes TH. In this embodiment, each through hole TH is dumbbell-shaped. In the present embodiment, a portion of the through holes TH extend along the first direction E1, and another portion of the through holes TH extend along the second direction E2. The partial through holes TH extending in the first direction E1 and the other partial through holes TH extending in the second direction E2 are alternately arranged, thereby improving stretchability of the stretchable substrate 10.

The device portion 200, the circuit portion 300, and the connection portion 400 are located on the patterned substrate 100. The device portion 200, the circuit portion 300, and the connection portion 400 are connected together, and one of the through holes TH is substantially surrounded by at least four device portions 200. In the present embodiment, one through hole TH is substantially surrounded by four device portions 200, two line portions 300, and two connection portions 400. For example, in fig. 1A, the through hole TH located in the center is surrounded by the two left and right line portions 300, the two upper and lower connection portions 400, and the device portion 200 at four corners.

Each device portion 200 includes an active region AR and a peripheral region PR surrounding the active region AR. Each device portion 200 includes a first active device T1 and a second active device T2 disposed in the active region AR. In this embodiment, each device portion 200 further includes a third active element T3. In some embodiments, each device portion 200 is rectangular in length L and width W, the width W1 of the peripheral region PR is 16% W to 40% W in the direction of the width W of each device portion 200, and the width W2 of the peripheral region PR is 16% L to 40% L in the direction of the length L of each device portion 200. The width W1 and the width W2 of the peripheral region PR are 10 to 250 μm.

In the present embodiment, each device section 200 includes a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3, wherein the second subpixel SP2 is located between the first subpixel SP1 and the third subpixel SP3. The first, second and third sub-pixels SP1, SP2 and SP3 include a first active device T1, a second active device T2 and a third active device T3, respectively, and the first, second and third sub-pixels SP1, SP2 and SP3 include a first light emitting diode (not shown in fig. 1A), a second light emitting diode (not shown in fig. 1A) and a third light emitting diode (not shown in fig. 1A), respectively. The first active device T1, the second active device T2 and the third active device T3 are respectively suitable for driving the first light emitting diode, the second light emitting diode and the third light emitting diode.

In the present embodiment, the retractable substrate 10 is suitable for a display device, but the invention is not limited thereto. In other embodiments, the retractable substrate 10 is not a display device, and the device portion 200 does not include sub-pixels.

The line portion 300 connects the corresponding device portion 200. In the present embodiment, each line portion 300 connects two corresponding device portions 200. Each circuit portion 300 includes at least one signal line 310. The signal lines 310 are electrically connected to the corresponding first sub-pixels SP1, the corresponding second sub-pixels SP2, and/or the corresponding third sub-pixels SP3. Although only the signal line 310 is shown in fig. 1A as extending to the edge of the device portion 200, in practice, many other wires (not shown in fig. 1A) are also included in the device portion 200, so that the signal line 310 is electrically connected to the corresponding first sub-pixel SP1, the corresponding second sub-pixel SP2, and/or the corresponding third sub-pixel SP3.

The connection portion 400 is adjacent to the corresponding line portion 300. In the present embodiment, each connection portion 400 connects the corresponding two device portions 200 and is located at one side of the corresponding one of the line portions 300. Each of the connection portions 400 includes a plurality of reinforcing structures 410 arranged in sequence. The reinforcing structure 410 is spaced apart from the signal line 310. In some embodiments, the reinforcement structure 410 can adjust the neutral axis position of the connection portion 400 and the line portion 300, and reduce the risk of the signal line 310 breaking due to stretching. In addition, since the reinforcing structure 410 is spaced apart from the signal line 310, even if the reinforcing structure 410 is broken, the broken line is not easily broken to the signal line 310, resulting in breakage of the signal line 310. In some embodiments, the reinforcing structure 410 is a spare wire. In some embodiments, the reinforcing structure 410 is an insulating pattern.

Fig. 1B is a schematic top view of the stretchable substrate 10 of fig. 1A after stretching. Fig. 2 is a schematic diagram of strain capacity simulation of the retractable substrate of fig. 1B, wherein the values on the left in fig. 2 represent strain capacity.

Referring to fig. 1B and 2, the stretchable substrate 10 is stretched and deformed. In the present embodiment, the stretchable substrate 10 receives the tensile forces F in different directions, and the tensile forces F change the shape of the stretchable substrate 10. As can be seen from the simulation of fig. 2, in the device portion 200, the peripheral region PR near the periphery is more likely to have a larger strain than the central active region AR, so that the first active device T1, the second active device T2 and the third active device T3 are disposed in the active region AR instead of the peripheral region PR, thereby avoiding the failure problem of the first active device T1, the second active device T2 and the third active device T3 of the stretchable substrate 10 after stretching.

In some embodiments, the first active device T1, the second active device T2 and the third active device T3 are driving devices directly electrically connected to the light emitting diode, i.e. no other thin film transistor is located between the first active device T1, the second active device T2 and the third active device T3 and the corresponding light emitting diode, so that the quality of the first active device T1, the second active device T2 and the third active device T3 affects the display screen more than other thin film transistors (e.g. switching devices) in the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3. Therefore, disposing the first active device T1, the second active device T2, and the third active device T3 in the active region AR can better improve the problem of the display Mura of the stretchable substrate 10 after stretching than disposing other thin film transistors not directly electrically connected to the light emitting diode in the active region AR.

Fig. 3A is a schematic top view of a retractable substrate 20 according to an embodiment of the present invention, wherein for more clearly illustrating the retractable substrate 20 of fig. 3A, part of components of the retractable substrate 20 are omitted and are shown in fig. 3B and 3C, in fig. 3A to 3D, the same conductive layers (i.e. conductive layers formed by the same patterning process) are shown with the same diagonal lines or dots, and different conductive layers are electrically connected through the via V penetrating through the insulating layers (e.g. the insulating layer GI and/or the insulating layer ILD). Fig. 3D is a schematic cross-sectional view of line A-A' of fig. 3A. Fig. 3E is an equivalent circuit diagram of a sub-pixel according to an embodiment of the present invention, in which the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 have similar equivalent circuits, and fig. 3E is an example of the equivalent circuit of the first sub-pixel SP 1.

It should be noted that the embodiments of fig. 3A to 3E use the element numbers and part of the contents of the embodiments of fig. 1A and 1B, wherein the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.

Referring to fig. 3A to 3E, the device portion 200 and the circuit portion 300 are disposed on the patterned substrate 100. In some embodiments, the surface of the patterned substrate 100 is provided with a buffer layer BL, and the device portion 200 and the circuit portion 300 are located on the buffer layer BL.

Each line section 300 includes a plurality of signal lines SGL. The signal lines SGL are the scanning lines SL, the first data lines DL1, the second data lines DL2, the third data lines DL3, the first power lines PL1, and/or the second power lines PL2.

Each device section 200 includes a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3.

The first subpixel SP1 includes a first switching element SE1, a first active element T1, and a first light emitting diode L1. The first switching element SE1 includes a semiconductor layer CHa, a gate Ga, a source Sa, and a drain Da. The gate Ga is electrically connected to the scan line SL. The gate Ga overlaps the channel layer CHa with the insulating layer GI interposed therebetween. The insulating layer ILD covers the gate Ga. The source Sa and the drain Da are disposed on the insulating layer ILD and electrically connected to the channel layer CHa. The source Sa is electrically connected to the first data line DL1.

The first active device T1 includes a semiconductor layer CHb, a gate Gb, a source Sb, and a drain Db. The gate Gb is electrically connected to the drain Da of the first switching element SE 1. The gate Gb overlaps the channel layer CHb with the insulating layer GI interposed therebetween. The insulating layer ILD covers the gate Gb. The source electrode Sb and the drain electrode Db are disposed on the insulating layer ILD and electrically connected to the channel layer CHb. The source electrode Sb is electrically connected to the first power supply line PL1.

The flat layer PL is located on the source Sa, the drain Da, the source Sb and the drain Db, and the first light emitting diode L1 is located on the flat layer PL. In some embodiments, the first light emitting diode L1 is electrically connected to the source Sb and the second power line PL2 through the pad PD1 and the pad PD2, respectively.

The second subpixel SP2 includes a second switching element SE2, a second active element T2, and a second light emitting diode L2. The second switching element SE2 includes a semiconductor layer CHc, a gate Gc, a source Sc, and a drain Dc. The gate Gc is electrically connected to the scanning line SL. The gate Gc is overlapped with the channel layer CHc with the insulating layer GI interposed therebetween. The insulating layer ILD covers the gate Gc. The source Sc and the drain Dc are disposed on the insulating layer ILD and electrically connected to the channel layer CHc. The source Sc is electrically connected to the second data line DL2.

The second active device T2 includes a semiconductor layer CHd, a gate Gd, a source Sd and a drain Dd. The gate Gd is electrically connected to the drain Dc of the second switching element SE 2. The gate Gd overlaps the channel layer CHd with the insulating layer GI interposed therebetween. The insulating layer ILD covers the gate Gd. The source electrode Sd and the drain electrode Dd are disposed on the insulating layer ILD and electrically connected to the channel layer CHd. The source Sd is electrically connected to the first power line PL1.

The second light emitting diode L2 is located on the flat layer PL. In some embodiments, the second light emitting diode L2 is electrically connected to the source Sd and the second power line PL2 through the pad PD3 and the pad PD4, respectively.

The third subpixel SP3 includes a third switching element SE3, a third active element T3, and a third light emitting diode L3. The third switching element SE3 includes a semiconductor layer CHe, a gate Ge, a source SE, and a drain De. The gate Ge is electrically connected to the scanning line SL. The gate Ge overlaps the channel layer CHe with an insulating layer GI interposed therebetween. An insulating layer ILD covers the gate Ge. The source electrode Se and the drain electrode De are disposed on the insulating layer ILD and electrically connected to the channel layer CHe. The source Se is electrically connected to the second data line DL3.

The third active device T3 includes a semiconductor layer CHf, a gate Gf, a source S and a drain Df. The gate Gf is electrically connected to the drain De of the third switching element SE 3. The gate Gf overlaps the channel layer CHf with the insulating layer GI interposed therebetween. The insulating layer ILD covers the gate Gf. The source Sf and the drain Df are disposed on the insulating layer ILD and electrically connected to the channel layer CHf. The source Sf is electrically connected to the first power line PL1.

The third light emitting diode L3 is located on the flat layer PL. In some embodiments, the third light emitting diode L3 is electrically connected to the source Sf and the second power line PL2 through the pad PD5 and the pad PD6, respectively. In the present embodiment, the position of the first active device T1 relative to the first light emitting diode L1, the position of the second active device T2 relative to the second light emitting diode L2, and the position of the third active device T3 relative to the third light emitting diode L3 are different from each other, so that the first light emitting diode L1, the second active device T2, and the third active device T3 can be more easily disposed in the active area AR.

In some embodiments, the pads PD 1-PD 6 are multi-layered structures, for example, the pads PD 1-PD 6 each include a first conductive layer CL1, a second conductive layer CL2, and a third conductive layer CL3. In some embodiments, the first conductive layer CL1 is a metal oxide (e.g., indium tin oxide), the second conductive layer CL2 is a metal (e.g., indium), and the third conductive layer CL3 is a metal (e.g., gold), but the invention is not limited thereto. In the embodiment, the first light emitting diode L1, the second light emitting diode L2 and the third light emitting diode L3 are inorganic light emitting diodes (e.g. micro-LEDs), but the invention is not limited thereto. In other embodiments, the first light emitting diode L1, the second light emitting diode L2, and the third light emitting diode L3 are organic light emitting diodes, electroluminescent devices, or other self-luminous devices.

In the present embodiment, in order that signal lines transmitting different signals are not shorted to each other, each signal line selectively includes different layers of conductive layers, and the different layers of conductive layers are electrically connected to each other through the via hole V.

In the present embodiment, the semiconductor layer CHb of the first active device T1, the semiconductor layer CHd of the second active device T2, and the semiconductor layer CHf of the third active device T3 are disposed in the active region AR instead of the peripheral region PR around the active region AR, so that the problem of the frame Mura caused by the failure of the stretchable substrate 20 after stretching can be avoided.

In the present embodiment, the first active device T1, the second active device T2 and the third active device T3 are respectively and directly electrically connected to the first light emitting diode L1, the second light emitting diode L2 and the third light emitting diode L3, so that the quality of the first active device T1, the second active device T2 and the third active device T3 has a larger influence on the display screen than the first switching device SE1, the second switching device SE2 and the third switching device SE 3. In some embodiments, based on the limitation of the wiring space, the first active device T1, the second active device T2, and the third active device T3, the first switching device SE1, the second switching device SE2, and the third switching device SE3 are not all disposed in the active area AR, and the first active device T1, the second active device T2, and the third active device T3 are preferably disposed in the active area AR, so that the problem that the retractable substrate 20 has a screen Mura after being stretched can be better improved, but the invention is not limited thereto. In other embodiments, if the wiring space is sufficient, the first active element T1, the second active element T2, and the third active element T3, the first switching element SE1, the second switching element SE2, and the third switching element SE3 are all disposed in the active region AR.

Fig. 4 is a schematic top view of a retractable substrate according to an embodiment of the invention, wherein fig. 4 shows the semiconductor layer of the first active device T1 in the first sub-pixel SP1, the semiconductor layer of the second active device T2 in the second sub-pixel SP2, and the semiconductor layer of the third active device T3 in the third sub-pixel SP3, and omits other components in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

It should be noted that the embodiment of fig. 4 uses the element numbers and part of the contents of the embodiments of fig. 3A to 3E, where the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.

Referring to fig. 4, in the present embodiment, the shape of the second active device T2 of the retractable substrate 30 is different from the shape of the first active device T1 and the shape of the third active device T3. For example, the semiconductor layer of the second active device T2 is different from the semiconductor layer of the first active device T1 and the semiconductor layer of the third active device T3. In the present embodiment, the semiconductor layer of the second active device T2 is substantially in a straight shape, and the semiconductor layers of the first active device T1 and the third active device T3 are substantially in an L shape. The semiconductor layer is L-shaped or bent, so that the stress applied to the semiconductor layer can be dispersed, and adverse effects on the electrical property of the semiconductor layer caused by strain or stress are reduced.

In some embodiments, each device portion 200 is rectangular in length L and width W, the width W1 of the peripheral region PR is 16% W to 40% W in the direction of the width W of each device portion 200, and the width W2 of the peripheral region PR is 16% L to 40% L in the direction of the length L of each device portion 200.

Based on the above, the semiconductor layer of the first active device T1, the semiconductor layer of the second active device T2, and the semiconductor layer of the third active device T3 are disposed in the active region AR instead of the peripheral region PR around the active region AR, so that the problem that the retractable substrate 30 fails after being stretched and causes the frame Mura can be avoided.

Fig. 5 is a schematic top view of a retractable substrate according to an embodiment of the invention, wherein fig. 5 shows the semiconductor layer of the first active device T1 in the first sub-pixel SP1, the semiconductor layer of the second active device T2 in the second sub-pixel SP2, and the semiconductor layer of the third active device T3 in the third sub-pixel SP3, and omits other components in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

It should be noted that the embodiment of fig. 5 uses the element numbers and part of the contents of the embodiments of fig. 3A to 3E, where the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.

Referring to fig. 5, in the present embodiment, the shape of the second active device T2 of the retractable substrate 40 is different from the shape of the first active device T1 and the shape of the third active device T3. For example, the semiconductor layer of the second active device T2 is different from the semiconductor layer of the first active device T1 and the semiconductor layer of the third active device T3. In the present embodiment, the semiconductor layers of the first active device T1 and the third active device T3 are substantially in the shape of a straight bar, and the semiconductor layer of the second active device T2 is substantially in the shape of an S.

The semiconductor layer is S-shaped or bent, so that the stress applied to the semiconductor layer can be dispersed, and adverse effects on the electrical property of the semiconductor layer caused by strain or stress are reduced.

The semiconductor layer with longer length has smaller current under the same voltage difference. In the present embodiment, the semiconductor layer of the second active device T2 is longer, and may be disposed corresponding to the blue sub-pixel. The semiconductor layers of the first active device T1 and the third active device T3 have shorter lengths and may be disposed corresponding to the red sub-pixel and the green sub-pixel, respectively.

Based on the above, the semiconductor layer of the first active device T1, the semiconductor layer of the second active device T2, and the semiconductor layer of the third active device T3 are disposed in the active region AR instead of the peripheral region PR around the active region AR, so that the problem that the retractable substrate 40 fails after being stretched and causes the frame Mura can be avoided.

Claims

1. A retractable substrate, comprising:

patterning the substrate;

a plurality of device parts located on the patterned substrate, wherein each device part comprises an active region and a peripheral region surrounding the active region, and each device part comprises a first active element and a second active element arranged in the active region; and

a plurality of circuit parts which are positioned on the patterned substrate and are connected with the corresponding device parts; and

a plurality of connecting parts arranged on the patterned substrate and adjacent to the corresponding circuit parts,

the patterning substrate is provided with a plurality of through holes, and one of the through holes is at least surrounded by four device parts.

2. The retractable substrate of claim 1, wherein the peripheral region has a width of 10 microns to 250 microns.

3. The retractable base of claim 1, wherein each device portion comprises:

a first sub-pixel including the first active device and a first light emitting diode directly electrically connected to the first active device;

a second sub-pixel including a second active device and a second light emitting diode directly electrically connected to the second active device; and

a third sub-pixel including a third active device and a third light emitting diode directly electrically connected to the third active device, wherein the second sub-pixel is located between the first sub-pixel and the third sub-pixel; and is also provided with

Each circuit part comprises at least one signal wire which is electrically connected to the corresponding first sub-pixel, the corresponding second sub-pixel and/or the corresponding third sub-pixel.

4. The retractable substrate of claim 3, wherein the shape of the semiconductor layer of the second active device is different from the shape of the semiconductor layer of the first active device and the shape of the semiconductor layer of the third active device.

5. The retractable substrate of claim 3, wherein the first active device is positioned with respect to the first light emitting diode, the second active device is positioned with respect to the second light emitting diode, and the third active device is positioned with respect to the third light emitting diode.

6. The retractable base of claim 1, wherein each device portion is rectangular with a length L and a width W, wherein:

the width of the peripheral region is 16 to 40% w in the width direction of each device portion

The width of the peripheral region is 16% L to 40% L in the direction of the length of each device portion.

7. The retractable substrate of claim 1, wherein each of the connection portions comprises a plurality of reinforcing structures arranged in sequence.

8. The retractable base plate of claim 1, wherein each of the through holes is dumbbell-shaped.