CN113778684A - Multi-information-source-oriented FPGA and CPU data synchronization device and method - Google Patents
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Abstract
The invention discloses a multi-information-source-oriented FPGA and CPU data synchronization device and a method, wherein the device comprises an FPGA unit and a CPU, data interaction is carried out between the FPGA unit and the CPU through a communication bus, and a certain IO pin of the FPGA unit is connected with an interrupt special pin of the CPU; the FPGA unit comprises n data cache regions, a change judgment module, a change mark interval timing convergence module, interrupt clearing logic, an interrupt register counter, interrupt shielding logic, an interrupt signal generation module and bus interface logic; the bus interface is used for realizing the function of data interaction with the CPU, on one hand, the data of the data cache region is reported to the CPU through the bus interface, and on the other hand, the command of the CPU can also be issued to the FPGA through the bus interface. Compared with the traditional method, the synchronization method reduces the number of the interrupt pins of the CPU, reduces the times of generating the interrupt signals, improves the efficiency of the CPU, ensures that the interrupt signals are not lost, and further ensures the integrity of data.
Description
Technical Field
The invention belongs to the technical field of FPGA and embedded technology, in particular to a multi-information-source-oriented FPGA and CPU data synchronization device and method.
Background
At present, most embedded systems are designed by adopting an architecture of FPGA + CPU, and methods for synchronizing data of FPGA and CPU mainly comprise a query-based mode and an interrupt-based mode. The mode based on the query is that a CPU periodically accesses a data cache region in the FPGA, and the mode has low efficiency and cannot realize real-time data synchronization. The interruption-based mode is that interruption is generated when the data of the FPGA changes, and the CPU accesses the data cache region in the FPGA after receiving an interruption signal, so that the working efficiency of the CPU is improved, and the real-time performance of data synchronization is higher. As embedded systems become more complex in design, more and more information sources are needed for data acquisition. In the traditional interrupt-based FPGA and CPU data synchronization method, an interrupt pin is configured for each information source, and after the CPU receives an interrupt signal, a data cache region corresponding to the interrupt is accessed, so that data synchronization is realized. When the number of information sources needing data acquisition is large, the traditional method has two problems. On one hand, the number of interrupt pins of the CPU is limited, and when there are many information sources, one interrupt pin cannot be configured for each information source. On the other hand, the data of each information source has the characteristics of burstiness, randomness and independence, so that the CPU frequently enters an interrupt processing program, the efficiency of the CPU is reduced, and the interrupt loss is easy to generate.
Disclosure of Invention
The invention provides a multi-information-source-oriented FPGA and CPU data synchronization device and method aiming at the defects of the prior art, is applied to a multi-information-source data acquisition system, realizes data synchronization of the FPGA and the CPU, and solves the problems of insufficient number of interrupt pins and too frequent interrupt triggering in the traditional method.
The invention relates to a multi-information-source-oriented FPGA and CPU data synchronization device, which comprises an FPGA unit and a CPU, wherein the FPGA unit and the CPU carry out data interaction through a communication bus, and a certain IO pin of the FPGA unit is connected with an interrupt special pin of the CPU.
The FPGA unit comprises n data cache regions, a change judgment module, a change mark interval timing convergence module, interrupt clearing logic, an interrupt register counter, interrupt shielding logic, an interrupt signal generation module and a bus interface;
the data buffer area is used for buffering the data reported by each information source;
the change judgment module is used for judging the data in the data cache region in real time and generating a corresponding change mark when the data changes;
the interval timing convergence module detects whether the change marks from the n data cache regions are effective or not in a time interval delta t, and if one or more change marks are effective, corresponding interrupt marks are generated at the tail of the time interval delta t;
the interrupt clear logic is used for receiving an interrupt clear command sent by the CPU and generating a corresponding interrupt clear mark;
after the CPU finishes an interrupt processing program, an interrupt clearing command is sent through a bus interface;
the interrupt register counter is used for registering the interrupt mark, 1 is added to the interrupt register counter when the interval timing convergence module generates one interrupt mark, and 1 is subtracted from the interrupt register counter when the interrupt clear logic generates one interrupt clear mark;
the interrupt shielding logic is used for interrupt shielding control, the CPU enters an interrupt service processing program after receiving an interrupt signal, and simultaneously sends an interrupt shielding command through a bus interface, and the interrupt shielding signal is effective; after the CPU finishes the interrupt service processing program, an interrupt shielding removing command is sent through the bus interface, and at the moment, an interrupt shielding signal is invalid;
the interrupt signal generating module is used for generating an interrupt signal which meets the time sequence requirement of the CPU, and generating the interrupt signal when the interrupt shielding signal is invalid and the interrupt register counter is not zero;
the bus interface is used for realizing the function of data interaction with the CPU, on one hand, the data of the data cache region is reported to the CPU through the bus interface, and on the other hand, the command of the CPU can also be issued to the FPGA through the bus interface.
The invention also aims to provide a multi-information-source-oriented FPGA and CPU data synchronization method, which comprises an FPGA processing flow and a CPU processing flow.
The FPGA processing flow comprises the following steps:
s101, caching data of an external information source by a data cache region of the FPGA, and for n information sources, allocating n data cache regions;
s102, carrying out change judgment on data in a data cache region in real time, and generating a corresponding change mark for the cache region with data conversion;
s103, setting a certain time interval
If one or more change marks are detected to be effective in the time interval delta t, an interruption mark is generated at the end of the time interval delta t, and if the change marks are not detected to be effective, the method continues to wait until the change marks are effective;
s104, registering the generated interrupt marks, wherein each time one interrupt mark is generated, the interrupt register counter is increased by 1;
s105, if the interrupt mask signal is invalid and the value of the interrupt register counter is nonzero, generating an interrupt signal, if the interrupt mask signal is valid, suspending the interrupt signal generation process and waiting for the interrupt mask signal to be invalid;
s106, the FPGA receives the CPU interrupt shielding command, the interrupt shielding signal becomes effective, and the CPU is waited to finish the interrupt processing program;
s107, after the FPGA receives the interrupt clearing command, the interrupt clearing logic generates an interrupt clearing mark, an interrupt register counter is decreased by 1, and the current interrupt is cleared;
and S108, after the FPGA receives the command of releasing the interrupt shielding, the interrupt shielding signal output by the interrupt shielding logic becomes invalid.
The CPU processing flow comprises the following steps:
s201, after receiving an interrupt signal, a CPU sends an interrupt shielding command through a communication bus and forbids an FPGA from generating the interrupt signal during the interrupt processing service program;
s202, the CPU enters an interrupt service program, and reads data in n data cache regions through a communication bus to realize data synchronization of the FPGA and the CPU;
s203, after finishing the interrupt processing service program, the CPU sends an interrupt clearing command to the FPGA;
and S204, sending an interrupt mask removing command to the FPGA.
The synchronization device of the invention carries out interval timing convergence on the change marks from a plurality of information sources, and combines a plurality of change marks in each interval into a single interrupt mark, thereby solving the problem of data synchronization of the FPGA and the CPU under the condition of a plurality of information sources. Compared with the traditional method, the synchronization method reduces the number of the interrupt pins of the CPU, reduces the times of generating the interrupt signals, improves the efficiency of the CPU, ensures that the interrupt signals are not lost, and further ensures the integrity of data.
Drawings
FIG. 1 is a schematic diagram of an FPGA and CPU data synchronization device according to the present invention;
FIG. 2 is a FPGA processing flow chart of the FPGA and CPU data synchronization method of the present invention;
FIG. 3 is a CPU processing flow chart of the FPGA and CPU data synchronization method of the present invention;
fig. 4 is a schematic diagram of the time of change of the source data and the time of occurrence of each change flag and interrupt flag in the embodiment.
Detailed Description
The present invention will be further described with reference to the following examples and drawings, but the present invention is not limited thereto.
Examples
A multi-information source oriented FPGA and CPU data synchronizer is shown in figure 1 and comprises an FPGA unit and a CPU, wherein the FPGA unit and the CPU carry out data interaction through a communication bus, and a certain IO pin of the FPGA unit is connected with an interrupt special pin of the CPU;
the FPGA unit comprises n data cache regions, a change judgment module, a change mark interval timing convergence module, interrupt clearing logic, an interrupt register counter, interrupt shielding logic, an interrupt signal generation module and bus interface logic;
the bus interface is used for realizing the function of data interaction with the CPU, on one hand, the data of the data cache region is reported to the CPU through the bus interface, and on the other hand, the command of the CPU can also be issued to the FPGA through the bus interface.
In this embodiment, assuming that the number of information sources n =5, a time interval is set
Is assumed to be
In the interval, the data of the information source 1, the information source 2, the information source 3, and the information source 5 are changed, and the time when the data are changed is as shown in fig. 4, it is assumed that the current interrupt register counter has a value of 0.
The invention relates to a multi-information-source-oriented FPGA and CPU data synchronization method, which comprises an FPGA processing flow and a CPU processing flow. As shown in fig. 2, the FPGA processing flow includes the following specific steps:
s101, caching data of an external information source by a data cache region of the FPGA, and allocating 5 data cache regions for 5 information sources;
s102, carrying out change judgment on data in the data buffer area in real time, generating corresponding change marks for the buffer area with data conversion, and carrying out change judgment at time intervals
When data of the internal information source 1, the information source 2, the information source 3 and the information source 5 changes, the change flag 1 is valid at the time of data change of the information source 1, the change flag 2 is valid at the time of data change of the information source 2, the change flag 3 is valid at the time of data change of the information source 3, and the change flag 5 is valid at the time of data change of the information source 5. Data of the information source 4 at time intervals
If there is no change, the change flag 4 is invalid, as shown in fig. 4;
s103, in time interval
In the time interval, if 4 change flags are detected to be valid
The tail end of the internal circuit generates an interrupt mark;
s104, registering the generated interrupt marks, wherein when one interrupt mark is generated, the interrupt register counter is increased by 1, the value of the interrupt register counter is changed into 1, and 1 interrupt signal needs to be generated and processed;
s105, if the CPU does not enter the interrupt service program, the interrupt mask signal is invalid, and the value of the interrupt register counter is 1, which is a non-zero value, the interrupt signal generating module generates an interrupt signal meeting the time sequence requirement of the CPU;
s106, the FPGA receives the CPU interrupt shielding command, the interrupt shielding signal becomes effective, and the CPU is waited to finish the interrupt processing program;
s107, after the FPGA receives the interrupt clear command, the interrupt clear logic generates an interrupt clear mark, the interrupt register counter is decreased by 1, the current interrupt is cleared, the value of the interrupt register counter is changed into 0, and the fact that no interrupt signal needs to be generated currently is indicated;
and S108, after the FPGA receives the command of releasing the interrupt shielding, the interrupt shielding signal output by the interrupt shielding logic becomes invalid.
The CPU processing flow, as shown in fig. 3, includes the following specific steps:
s201, after receiving an interrupt signal, a CPU sends an interrupt shielding command through a communication bus and forbids an FPGA from generating the interrupt signal during the interrupt processing service program;
s202, the CPU enters an interrupt service program, and reads data in 5 data cache regions through a communication bus to realize data synchronization of the FPGA and the CPU;
s203, after finishing the interrupt processing service program, the CPU sends an interrupt clearing command to the FPGA;
and S204, sending an interrupt mask removing command to the FPGA.
The data synchronization method of the invention gathers the data change marks of a plurality of information sources into an interrupt source by adopting interval timing, thereby reducing the occupation of the number of CPU interrupt pins, reducing the times of CPU entering interrupt and improving the working efficiency of the CPU.
Claims (3)
1. The utility model provides a FPGA and CPU data synchronizer towards many information sources, includes FPGA unit and CPU, its characterized in that:
the FPGA unit and the CPU carry out data interaction through a communication bus; one IO pin of the FPGA unit is connected with an interrupt special pin of the CPU;
the FPGA unit comprises n data cache regions, a change judgment module, a change mark interval timing convergence module, interrupt clearing logic, an interrupt register counter, interrupt shielding logic, an interrupt signal generation module and a bus interface;
the bus interface is used for realizing the function of data interaction with the CPU, and on one hand, the data of the data cache region is reported to the CPU through the bus interface; on the other hand, the command of the CPU can also be issued to the FPGA through the bus interface.
2. The FPGA and CPU data synchronization device of claim 1, wherein:
the data buffer area of the FPGA unit is used for buffering the data reported by each information source;
the change judgment module is used for judging the data in the data cache region in real time and generating a corresponding change mark when the data changes; the interval timing convergence module detects whether the change marks from the n data cache regions are effective or not within a time interval delta t, and if one or more change marks are effective, corresponding interrupt marks are generated at the tail of the time interval delta t;
the interrupt clear logic is used for receiving an interrupt clear command sent by the CPU and generating a corresponding interrupt clear mark;
after the CPU completes an interrupt processing program, an interrupt clearing command is sent through an interface bus;
the interrupt register counter is used for registering the interrupt mark, 1 is added to the interrupt register counter when the interval timing convergence module generates one interrupt mark, and 1 is subtracted from the interrupt register counter when the interrupt clear logic generates one interrupt clear mark;
interrupt mask logic is used for interrupt mask control;
after receiving the interrupt signal, the CPU enters an interrupt service processing program and simultaneously sends an interrupt shielding command through a bus interface, wherein the interrupt shielding signal is effective;
after the CPU finishes the interrupt service processing program, an interrupt shielding removing command is sent through the bus interface, and at the moment, an interrupt shielding signal is invalid;
the interrupt signal generating module is used for generating an interrupt signal which meets the time sequence requirement of the CPU, and generating the interrupt signal when the interrupt shielding signal is invalid and the interrupt register counter is not zero.
3. The data synchronization method of the FPGA and CPU data synchronization device according to any one of claims 1-2, characterized in that:
the method comprises an FPGA processing flow and a CPU processing flow;
the FPGA processing flow comprises the following steps:
s101, caching data of an external information source by a data cache region of the FPGA, and for n information sources, allocating n data cache regions;
s102, carrying out change judgment on data in a data cache region in real time, and generating a corresponding change mark for the cache region with data conversion;
s103, setting a certain time interval, generating an interruption mark at the end of the time interval if one or more change marks are detected to be effective in the time interval, and continuing waiting until the change marks are effective if the change marks are not detected to be effective;
s104, registering the generated interrupt marks, wherein each time one interrupt mark is generated, the interrupt register counter is increased by 1;
s105, if the interrupt mask signal is invalid and the value of the interrupt register counter is nonzero, generating an interrupt signal, if the interrupt mask signal is valid, suspending the interrupt signal generation process and waiting for the interrupt mask signal to be invalid;
s106, the FPGA receives the CPU interrupt shielding command, the interrupt shielding signal becomes effective, and the CPU is waited to finish the interrupt processing program;
s107, after the FPGA receives the interrupt clearing command, the interrupt clearing logic generates an interrupt clearing mark, an interrupt register counter is decreased by 1, and the current interrupt is cleared;
s108, after the FPGA receives the command of releasing the interrupt shielding, the interrupt shielding signal output by the interrupt shielding logic becomes invalid;
the CPU processing flow comprises the following steps:
s201, after receiving an interrupt signal, a CPU sends an interrupt shielding command through a communication bus and forbids an FPGA from generating the interrupt signal during the interrupt processing service program;
s202, the CPU enters an interrupt service program, and reads data in n data cache regions through a communication bus to realize data synchronization of the FPGA and the CPU;
s203, after finishing the interrupt processing service program, the CPU sends an interrupt clearing command to the FPGA;
and S204, sending an interrupt mask removing command to the FPGA.
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