CN113765512A - Digital circuit device and voltage drop detection circuit - Google Patents

Abstract

The present application relates to digital circuit devices and voltage drop detection circuits. The digital circuit device comprises a power supply circuit system, a digital circuit system and a protection circuit system. The power supply circuitry outputs a supply voltage. The digital circuit system is driven by the supply voltage and executes at least one operation according to a first clock signal. The protection circuitry generates a first clock signal based on at least one of a voltage drop of the supply voltage and a load signal issued from the digital circuitry.

Description

Digital circuit device and voltage drop detection circuit

Technical Field

The present invention relates to a digital circuit device, and more particularly, to a digital circuit device with auto-power regulation and a voltage drop (voltage drop) detection circuit thereof.

Background

In practical applications, digital circuit devices need to be over-designed (over design) at circuit design time in order to function properly under variations in various process parameters, temperatures and/or voltages. For example, during the time of performing high computation density operations or power switching, the voltage variation inside the digital circuit device may exceed 20% of the predetermined value. To tolerate this voltage variation, the design of the digital circuit device needs to be over-constrained. However, this approach may result in more power consumption and/or larger circuit area.

Disclosure of Invention

In some embodiments, the digital circuit device includes power supply circuitry, digital circuitry, and protection circuitry. The power supply circuit system is used for outputting a supply voltage. The digital circuit system is driven by the supply voltage and executes at least one operation according to a first clock signal. The protection circuit system is used for generating the first clock signal according to at least one of a voltage drop of the supply voltage and a load signal sent from the digital circuit system.

In some embodiments, the voltage drop detection circuit includes a first flip flop (flip flop) circuit, a plurality of first delay circuits (delay), a plurality of second delay circuits, a logic gate circuit, and a second flip flop circuit. The first flip-flop circuit is used for outputting an enable signal as a test signal according to a clock signal. The first delay circuits are driven by the supply voltage and delay the test signal to generate flag signals, wherein the flag signals are read in response to a refresh signal to indicate a voltage drop of the supply voltage. The plurality of second delay circuits are driven by the supply voltage and delay the test signal to generate a first signal. The logic gate circuit is used for generating a second signal according to the first signal and a control signal. The second flip-flop circuit is used for outputting the second signal as the updating signal according to the clock signal.

The features, implementations, and functions of the present application are described in detail below with reference to the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram of a digital circuit arrangement shown in accordance with some embodiments of the present application;

FIG. 2 is a schematic diagram illustrating the protection circuitry of FIG. 1 according to some embodiments of the present application;

FIG. 3A is a schematic diagram illustrating the voltage drop detection circuit of FIG. 2 according to some embodiments of the present application;

FIG. 3B is a schematic diagram illustrating the voltage drop detection circuit of FIG. 2 according to some embodiments of the present application;

FIG. 4 is a schematic diagram illustrating the clock masking circuit of FIG. 2 according to some embodiments of the present application;

FIG. 5A is a schematic diagram illustrating the protection circuitry of FIG. 1 according to some embodiments of the present application;

FIG. 5B is a flow chart illustrating operations performed by the frequency adjustment circuit of FIG. 5A according to some embodiments of the present application; and

fig. 6 is a schematic diagram illustrating the protection circuitry of fig. 1 according to some embodiments of the present application.

Detailed Description

All terms used herein have their ordinary meaning. The above definitions of words and phrases are generally used in dictionary and the use of any and all examples of the present invention, including any and all terms discussed herein, are intended to be exemplary and should not be construed to limit the scope or spirit of the present invention. Likewise, the present application is not limited to the various embodiments shown in this specification.

As used herein, coupled or connected means that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or that two or more elements are in mutual operation or action. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuitry" may be a device connected by at least one transistor and/or at least one active and passive component in a certain manner to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. As used herein, the term "at least one of a and B" includes any combination of one or more of the associated listed items (a and B). The terms first, second, third and the like are used herein to describe and distinguish between various components. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the present application. For ease of understanding, similar components in the various drawings will be designated with the same reference numerals.

Fig. 1 is a schematic diagram illustrating a digital circuit arrangement 100 according to some embodiments of the present application. The digital circuit device 100 includes power supply circuitry 110, digital circuitry 120, protection circuitry 130, and clock generation circuitry 140. The power supply circuitry 110 generates a supply voltage DVDD and a supply voltage AVDD. In some embodiments, the supply voltage DVDD drives (i.e., powers) digital circuits in the digital circuitry 120 and the protection circuitry 130, while the supply voltage AVDD drives analog circuits in the protection circuitry 130. In some embodiments, the power supply circuitry 110 includes a low dropout regulator (LDO) circuit 112 and an LDO circuit 114. LDO circuit 112 generates a supply voltage DVDD, and LDO circuit 114 generates a supply voltage AVDD.

Digital circuitry 120 includes at least one digital circuit (e.g., a processor circuit, a flip-flop circuit, a logic gate, etc.). The at least one digital circuit can be protected by the protection circuit system 130 to avoid voltage variation abnormality caused by instantaneous large current variation inside the circuit. The digital circuit system 120 is based on the clock signal CK_1-At least one operation is executed. For example, flip-flop circuits in the digital circuitry 120 may be based on the clock signal CK_1--An operation to transfer data is performed. Alternatively, the processor circuit in the digital circuitry 120 may be based on the clock signal CK_1--An algorithm is executed. The above description of at least one type of operation is provided for purposes of example and is not intended to limit the present disclosure. When at least one circuit in the digital circuitry 120 performs the at least one operation, the output and/or conduction state of the at least one circuit is switched.

In some embodiments, the digital circuit system 120 further issues the load signal S according to the operating condition_LIndicating that the digital circuitry 120 is to operate at heavy or light loads. The description herein will be described later with reference to fig. 5A and 5B.

The protection circuit system 130 is based on the clock signal CK₀Generating a clock signal CK₁. The protection circuit system 130 further generates a load signal S according to the voltage drop of the supply voltage DVDD_LAt least one of the adjusted clock signals CK₁. In this way, the protection circuitry 130 can prevent the transient current of the digital circuitry 120 from changing too much, so as to keep the operating voltage of the digital circuitry 120 stable. The operation of the protection circuitry 130 will be described later with reference to the drawings. Clock generation circuitry 140 provides clock signal CK₀. In some embodiments, clock generation circuitry140 may be implemented by, but is not limited to, a Phase-locked Loop (Phase-locked Loop) circuit.

Fig. 2 is a schematic diagram illustrating the protection circuitry 130 of fig. 1 according to some embodiments of the present application. In this example, the protection circuitry 130 adjusts the clock signal CK according to the voltage drop of the supply voltage DVDD₁. The protection circuitry 130 includes a voltage drop detection circuit 220 and a clock masking circuit 240. The voltage drop detection circuit 220 is coupled to the LDO circuits 112 and 114 of fig. 1 to receive the supply voltage DVDD and the supply voltage AVDD. The voltage drop detection circuit 220 can continuously detect the voltage drop of the supply voltage DVDD according to the enable signal EN and the clock signal CK₀Triggered to output multiple flag signals S [0]]～S[31]And the refresh signal S_U。

The clock masking circuit 240 is responsive to the refresh signal S_UAnd a plurality of flag signals S [0]]～S[31]Adjusting clock signal CK₀To generate a clock signal CK₁. For example, if a plurality of flag signals S [0]]～S[31]In turn '00111111111111111111111111111111', the clock masking circuit 240 can be based on a plurality of flag signals S [0]]～S[31]The number of logic values 0 (2 in this example) in the self-clock signal CK₀Masking off the corresponding number of pulse waves (pulse), and adjusting the clock signal CK₀Output as clock signal CK_1-. Thus, if the voltage DVDD begins to drop, the protection circuitry 130 can adjust the clock signal CK₁The number of pulses to reduce the number of switching times in the digital circuitry 120. In this manner, the current increase of the digital circuitry 120 may be reduced, thereby also reducing the voltage drop of the supply voltage DVDD.

Fig. 3A is a schematic diagram illustrating the voltage drop detection circuit 220 of fig. 2 according to some embodiments of the present application. The voltage drop detection circuit 220 includes a flip-flop circuit 301, a plurality of delay circuits 302, a plurality of delay circuits 303, a logic gate circuit 304, and a flip-flop circuit 305. In this example, the delay circuit 302, the delay circuit 303, and the logic gate 304 are digital circuits. The flip-flop circuit 301 generates a clock signal CK according to the clock signal CK₀Outputting the enable signal EN as the test signal S_T。

Delay circuit 302 and delayLate circuit 303 is driven by supply voltage DVDD. In some embodiments, the delay time introduced by the single delay circuit 302 in fig. 3A is set to be longer than the delay time introduced by the single delay circuit 303, and the sensitivity of the single delay circuit 302 to voltage is greater than the sensitivity of the single delay circuit 303 to voltage. In other words, when the voltage drop of the supply voltage DVDD increases, the delay time of the single delay circuit 302 increases by an amount larger than that of the single delay circuit 303. For example, each delay circuit 302 may be implemented by a standard cell (standard cell) having a high threshold voltage (threshold voltage), and each delay circuit 303 may be implemented by a standard cell having a low threshold voltage (i.e., the threshold voltage of the delay circuit 302 is higher than the threshold voltage of the delay circuit 303). In some embodiments, the standard cells may include, but are not limited to, inverters, flip-flops, AND (AND) gates, OR (OR) gates. The plurality of delay circuits 302 are coupled in series to form a first delay chain circuit, and the plurality of delay circuits 303 are coupled in series to form a second delay chain circuit. In the present embodiment, the total delay time T of the first delay chain circuit_D1Set to be the same as the total delay time T of the second delay chain circuit_D2. Therefore, the number of delay circuits 303 is larger than the number of delay circuits 302. The above embodiments related to the delay circuit 302 and the delay circuit 303 are used for illustration, and the application is not limited thereto.

In an initial state (e.g., when the enable signal EN is at logic value 0), the flip-flop circuit 301 is reset, and resets the outputs of the delay circuits 302 and 303 to a first logic value (e.g., logic value 0). Then, the flip-flop circuit 301 generates a clock signal CK₀Outputting an enable signal EN having a second logic value (e.g., logic value 1) as a test signal S_T. The plurality of delay circuits 302 delay the test signal S_TTo generate a plurality of flag signals S [0] respectively]～S[31]. The plurality of delay circuits 303 delay the test signal S_TTo generate a signal S₁. The logic gate circuit 304 is used for generating a second logic value according to the signal S₁And a control signal S_PDGenerating a signal S₂. Equivalently, when the test signal S_TWhen passing through all the delay circuits 303 to the logic gate circuit 304, the logic gate circuit 304 can generate the signal S₂. In some embodiments, the control signal S_PDMay be the enable signal EN AND the logic gate 304 may be implemented as an AND gate. The flip-flop circuit 305 generates a clock signal CK according to the clock signal CK₀-converting the signal S₂Output as the update signal S with the second logic value_U。

As previously mentioned, the total delay time T_D1Is set to be the same as the total delay time T_D2. When the test signal S_TWhen passing to the logic gate circuit 304, the logic gate circuit 304 can generate the signal S₂And the flip-flop circuit 305 outputs the refresh signal S accordingly_U. If the voltage drop of the supply voltage DVDD is sufficiently low, the total delay time T_D1Will be approximately the same as the total delay time T_D2. Under this condition, the update signal S having the second logic value_U-When generated, a plurality of flag signals S [0]]～S[31]Are all the second logic values. If the voltage drop of the supply voltage DVDD is higher (i.e., the lower the supply voltage DVDD becomes), the operation speed of the delay circuit 302 and the delay circuit 303 is slower. Since the delay circuit 302 is designed differently from the delay circuit 303, the delay circuit 303 increases the delay time at a slower rate when the voltage drops. Under this condition, the total delay time T_D1Will be greater than the total delay time T_D2. Therefore, the update signal S having the second logic value_U-When generated, a part of the flag signal S [0]]～S[31]May still be the first logical value.

In this way, the update signal S can be responded to_UReading a plurality of flag signals S [0]]～S[31]To detect a voltage drop of the supply voltage DVDD. For example, when updating the signal S_UWhen the second logic value is set, a plurality of flag signals S [0]]～S[31]The relationship with the voltage drop of the supply voltage DVDD can be shown as follows:

as can be seen from the above table, the lower the voltage drop of the supply voltage DVDD, the greater the number of second logic values (e.g., logic value 1) in the plurality of flag signals S [0] to S [31 ]. Conversely, the higher the voltage drop of the supply voltage DVDD, the smaller the number of second logic values. Therefore, a plurality of flag signals S [0] S [31] can be used to indicate the voltage drop of the supply voltage DVDD.

Fig. 3B is a schematic diagram illustrating the voltage drop detection circuit 220 of fig. 2 according to other embodiments of the present application. The voltage drop detection circuit 220 in fig. 3B includes a buffer circuit 311, a capacitor C, an amplifier circuit 312, an analog-to-digital converter (ADC) circuit 313, a memory circuit 314, a plurality of flip-flop circuits 315, and a flip-flop circuit 316. In this example, the voltage drop detection circuit 220 includes an analog circuit (e.g., a portion of the amplifier circuit 312 and/or the ADC circuit 313) that can be driven by the supply voltage AVDD (not shown). The remaining digital circuit portion may be driven by a supply voltage DVDD (not shown).

The capacitor C is coupled to the output terminal of the buffer circuit 311. The buffer circuit 311 outputs a reference voltage VREF according to the supply voltage DVDD. The amplifier circuit 312 amplifies a difference (corresponding to a voltage drop of the supply voltage DVDD) between the supply voltage DVDD and the reference voltage VREF to generate the signal S_AAnd a control signal S_PD. For example, the amplifier circuit 312 may be implemented by a fully differential amplifier to generate the signal S according to the supply voltage DVDD and the reference voltage VREF_AAnd a control signal S_PD。

The ADC circuit 313 outputs the signal S_AConversion to digital code S_DWhich may be used to indicate the voltage drop of the supply voltage VDD. The memory circuit 314 stores a look-up table (e.g., the table shown previously). The memory circuit 314 may be based on the digital code S_DSelecting a plurality of corresponding control codes S from the lookup table_BAnd outputs a plurality of control codes S_BTo a plurality of flip-flop circuits 315. Multiple flip-flop circuits 315 can be driven by the clock signal CK₀A plurality of control codes S_BRespectively output as a plurality of flag signals S [0]]～S[31]. The flip-flop circuit 316 can be based on the clock signal CK₀Will control signal S_PDOutput as the update signal S_U。

Fig. 4 is a schematic diagram illustrating the clock masking circuit 240 of fig. 2 according to some embodiments of the present application. The clock masking circuit 240 includes a plurality of selection circuits 410[0]]～410[31]And a clock gating circuit 420. Multiple selection circuits 410[0]～410[31]-coupled in series and sequentially generating a plurality of signals S₄₁Signal S₄₂…, signal S₄₃₂. To select circuit 410[0]]For example, selection circuit 410[0]]Receiving the last 1 signal S₄₃₂And flag signal S [0]]And according to the update signal S_UWill signal S₄₃₂OR flag signal S [0]Output as signal S₄₁. To select circuit 410[ 1]]For example, selection circuit 410[ 1]]Receives a signal from the previous stage selection circuit 410[0]]A preamble signal S of₄₁And flag signal S [ 1]]And according to the update signal S_UWill signal S₄₁Or flag signal S [ 1]]Output as signal S₄₂. By analogy, multiple selection circuits 410[0] can be derived]～410[31]The arrangement of each.

Multiple selection circuits 410[0]～410[31]Each comprising a multiplexer circuit 411 and a flip-flop circuit 412. To select circuit 410[0]]For example, in selection circuit 410[0]]In the multiplexer circuit 411, according to the refresh signal S_UOutput signal S₄₃₂OR flag signal S [0]Output as a corresponding signal S₃. In selection circuit 410[0]In the flip-flop circuit 412, according to the clock signal CK₀Will correspond to the signal S₃Output as signal S₄₁. In the various embodiments described above, the flip-flop circuits 301,305, 315,316 and 412 may be, but are not limited to, D-type flip-flops.

The clock gating circuit 420 may be driven by the supply voltage AVDD to reduce the effect of voltage drops. The clock gating circuit 420 is based on the last signal S₄₃₂Adjusting clock signal CK₀To generate a clock signal CK₁. For example, when the signal S₄₃₂When the clock gating circuit 420 has the first logic value, the clock gating circuit does not output the clock signal CK₀The pulse wave of (2). Thus, the clock signal CK₁One pulse will be masked. When the signal S₄₃₂When the clock gating circuit 420 outputs the clock signal CK with the second logic value₀The pulse wave of (A) is a clock signal CK₁. In some embodiments, the clock gating circuit 420 may be implemented by, but is not limited to, an Integrated Clock Gating (ICG) circuit unit.

Fig. 5A is a schematic diagram illustrating the protection circuitry 130 of fig. 1 according to further embodiments of the present application. In this example, the protection circuitry 130 is responsive to the load signal S_LAdjusting clock signal CK₁. As described above, the digital circuit system 120 can determine the load signal S according to the operating condition_LIndicating that the digital circuitry 120 is to operate at heavy or light loads. For example, when an arithmetic processing circuit (not shown) or firmware of the digital circuitry 120 predicts that the computation strength is going to be high (e.g., to perform a fast fourier transform), the digital circuitry 120 may output the load signal S with a logic value 1_LTo indicate that a reload is to be entered. Alternatively, when a power management circuit (not shown) of the digital circuit system 120 knows that the digital circuit system 120 is switched from the standby mode to the busy mode, the digital circuit system 120 may output the load signal S having a logic value of 1_LTo indicate that a reload is to be entered. Alternatively, when a clock switch circuit (not shown) of the digital circuit system 120 knows that more clock signals are needed for the current operation, the digital circuit system 120 can output the load signal S with logic value 1_LTo indicate that a reload is to be entered.

The protection circuitry 130 in fig. 5A includes a frequency adjustment circuit 510 and a frequency divider circuit 520. The frequency adjustment circuit 510 adjusts the frequency according to the load signal S_LDetermining a control ratio S_R. The operation of this will be described later with reference to fig. 5B. The frequency-dividing circuit 520 is controlled according to the control ratio S_RAnd clock signal CK₀Generating a clock signal CK₁. For example, the clock signal CK₀The frequency of which is f 1. The frequency divider 520 can be driven by the clock signal CK₀Generating a clock signal CK having a frequency f2₁Wherein the frequency f2 is f1/S_R。

Fig. 5B is a flowchart illustrating operations performed by the frequency adjustment circuit 510 of fig. 5A according to some embodiments of the present application. In some embodiments, the frequency adjustment circuit 510 may be implemented by a state machine (state machine) or a digital signal executing operations S503 to S506 of fig. 5BA controller circuit implementation. As described above, if the digital circuitry 120 predicts that the operating condition will switch from light load to heavy load, the digital circuitry 120 outputs the load signal S having a second logic value (e.g., logic value 1)_L(operation S501). Alternatively, if the digital circuitry 120 predicts that the operating condition will switch from a heavy load to a light load, the digital circuitry 120 outputs the load signal S having a first logic value (e.g., logic value 0)_L(operation S502).

In response to the load signal S having a second logic value_LThe frequency adjustment circuit 510 decrements the control ratio S_R(operation S503). If the load signal S_LMaintaining the second logic value, the frequency adjustment circuit 510 decreases the control ratio S_RTo a predetermined minimum value (for example, 1), and controlling the ratio S_RIs maintained at the preset minimum value (operation S504). In other words, when the digital circuitry 120 is going to be overloaded, the protection circuitry 130 can clock the CK signal₁Gradually increases in frequency.

In response to a load signal S having a first logic value_LThe frequency adjustment circuit 510 increases the control ratio S_R(operation S505). If the load signal S_LThe frequency adjustment circuit 510 increases the control ratio S while maintaining the first logic value_RTo a predetermined maximum value (e.g., 64, 128, etc.), and controlling the ratio S_RIs maintained at the preset maximum value (operation S506). In other words, when the digital circuitry 120 is going to enter a light load, the protection circuitry 130 may clock the CK signal₁Gradually decreases in frequency. By the above operation, the protection circuitry 130 can provide the clock signal CK to the protection circuitry 130 when the operating conditions of the digital circuitry 120 are predictably changed₁Gradually increases/decreases to avoid too large transient current variations in the digital circuitry 120.

Fig. 6 is a schematic diagram illustrating the protection circuitry 130 of fig. 1 according to some embodiments of the present application. In this example, the protection circuitry 130 drops the voltage and/or the load signal S according to the supply voltage DVDD_LAdjusting clock signal CK₁. The protection circuitry 130 includes a voltage drop detection circuit 220, a clock mask circuitPath 240, frequency adjustment circuit 510, and frequency divider circuit 520. In this embodiment, with reference to fig. 2 and fig. 5A-5B, the frequency divider 520 divides the clock signal CK₂Output to the clock masking circuit 240, and the clock masking circuit 240 masks the clock signal CK₁Output to digital circuitry 120. That is, the frequency dividing circuit 520 is based on the clock signal CK₀And the control ratio S_RGenerating a clock signal CK₂And the clock shielding circuit 240 is based on the refresh signal S_UAnd a plurality of flag signals S [0]]～S[31]Adjusting clock signal CK₂To generate a clock signal CK₁. The detailed configuration of the circuits can refer to the embodiments, and will not be repeated herein.

In summary, the digital circuit device provided in some embodiments of the present application can adjust the power consumption of the digital circuit system in real time by detecting the voltage drop of the supply voltage and/or according to the predetermined operating condition, so as to protect the digital circuit system from abnormality. Thus, the design constraints of the digital circuitry can be relaxed. Furthermore, the voltage drop detection circuit provided by some embodiments of the present application is implemented by a fully digital circuit, which saves circuit area and power consumption compared to the common analog circuit approach in the field.

Although the embodiments of the present application have been described above, many embodiments are not intended to limit the present application, and one skilled in the art can apply variations to the technical features of the present application according to the explicit or implicit contents of the present application, and any such variations may fall within the scope of the patent protection sought by the present application, in other words, the scope of the patent protection sought by the present application should be determined by the scope of the patent application defined in the present specification.

[ notation ] to show

100 digital circuit device

110 power supply circuit system

112,114 Low dropout regulator (LDO) Circuit

120 digital circuit system

130 protection circuit system

140 clock generation circuitry

AVDD, DVDD supply voltage

CK₀、CK₁Clock signal

S_LLoad signal

220 voltage drop detection circuit

240 clock shielding circuit

EN enable signal

Flag signals S0-S31

S_UUpdate signal

301,305 flip-flop circuit

302,303 delay circuit

304 logic gate circuit

S₁,S₂Signal

S_PDControl signal

S_TTest signals

T_D1,T_D2Total delay time

311 buffer circuit

312 amplifier circuit

313 analog-to-digital converter (ADC) circuit

314 memory circuit

315,316 flip-flop circuit

C is capacitor

S_ASignal

S_BControl code

S_DDigital code

VREF reference voltage

410[0] to 410[31] -, selection circuit

411 multiplexer circuit

412 flip-flop circuit

420 clock gating circuit

S₃,S₄₁～S₄₃₂Signal

510 frequency adjusting circuit

520 frequency eliminating circuit

S_RControl the ratio

S501-S506 operation

CK₂A clock signal.

Claims (10)

1. A digital circuit device, comprising:

a power supply circuit system for outputting a supply voltage;

a digital circuit system, driven by the supply voltage, for performing at least one operation according to a first clock signal; and

a protection circuit system for generating the first clock signal according to at least one of a voltage drop of the supply voltage and a load signal emitted from the digital circuit system.

2. The digital circuit device of claim 1, wherein the protection circuitry comprises:

a voltage drop detection circuit for detecting the voltage drop and generating a plurality of flag signals and a refresh signal according to an enable signal and a second clock signal; and

a clock masking circuit for adjusting the second clock signal according to the plurality of flag signals and the update signal to generate the first clock signal.

3. The digital circuit device of claim 2, wherein the voltage drop detection circuit comprises:

a first flip-flop circuit for outputting the enable signal as a test signal according to the second clock signal;

a plurality of first delay circuits driven by the supply voltage and delaying the test signal to generate the plurality of flag signals;

a plurality of second delay circuits driven by the supply voltage and delaying the test signal to generate a first signal;

a logic gate circuit for generating a second signal according to the first signal and a control signal; and

a second flip-flop circuit for outputting the second signal as the refresh signal according to the second clock signal.

4. The digital circuit device of claim 3, wherein an amount of an increase in a delay time of each of the plurality of first delay circuits is greater than an amount of an increase in a delay time of each of the plurality of second delay circuits as the voltage drop increases.

5. The digital circuit device of claim 3, wherein a total delay time of the plurality of first delay circuits is the same as a total delay time of the plurality of second delay circuits.

6. The digital circuit device according to claim 3, wherein each of the plurality of first delay circuits has a first threshold voltage, each of the plurality of second delay circuits has a second threshold voltage, and the first threshold voltage is higher than the second threshold voltage.

7. The digital circuit device of claim 2, wherein the clock masking circuit comprises:

a plurality of selection circuits coupled in series and configured to sequentially generate a plurality of first signals, wherein one of the plurality of selection circuits is configured to output a corresponding one of the plurality of flag signals or a leading signal of the plurality of first signals as a second signal according to the update signal, and output the second signal as a corresponding one of the plurality of first signals according to the second clock signal; and

a clock gating circuit for adjusting the second clock signal according to a last first signal of the plurality of first signals to generate the first clock signal.

8. The digital circuit device of claim 1, wherein the protection circuitry comprises:

a frequency adjusting circuit for determining a control ratio according to the load signal, wherein the frequency adjusting circuit is used for increasing the control ratio to a preset maximum value according to the load signal or decreasing the control ratio to a preset minimum value according to the load signal; and

a frequency divider for generating the first clock signal according to the control ratio and a second clock signal.

9. The digital circuit device of claim 1, wherein the protection circuitry comprises:

a voltage drop detection circuit for detecting the voltage drop and generating a plurality of flag signals and a refresh signal according to an enable signal and a second clock signal;

a frequency adjusting circuit for determining a control ratio according to the load signal;

a frequency divider for generating a third clock signal according to the control ratio and the second clock signal; and

a clock masking circuit for adjusting the third clock signal according to the plurality of flag signals and the update signal to generate the first clock signal.

10. A voltage drop detection circuit, comprising:

a first flip-flop circuit for outputting an enable signal as a test signal according to a clock signal;

a plurality of first delay circuits driven by a supply voltage and delaying the test signal to generate a plurality of flag signals, wherein the plurality of flag signals are read in response to a refresh signal to indicate a voltage drop of the supply voltage;

a plurality of second delay circuits driven by the supply voltage and delaying the test signal to generate a first signal;

a logic gate circuit for generating a second signal according to the first signal and a control signal; and

a second flip-flop circuit for outputting the second signal as the refresh signal according to the clock signal.

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