CN113763896B - Driving circuit, display panel and device - Google Patents
Driving circuit, display panel and device Download PDFInfo
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- CN113763896B CN113763896B CN202110933961.8A CN202110933961A CN113763896B CN 113763896 B CN113763896 B CN 113763896B CN 202110933961 A CN202110933961 A CN 202110933961A CN 113763896 B CN113763896 B CN 113763896B
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- 230000002159 abnormal effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
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- 230000009286 beneficial effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 208000014674 injury Diseases 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application discloses a driving circuit, a display panel and a display device. The driving circuit comprises a plurality of array substrate row driving circuits, each array substrate row driving circuit comprises an initial driving signal input end and a plurality of array substrate row driving units which are sequentially cascaded, and each array substrate row driving circuit can independently receive the initial driving signals, so that the corresponding pixel array can be independently driven to work. The application solves the problem that the whole display panel has to be scrapped when the row driving unit of one row of array substrate is damaged, and improves the production yield of the display panel.
Description
Technical Field
The present application relates to the field of electronic circuits, and more particularly, to a driving circuit, a display panel, and a display device.
Background
The Array substrate row driving (Gate Driver on Array, GOA) is a process technology for directly manufacturing a Gate driving circuit (Gate driver IC) on an Array (Array) substrate of a display device, instead of a Gate driving chip manufactured by an external silicon chip, for driving a pixel Array row by row.
The array substrate row driving circuit comprises a plurality of rows of array substrate row driving units which are arranged in a cascading manner, when the array substrate row driving circuit actually works, the first row of array substrate row driving units work after receiving a frame Start Signal (STV), the first row of array substrate row driving units output driving signals to the next row of array substrate row driving units, when each row of array substrate row driving unit stage downwards receives the driving signals output by the array substrate row driving units in the previous row, the corresponding pixel array in the display panel is driven to work, the driving signals are transmitted to the input ends of the array substrate row driving units in the next row, namely, the driving signals are transmitted between the array substrate row driving units step by step, and the work of each array substrate row driving unit depends on the work of the array substrate row driving units in the previous row.
In the actual production or application process, the row driving units of one row of the array substrate are damaged due to static impact or other processing factors, and at this time, the driving signals cannot be transmitted to the row driving units of the next row of the array substrate by the damaged row driving units of the array substrate, so that the whole row driving circuit of the array substrate cannot work. In this case, the display panel is generally only scrapped, resulting in a high defective rate of the display panel.
Disclosure of Invention
The main object of the present application is to provide a driving circuit, which is capable of independently driving each array substrate row driving circuit by arranging a plurality of array substrate row driving circuits of a display panel driving circuit and respectively outputting a start driving signal. Therefore, when the array substrate row driving unit of a certain row is damaged by static electricity injury or other processing factors, only the array substrate row driving circuit comprising the array substrate row driving unit cannot work, and other array substrate row driving circuits which are independently driven still can receive the initial driving signals and work, so that the part of the display panel corresponding to the other array substrate row driving circuits can be kept for continuous use, and the reject ratio of the production of the display panel is reduced.
In order to achieve the above object, the present application provides a driving circuit, which includes an array substrate row driving circuit, the array substrate row driving circuit is connected with a timing control circuit and receives a start driving signal output by the timing control circuit, the number of the array substrate row driving circuits is plural, and each of the array substrate row driving circuits includes:
the initial driving signal input end is used for accessing the initial driving signal;
and the array substrate row driving units are used for driving corresponding pixel arrays in the display panel to work when receiving driving signals output by the first preset row of array substrate row driving units in connection, and transmitting the driving signals to the input ends connected with the second preset row of array substrate row driving units.
In an embodiment, the timing control circuit is configured to sequentially output the corresponding start driving signal to each array substrate row driving circuit according to a preset first set delay time.
In one embodiment, a plurality of the array substrate row driving circuits are arranged in cascade.
In an embodiment, the number of array substrate row driving units of each array substrate row driving circuit is N rows;
the input end of the first row of array substrate row driving units in the N rows of array substrate row driving units is connected with the initial driving signal input end, and the input ends of the second to N rows of array substrate row driving units are connected with the third preset row of array substrate row driving units.
In an embodiment, each of the array substrate row driving circuits further includes:
and the redundant array substrate row driving unit is connected with the N-th row of the array substrate row driving unit.
In one embodiment, each of the array substrate row driving circuits includes:
the array substrate comprises a first subarray substrate row driving circuit and a second subarray substrate row driving circuit, wherein the first subarray substrate row driving circuit and the second subarray substrate row driving circuit are used for respectively scanning the pixel array from two sides of the pixel array.
The application also provides a driving circuit, which comprises an array substrate row driving circuit, wherein the array substrate row driving circuit is connected with the time sequence control circuit and receives an initial driving signal output by the time sequence control circuit, the number of the array substrate row driving circuits is two, namely a first array substrate row driving circuit and a second array substrate row driving circuit, and each array substrate row driving circuit comprises:
the initial driving signal input end is used for accessing the initial driving signal;
the array substrate comprises a plurality of rows of array substrate row driving units which are sequentially cascaded, wherein the input ends of the array substrate row driving units in the first row of the array substrate row driving units are connected with the initial driving signal input end, and each row of the array substrate row driving units are used for driving a corresponding pixel array in a display panel to work when receiving driving signals which are output by the first preset row of the array substrate row driving units in a connecting way and transmitting the driving signals to the input ends which are output by the second preset row of the array substrate row driving units in a connecting way;
the time sequence control circuit is used for sequentially outputting corresponding initial driving signals to the first array substrate row driving circuit and the second array substrate row driving circuit according to a preset second set delay time;
the second preset delay time is a time required by the first array substrate row driving circuit to scan the pixel array row by row after receiving the initial driving signal.
The present application also proposes a display panel comprising: color film substrate, liquid crystal layer and array substrate; the liquid crystal layer is arranged between the array substrate and the color film substrate;
the array substrate comprises an effective display area and an inactive display area, wherein the inactive display area surrounds the periphery of the effective display area, and the driving circuit is arranged in the inactive display area of the array substrate.
The application also provides a display device which is characterized by comprising a backlight module, a time sequence control board and the display panel;
the time sequence control circuit is arranged on the time sequence control board and is connected with the driving circuit.
In one embodiment, the timing control circuit includes:
the time sequence control circuit is arranged on the time sequence control board and is used for outputting an initial driving signal;
the first level shifter is arranged on the time sequence control board and on one side of the time sequence control circuit, the input end of the first level shifter is connected with the time sequence control circuit, the output end of the first level shifter is respectively connected with the first subarray substrate row driving circuit of each array substrate row driving circuit, and the first level shifter is used for carrying out level conversion on the initial driving signal and then outputting the initial driving signal;
the second level shifter is arranged on the time sequence control board and is arranged on one side of the time sequence control circuit, which is away from the first level shifter; the input end of the second level shifter is connected with the time sequence control circuit, the output end of the second level shifter is respectively connected with the second subarray substrate row driving circuit of each array substrate row driving circuit, and the second level shifter is used for outputting the initial driving signal after level conversion.
The technical scheme of the application comprises a plurality of array substrate row driving circuits, wherein each array substrate row driving circuit comprises an initial driving signal input end and can independently receive an initial driving signal. Therefore, when a certain row of array substrate row driving units are damaged by static electricity injury or other processing factors, only the array substrate row driving circuits comprising the row of array substrate row driving units cannot work, and other array substrate row driving circuits still can receive the initial driving signals and work, so that the parts of the display panel corresponding to the other array substrate row driving circuits can be kept for continuous use, and the reject ratio of the production of the display panel is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a first circuit diagram of a driving circuit according to an embodiment of the application;
FIG. 2 is a second circuit diagram of a driving circuit according to an embodiment of the application;
FIG. 3 is a third circuit diagram of a driving circuit according to an embodiment of the application;
FIG. 4 is a schematic structural diagram of a display panel according to a second embodiment of the application;
fig. 5 is a schematic structural diagram of a display device according to a third embodiment of the application.
Reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
In the present application, unless specifically stated and limited otherwise, the terms "connected," "affixed," and the like are to be construed broadly, and for example, "affixed" may be a fixed connection, a removable connection, or an integral body; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present application.
The application provides a driving circuit which can effectively reduce the reject ratio in the production process of a display panel.
Embodiment one:
referring to fig. 1, the present application discloses a driving circuit, which comprises array substrate row driving circuits (21, 22), wherein the array substrate row driving circuits (21, 22) are connected with a timing control circuit 10 and receive a start driving signal output by the timing control circuit 10; wherein the number of the array substrate row driving circuits (21, 22) is plural, and each of the array substrate row driving circuits (21, 22) includes:
the initial driving signal input end is electrically connected with the time sequence control circuit 10 and is used for accessing the initial driving signal;
the array substrate driving units (211-21 x, 221-22 y) are sequentially cascaded, the input ends of the array substrate driving units (211, 221) of the first row of the array substrate driving units are connected with the initial driving signal input end, and each row of the array substrate driving units (212-21 x, 222-22 y) is used for driving a corresponding pixel array 30 in the display panel to work when receiving driving signals output by the first preset row of the array substrate driving units, and transmitting the driving signals to the input end connected with the second preset row of the array substrate driving units.
The first preset row array substrate row driving unit may be any row array substrate row driving unit above the current row array substrate row driving unit, and the embodiment may be selected as the row array substrate row driving unit above the current row array substrate row driving unit. The second preset row array substrate row driving unit may be any row array substrate row driving unit below the current row array substrate row driving unit, and in this embodiment, the next row array substrate row driving unit of the current row array substrate row driving unit may be selected.
The number of array substrate row driving units in each array substrate row driving circuit is not limited. The number of array substrate row driving units of different array substrate row driving circuits may be equal or unequal. Referring to fig. 1, when the driving circuit is operated, the first row of the array substrate row driving unit 211 of the array substrate row driving circuit drives the corresponding pixel array 30 to operate when receiving the start driving signal, and outputs the driving signal to the next row of the array substrate row driving unit 212, and when the array substrate row driving unit 212 receives the driving signal, drives the corresponding pixel array 30 in the display panel to operate, and transmits the driving signal to the input end of the next row of the array substrate row driving unit (not shown in the figure), and the above steps are circulated until the array substrate row driving unit 21x receives the driving signal. Similarly, when the array substrate row driving unit 221 receives the start driving signal, the driving signals are sequentially transferred between the array substrate driving units 212 to 21 y.
Wherein the number of array substrate row driving circuits (21, 22) may be 2 or more. This embodiment is optional for 2. Therefore, the relation between the product yield and the production cost can be well balanced, the yield of the display panel is improved, and the cost increase caused by excessive number of array substrate row driving circuits can be avoided.
The Start signal driving signal, also referred to as a Start Vertical (STV), may be configured by configuring a program of the timing control circuit 10 such that the timing control circuit 10 sequentially outputs the Start signal driving signal to each of the array substrate row driving circuits (21, 22), thereby independently driving each of the array substrate row driving circuits (21, 22). For example, the plurality of array substrate row driving circuits may be sequentially arranged, and the timing control circuit 10 sequentially outputs the start driving signal to the plurality of array substrate row driving circuits (21, 22) according to the arrangement order of the plurality of array substrate row driving circuits (21, 22) so as to control the plurality of array substrate row driving circuits to sequentially operate. In addition, the timing control circuit 10 outputs a timing control signal, a low frequency signal to each array substrate row driving unit of each array substrate row driving circuit (21, 22).
According to the technical scheme, the array substrate row driving circuits (21 and 22) are arranged, each array substrate row driving circuit (21 and 22) comprises an initial driving signal input end so as to independently receive an initial driving signal, and dependence on a previous-stage array substrate row driving circuit is eliminated (the array substrate row driving circuit 22 can work without outputting a driving signal by the array substrate row driving circuit 21). Therefore, when a certain row of array substrate row driving units is damaged by static electricity injury or other processing factors, only the array substrate row driving circuits comprising the row of array substrate row driving units cannot work at the moment, and other independently driven array substrate row driving circuits (21, 22) can still receive the initial driving signals and work, so that the parts of the display panels corresponding to the other array substrate row driving circuits (21, 22) can be kept for continuous use. For example, when the array substrate row driving unit 211 is damaged, only the array substrate row driving circuit 21 is affected to fail to operate. The array substrate row driving circuit 22 can independently receive the start driving signal and operate, so that the corresponding display panel part can be reserved. Thereby reducing the defective rate of the display panel production.
In practical application, after the display panel is manufactured, a plurality of test points are arranged on the display panel to detect the display panel, test signals are respectively provided for each array substrate row driving unit through the test points, and whether each array substrate row driving unit has an output signal is judged. If yes, the corresponding array substrate row driving circuit to be tested can be determined to work normally, and if not, the array substrate row driving circuit can be determined to be abnormal. And when all the array substrate row driving circuits can work normally, the display panel can pass detection. When the abnormal state of the row driving circuit of a certain array substrate is determined, the part corresponding to the damaged row driving circuit of the array substrate in the display panel can be cut off, other parts of the display panel are reserved for continuous use, the scrapping of the whole display panel is avoided, and the reject ratio of the production of the display panel is effectively reduced.
Referring to fig. 1, the timing control circuit 10 is configured to sequentially output the corresponding start driving signals to each of the array substrate row driving circuits (21, 22) according to a preset first set delay time.
The first preset delay time is set, so that all array substrate row driving circuits (21, 22) can work sequentially, and only one-stage array substrate row driving circuit works at any moment. In other words, all the array substrate row driving units in the entire driving circuit can sequentially operate to scan the pixel array 30 row by row.
The time interval between two adjacent initial driving signals is equal to the time required by the line-by-line scanning of the array substrate line driving circuit after the previous initial driving signal in the two adjacent initial driving signals is output to the array substrate line driving circuit. For example, referring to fig. 1, when the timing control circuit 10 outputs the start driving signal to the array substrate row driving circuit 21, the time required for the start driving signal to be transferred from the array substrate row driving unit 211 to the array substrate row driving unit 21x is the time interval between the time when the timing control circuit outputs the start driving signal to the array substrate row driving circuit 21 and the array substrate row driving circuit 22.
Referring to fig. 1, the number of array substrate row driving units of each of the array substrate row driving circuits is N rows.
The input ends of the first row array substrate row driving units (211, 221) in the N rows of array substrate row driving units are connected with the initial driving signal input ends. The input ends of the second to N-th row array substrate row driving units (212 to 21x, 222 to 22 y) are connected with the third preset row array substrate row driving units (the previous row array substrate row driving units or the previous N row array substrate row driving units) so as to realize the transmission of driving signals.
The third preset row array substrate row driving unit may be any row array substrate row driving unit above the current row array substrate row driving unit, and the embodiment may be selected as the row array substrate row driving unit above the current row array substrate row driving unit.
In this embodiment, the number of array substrate row driving units by providing each array substrate row driving circuit (21, 22) is N, that is, the same. In this way, the time required for the array substrate row driving units inside each array substrate row driving circuit to transfer the driving signals from the first row array substrate row driving unit to the last row array substrate row driving unit is the same. Therefore, the timing control circuit 10 only needs to sequentially output the initial driving signals to each array substrate row driving circuit according to the preset delay time T, so that the plurality of array substrate row driving circuits sequentially and continuously work, and further the pixel units in the display area of the display panel are driven to work row by row, so that the picture displayed by the display panel is normally displayed. Wherein T is the time required for transmitting the start driving signal in the N rows of array substrate row driving units.
Referring to fig. 2, each of the array substrate row driving circuits further includes: and the redundant array substrate row driving units (21N, 22N), wherein the redundant array substrate row driving units (21N, 22N) are connected with reset signal input ends of the N-th row of the array substrate row driving units (21 x, 22 y).
In this embodiment, each row of the array substrate row driving units is configured to, when receiving a driving signal output by a previous row of the array substrate row driving units, drive a corresponding pixel array 30 in the display panel to operate, and transmit the driving signal to an input end of a next row of the array substrate row driving units, and output a reset signal to the previous row of the array substrate row driving units. Therefore, the array substrate row driving unit in each array substrate row driving circuit can reset automatically after working. However, the array substrate row driving units (21 x, 22 y) on the nth row have no next row of array substrate row driving units, so that a reset signal cannot be received for resetting.
The redundant array substrate row driving units (21N, 22N) of the present embodiment do not drive the pixel array 30 to operate, but output a reset signal to the nth row of the array substrate row driving units (21 x, 22 y) when receiving the driving signal, so as to reset the nth row of the array substrate row driving units (21 x, 22 y). Thus, in this embodiment, each array substrate row driving unit can be reset.
Referring to fig. 2, a plurality of the array substrate row driving circuits are arranged in cascade. That is, the first stage array substrate row driving unit (211, 221) of each array substrate row driving circuit not only receives the start driving signal through the start driving signal input terminal, but also can be connected (e.g. 21 x) with the last stage array substrate row driving unit of the previous stage array substrate row driving circuit to receive the driving signal output by the last stage array substrate row driving unit. For example, referring to fig. 2, the first row array substrate row driving unit 221 of the array substrate row driving unit 22 may not only receive the start driving signal through the start driving signal input terminal, but also be connected to the last row array substrate row driving unit 21x of the array substrate row driving unit 21 and receive the driving signal transmitted from the array substrate row driving unit 21 x.
In this way, in practical application, if it is determined that any one or more of the array substrate row driving units is abnormal during the detection of the display panel, the portion of the display panel corresponding to the array substrate row driving circuit where the array substrate row driving unit is located may be cut and removed, and the portion of the display panel corresponding to the other array substrate row driving circuit is reserved for continuous use.
When it is confirmed that all the array substrate row driving units are abnormal, the software program written by the timing control circuit 10 may be configured to output only one start driving signal to the first row array substrate row driving unit 211 of the first stage array substrate row driving circuit 21, so as to simplify the software program written by the timing control circuit 10.
Of course, when it is confirmed that all the array substrate row driving units are abnormal, the software program written by the timing control circuit 10 may still be configured to sequentially output a plurality of start driving signals. Each array substrate row driving circuit (21, 22) may receive the start driving signal and the driving signal outputted from the upper stage array substrate row driving circuit at the same time. And enters into operation upon receiving either one of the start drive signal and the drive signal. Therefore, the yield of the display panel can be improved, and the connection of the row driving circuits of the adjacent two-stage array substrates can be ensured to be timely enough, so that the picture display is smoother.
Referring to fig. 3, each of the array substrate row driving circuits includes:
first and second sub-array substrate row driving circuits (21 a, 22a, 21b, 22 b) for scanning the pixel array 30 from both sides of the pixel array 30, respectively.
It should be noted that, in some large-sized display panels, since the pixel array 30 in the panel has a region far from the array substrate row driving circuit and a region near the array substrate row driving circuit, the line loss is different between the two regions, and the line loss when the region near the array substrate row driving circuit is driven (receives the gate driving signal) is much smaller than the region far from the array substrate row driving circuit. This tends to cause uneven pixel charging in the pixel array 30 in the area of the array substrate row driving circuit and the area close to the array substrate row driving circuit, thereby causing uneven brightness of the display panel.
In this embodiment, the first sub-array substrate row driving circuits (21 a, 22 a) and the second sub-array substrate row driving circuits (21 b, 22 b) are used for scanning the pixel array 30 from two sides of the pixel array 30 respectively, so as to realize bilateral driving, shorten the transmission path of signals, and further reduce transmission loss, so that the brightness display of the display panel is more uniform.
Referring to fig. 1, a driving circuit is proposed, the driving circuit includes an array substrate row driving circuit (21, 22), the array substrate row driving circuit (21, 22) is connected with a timing control circuit 10, and receives a start driving signal outputted by the timing control circuit 10; wherein the number of the array substrate row driving circuits (21, 22) is plural, each of the array substrate row driving circuits includes:
the initial driving signal input end is electrically connected with the time sequence control circuit 10 and is used for accessing the initial driving signal;
the array substrate comprises a plurality of rows of array substrate row driving units (211-21 x, 221-22 y) which are sequentially cascaded, wherein the input ends of the array substrate row driving units (211, 221) of the first row of the array substrate row driving units are connected with the initial driving signal input end, and each row of the array substrate row driving units are used for driving a corresponding pixel array 30 in a display panel to work when receiving a driving signal connected with the first preset row of the array substrate row driving units and transmitting the driving signal to the input end connected with the second preset row of the array substrate row driving units;
the timing control circuit 10 is configured to sequentially output corresponding start driving signals to the first array substrate row driving circuit 21 and the second array substrate row driving circuit 22 according to a preset second delay time, where the second preset delay time is a time required for the first array substrate row driving circuit 21 to scan the pixel array 30 line by line after receiving the start driving signals.
In this embodiment, two array substrate row driving circuits are provided, each of which includes an initial driving signal input end for accessing an initial driving signal, and the timing control circuit 10 is further provided to sequentially output corresponding initial driving signals to the first array substrate row driving circuit 21 and the second array substrate row driving circuit 22 according to a second preset delay time, so as to independently drive the two array substrate row driving circuits. When the array substrate row driving unit inside one array substrate row driving circuit is damaged, the operation of the other array substrate row driving circuit is not affected, and then the display panel corresponding to the other array substrate row driving circuit can be reserved for continuous use, so that the whole display panel is not scrapped, and the yield of the display panel is improved.
Embodiment two:
referring to fig. 4, a display panel is proposed, the display panel comprising: a color film substrate 3, a liquid crystal layer 2 and an array substrate 1; the liquid crystal layer 2 is arranged between the color film substrate 3 and the array substrate 1;
the array substrate 1 comprises an effective display area and an inactive display area, the inactive display area surrounds the periphery of the effective display area, and the driving circuit is arranged in the inactive display area of the array substrate.
The specific structure of the driving circuit refers to the above embodiments, and since the display panel adopts all the technical solutions of all the embodiments, the driving circuit has at least all the beneficial effects brought by the technical solutions of the embodiments, and will not be described in detail herein.
Embodiment III:
referring to fig. 5, a display device is disclosed, which includes a backlight module, a timing control board 4, and the display panel described above; the specific structure of the display panel refers to the above embodiments, and since the display device adopts all the technical solutions of all the embodiments, at least the display panel has all the beneficial effects brought by the technical solutions of the embodiments, and the details are not repeated here.
Wherein the timing control board 4 is provided with the timing control circuit 10 and source drivers (40 a and 40 b), and the timing control circuit is connected with the driving circuit. .
Referring to fig. 5, the timing control circuit 10 includes:
a timing control circuit 11 disposed on the timing control board 4, the timing control circuit 11 being configured to output a start driving signal;
a first level shifter 121 disposed on the timing control board 4 and disposed on one side of the timing control circuit 11, wherein an input end of the first level shifter 121 is connected to the timing control circuit 11, an output end of the first level shifter 121 is respectively connected to the first sub-array substrate row driving circuits (21 a, 22 a) of each of the array substrate row driving circuits, and the first level shifter 121 is configured to level-shift the start driving signal and output the start driving signal;
a second level shifter 122 provided on the timing control board 4 and provided on a side of the timing control circuit 11 facing away from the first level shifter 121; the input end of the second level shifter 122 is connected to the timing control circuit 11, the output end of the second level shifter 122 is respectively connected to the second sub-array substrate row driving circuits (21 b, 22 b) of each of the array substrate row driving circuits, and the second level shifter 122 outputs the start driving signal after performing level conversion.
In this embodiment, a delay may be provided inside the level shifter to access fewer signals while outputting more signals. Taking the level shifter output timing control signal as an example. The time sequence control circuit outputs a time sequence control signal to the level converter, and the level converter converts the time delay into 8 time sequence control signals to output.
Similarly, taking the example that the level shifter outputs the initial driving signal, the timing control circuit 11 outputs one path of initial driving signal to the level shifter, and the level shifter then delays and converts the initial driving signal to multiple paths of timing control signals (determined according to the number of the array substrate row driving circuits) for outputting.
The connection between the timing control board 4 and the display panel may be through flexible circuit boards on both sides of the timing control board. Thus, when there is only one level shifter (the level shifter is generally disposed on the upper side or the lower side of the timing control circuit), and the level shifter is required to output the multiple start driving signals, the multiple timing control signals, and other control signals to the first sub-array substrate row driving circuits (21 a, 22 a) and the second sub-array substrate row driving circuits (21 b, 22 b) at the same time. The routing of the multi-path timing control signal and the start driving signal to the left and right sides is necessarily very complex and has a crossover.
In view of this technical problem, in the present embodiment, the first level shifter 121 and the second level shifter 122 are disposed on both sides of the timing control circuit 11. Further, the first level shifter 121 and the second level shifter 122 are provided on both sides of the timing control board 4 near the position of the flexible circuit board. In this way, only one path of initial driving signal, one path of timing control signal and other paths of wires are arranged around the timing control circuit 11, so that the wires around the timing control circuit 11 are very simple, meanwhile, the multiple paths of initial driving signals and multiple paths of timing control signals output by the first level converter 121 and the second level converter 122 are directly output to the corresponding flexible circuit board, and no cross wires exist, thereby being beneficial to reducing the area of the timing control board 4, reducing the frame area of the display device and improving the screen occupation ratio of the display device
The foregoing description is only of the optional embodiments of the present application, and is not intended to limit the scope of the application, and all the equivalent structural changes made by the description of the present application and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the application.
Claims (9)
1. The driving circuit comprises an array substrate row driving circuit, wherein the array substrate row driving circuit is connected with a time sequence control circuit and receives an initial driving signal output by the time sequence control circuit; the array substrate row driving circuit is characterized in that the number of the array substrate row driving circuits is multiple, and each array substrate row driving circuit comprises:
the initial driving signal input end is used for accessing the initial driving signal;
the array substrate comprises a plurality of rows of array substrate row driving units which are sequentially cascaded, wherein the input end of a first row of array substrate row driving units in the plurality of rows of array substrate row driving units is connected with the initial driving signal input end, and each row of array substrate row driving units are used for driving a corresponding pixel array in a display panel to work when receiving a driving signal output by the connection of the last row of array substrate row driving units and transmitting the driving signal to the input end connected with the next row of array substrate row driving units;
the time sequence control circuit is used for sequentially outputting the corresponding initial driving signals to each array substrate row driving circuit according to a first preset delay time;
the number of array substrate row driving units of each array substrate row driving circuit is N rows;
the input end of the first row of array substrate row driving units in each array substrate row driving circuit is also connected with the last row of array substrate row driving units of the upper-stage array substrate row driving circuit, and each array substrate row driving circuit works when receiving the starting driving signals and/or the driving signals output by the last row of array substrate row driving units of the upper-stage array substrate row driving circuit.
2. The drive circuit of claim 1, wherein a plurality of the array substrate row drive circuits are arranged in cascade.
3. The driving circuit according to claim 1, wherein the input terminals of the second to nth rows of the array substrate row driving units among the N rows of the array substrate row driving units are connected to the respective corresponding upper row of the array substrate row driving units.
4. The drive circuit of claim 3, wherein each of the array substrate row drive circuits further comprises:
and the redundant array substrate row driving unit is connected with the N-th row of the array substrate row driving unit.
5. The drive circuit of claim 1, wherein each of the array substrate row drive circuits comprises:
the array substrate comprises a first subarray substrate row driving circuit and a second subarray substrate row driving circuit, wherein the first subarray substrate row driving circuit and the second subarray substrate row driving circuit are used for respectively scanning the pixel array from two sides of the pixel array.
6. The driving circuit comprises an array substrate row driving circuit, wherein the array substrate row driving circuit is connected with a time sequence control circuit and receives an initial driving signal output by the time sequence control circuit; the array substrate row driving circuit is characterized in that the number of the array substrate row driving circuits is two, namely a first array substrate row driving circuit and a second array substrate row driving circuit, and each array substrate row driving circuit comprises:
the initial driving signal input end is used for accessing the initial driving signal;
the array substrate comprises a plurality of rows of array substrate row driving units which are sequentially cascaded, wherein the input ends of the array substrate row driving units in the first row of the array substrate row driving units are connected with the initial driving signal input end, and each row of the array substrate row driving units are used for driving a corresponding pixel array in a display panel to work when receiving driving signals output by the connection of the array substrate row driving units in the last row and transmitting the driving signals to the input ends connected with the array substrate row driving units in the next row;
the number of array substrate row driving units of the first array substrate row driving circuit and the second array substrate row driving circuit is N rows;
the time sequence control circuit is used for sequentially outputting corresponding initial driving signals to the first array substrate row driving circuit and the second array substrate row driving circuit according to a second preset delay time;
the second preset delay time is the time required by the first array substrate row driving circuit to scan the pixel array row by row after receiving the initial driving signal;
the input end of the array substrate row driving unit of the first row in the second array substrate row driving circuit is also connected with the array substrate row driving unit of the last row in the first array substrate row driving circuit; the second array substrate row driving circuit works when receiving the initial driving signal and/or the driving signal output by the last row of array substrate row driving units of the first array substrate row driving circuit.
7. A display panel, the display panel comprising: color film substrate, liquid crystal layer and array substrate; the liquid crystal layer is arranged between the array substrate and the color film substrate;
the array substrate comprises an effective display area and an inactive display area, wherein the inactive display area surrounds the periphery of the effective display area, and the driving circuit according to any one of claims 1-6 is arranged in the inactive display area of the array substrate.
8. A display device, wherein the display device comprises a backlight module, a time sequence control board and the display panel according to claim 7;
the time sequence control circuit is arranged on the time sequence control board and is connected with the driving circuit.
9. The display device according to claim 8, wherein the timing control circuit includes:
the time sequence control circuit is arranged on the time sequence control board and is used for outputting an initial driving signal;
the first level shifter is arranged on the time sequence control board and on one side of the time sequence control circuit, the input end of the first level shifter is connected with the time sequence control circuit, the output end of the first level shifter is respectively connected with the first subarray substrate row driving circuit of each array substrate row driving circuit, and the first level shifter is used for carrying out level conversion on the initial driving signal and then outputting the initial driving signal;
the second level shifter is arranged on the time sequence control board and is arranged on one side of the time sequence control circuit, which is away from the first level shifter; the input end of the second level converter is connected with the time sequence control circuit, the output end of the second level converter is respectively connected with the second subarray substrate row driving circuit of each array substrate row driving circuit, and the second level converter is used for carrying out level conversion on the initial driving signals and then outputting the initial driving signals.
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