CN113763890B - Display system with backlight - Google Patents
Display system with backlight Download PDFInfo
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- CN113763890B CN113763890B CN202010484102.0A CN202010484102A CN113763890B CN 113763890 B CN113763890 B CN 113763890B CN 202010484102 A CN202010484102 A CN 202010484102A CN 113763890 B CN113763890 B CN 113763890B
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- backlight
- control signal
- display system
- frame rate
- backlit display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention relates to a display system with backlight. The display system includes: a panel having a plurality of pixels; a backlight driver for controlling an irradiation light of the backlight using the pulse width modulation control signal; and a timing controller synchronizing with the backlight driver through a synchronization control signal. When the frame rate deviates from the preset rate, a part of the pulse width modulation control signal is adjusted in the period of the synchronous control signal, and the frame rate represents the frequency of displaying the image on the panel. The display system of the present invention can avoid flicker when the frame rate is changed.
Description
Technical Field
The present invention relates to a display system, and more particularly, to a display system using local dimming.
Background
The Liquid Crystal Display (LCD) itself does not emit light, and a backlight (backlight) is required to provide illumination light to the liquid crystal display. The light source of the backlight may comprise a Light Emitting Diode (LED).
To enhance contrast (contrast), backlight dimming (dimming) techniques are used to dynamically control the brightness of the backlight. Global dimming is one of the technologies of backlight dimming, which simultaneously controls the brightness of the entire display panel. Global dimming may promote dynamic contrast (dynamic contrast) between adjacent frames (frames). Regional (local) dimming is another backlight dimming technique that controls the brightness of a portion of a display panel of a single frame. Local dimming may improve static contrast (static contrast).
Conventional dimming methods, particularly, the regional dimming method, have a problem of flicker (flicker) when the frame rate (frame rate) is changed. Therefore, a novel mechanism is needed to overcome the drawbacks of the conventional local dimming method.
Disclosure of Invention
In view of the above, it is an object of an embodiment of the present invention to provide a display system that can avoid flicker when the frame rate is changed.
According to an embodiment of the present invention, there is provided a display system with a backlight, including: a panel including a plurality of pixels; a backlight driver for controlling an irradiation light of the backlight using the pulse width modulation control signal; and a timing controller synchronizing with the backlight driver through a synchronization control signal; when the frame rate deviates from the preset rate, the synchronization of the backlight driver and the time schedule controller is maintained in the period of the synchronization control signal, the working period of the pulse width modulation control signal is set to be 100%, and the frame rate represents the frequency of displaying the image on the panel.
According to another embodiment of the present invention, there is provided a display system with backlight, including: a panel including a plurality of pixels; a backlight driver for controlling an irradiation light of the backlight using the pulse width modulation control signal; and a timing controller synchronizing with the backlight driver through a synchronization control signal; when the frame rate deviates from the preset rate, the synchronization of the backlight driver and the time sequence controller is not maintained in the period of the synchronization control signal, and the pulse width modulation frequency is maintained to be an integral multiple of the preset rate so as to enable the frame rate to return to the preset rate; the frame rate represents the frequency at which images are displayed on the panel.
According to another embodiment of the present invention, at least two different channels of the backlight are synchronized to different times during a period of the synchronization control signal when the frame rate deviates from the preset rate.
According to a further embodiment of the invention, at least two different channels of the backlight are illuminated at different times during a period of the synchronization control signal when the frame rate deviates from the preset rate.
Drawings
FIG. 1 is a block diagram of a display system according to an embodiment of the invention.
Fig. 2A illustrates a timing diagram of a synchronous control signal and a pwm control signal in a normal state.
Fig. 2B illustrates a timing diagram of the abnormal state synchronization control signal and the pwm control signal.
FIG. 3 is a flowchart of a method for avoiding backlight flicker according to an embodiment of the present invention.
Fig. 4 illustrates a timing diagram of an abnormal state synchronization control signal and a pwm control signal according to a first embodiment of the present invention.
Fig. 5 illustrates a timing diagram of an abnormal state synchronization control signal and a pwm control signal according to a second embodiment of the present invention.
Fig. 6A illustrates a timing diagram of an abnormal state synchronization control signal and a multi-pwm control signal according to a third embodiment of the present invention.
Fig. 6B illustrates a timing diagram of an abnormal state synchronization control signal and a multi-pwm control signal according to a third embodiment of the present invention.
Fig. 7 illustrates a timing diagram of an abnormal state synchronization control signal and a multi-pwm control signal according to a fourth embodiment of the present invention.
Fig. 8 illustrates a timing diagram of an abnormal state synchronization control signal and a multi-pwm control signal according to a fifth embodiment of the present invention.
Description of the reference numerals
100 display system
11 panel
12 Gate driver
13 source driver
14 timing controller
15 backlight
16 backlight driver
17 light modulation controller
300 method for avoiding backlight flicker
31 whether the frame rate deviates
32A maintaining synchronization
32B not maintaining synchronization
33 the working period is set to 100%
34 whether the frame rate is reverted to
35 the pulse width modulation frequency is an integer multiple of the preset rate
36 maintain duty cycle
37 whether the frame rate is greater than a preset rate
38A to reduce the pulse width modulation period
38B increasing pulse width modulation period
39 in synchronization with different times
40 irradiation at different times
Vsync-synchronization control signal
Detailed Description
FIG. 1 is a block diagram of a display system 100 according to an embodiment of the invention. The display system 100 (e.g., liquid crystal display) of the present embodiment may include a panel 11, a gate driver 12, a source driver 13, and a timing controller 14. The panel 11 may include a plurality of pixels arranged in a matrix form. The gate driver 12 is controlled by the timing controller 14 for sequentially turning on at least one row of pixels of the panel 11; the source driver 13 is controlled by the timing controller 14 for generating image signals to the corresponding row pixels of the opening row of the panel 11.
The display system 100 may also include a backlight 15 (e.g., a light emitting diode backlight) and a backlight driver 16. In the present embodiment, the backlight 15 may be a local dimming backlight, which is divided into a plurality of channels (or blocks), and is controlled by the backlight driver 16 to illuminate the panels 11 respectively. The backlight driver 16 may control the illumination light of the backlight 15 using a Pulse Width Modulation (PWM) control signal whose duty cycle represents a ratio of the illumination time to the entire period of the PWM control signal. The backlight driver 16 may be synchronized with the timing controller 14 by a synchronization control signal Vsync (e.g., a vertical synchronization signal). The frame rate (frame rate) represents the frequency of displaying images on the panel 11, and may be set by the synchronization control signal such that the frame rate is equal to the frequency of the synchronization control signal Vsync. It is noted that in the normal state, the frame rate is equal to the preset rate, and the frequency of the pwm control signal is an integer multiple of the frame rate.
Fig. 2A illustrates a timing diagram of a normal state synchronization control signal Vsync and a pulse width modulation control signal (e.g., duty cycle of 70%) of a channel. Wherein the frame rate is equal to the preset rate. Since the pwm frequency is an integer multiple of the frame rate, the backlight driver 16 can be normally synchronized with the timing controller 14.
Fig. 2B illustrates a timing diagram of the synchronization control signal Vsync and the pulse width modulation control signal (of one channel) in an abnormal state. Wherein the frame rate deviates from a preset rate (rate increase in this example). Even though the backlight driver 16 is still synchronized with the timing controller 14, the pwm frequency is no longer an integer multiple of the frame rate. Therefore, incomplete (partial) illumination light (diagonal line area as shown) occurs per frame. Accordingly, the long irradiation light and the short irradiation light alternate, and thus the eye perceives flickering.
According to one of the features of the present embodiment, a dimming controller 17 is provided, controlled by the backlight driver 16, for avoiding backlight flickering when the frame rate deviates from a preset rate. In one embodiment, the dimming controller 17 may be provided (but is not limited to) to the source driver 13. Fig. 3 is a flowchart of a method 300 for avoiding backlight flicker, which may be performed by the dimming controller 17.
In step 31, the frame rate is compared with a predetermined rate to determine whether the frame rate deviates from the predetermined rate. If the frame rate does not deviate from the predetermined rate (e.g., the difference between the frame rate and the predetermined rate is less than the predetermined threshold), normal (local) dimming operation is maintained, i.e., the backlight driver 16 is synchronized with the timing controller 14 and the pwm frequency (of the pwm control signal) is an integer multiple of the frame rate. If the frame rate deviates from the preset rate in step 31, indicating that an abnormal state occurs, the flow proceeds to step 32A or 32B.
Fig. 4 illustrates a timing diagram of an abnormal state synchronization control signal Vsync and a (one-channel) pwm control signal according to a first embodiment of the present invention, wherein the frame rate deviates from a predetermined rate (step 31), and the pwm frequency is no longer an integer multiple of the frame rate.
In this embodiment, at step 32A, the synchronization of the backlight driver 16 and the timing controller 14 is maintained. According to one of the features of the present embodiment, in step 33, the duty cycle of the pwm control signal is set to 100% so that the backlight 15 always irradiates light. Therefore, the incomplete (partial) irradiation light (shown as a hatched area) as in fig. 2B does not occur. Next, in step 34, the dimming controller 17 detects whether the frame rate has been restored to the preset rate. If so, normal (zone) dimming operation is resumed and flow returns to step 31.
Fig. 5 illustrates a timing diagram of an abnormal state synchronization control signal Vsync and a pulse width modulation control signal (of a channel) according to a second embodiment of the present invention, wherein a frame rate deviates from a predetermined rate (step 31).
In this embodiment, in step 32B, the synchronization between the backlight driver 16 and the timing controller 14 is not maintained (i.e., the synchronization between the two is released). According to one of the features of the present embodiment, at step 35, the pwm frequency is maintained at an integer multiple of the predetermined rate. Since the pwm frequency is no longer an integer multiple of the predetermined rate, incomplete (partial) illumination and flicker as in fig. 2B does not occur. Next, in step 34, the dimming controller 17 detects whether the frame rate has been restored to the preset rate. If so, normal (zone) dimming operation is resumed and flow returns to step 31.
Fig. 6A illustrates a timing diagram of an abnormal state synchronization control signal Vsync and a (multi-channel) multi-pwm control signal according to a third embodiment of the present invention, wherein the frame rate deviates from and is greater than the predetermined rate (step 31), and the pwm frequency is no longer an integer multiple of the predetermined rate.
In this embodiment, the synchronization of the backlight driver 16 and the timing controller 14 is maintained at step 32A, and the duty cycle of the pwm control signal is maintained at step 36. In step 37, the dimming controller 17 determines whether the frame rate is greater than a preset rate. If so, at step 38A, one (e.g., the last) pulse width modulation period is reduced among the periods of the synchronization control signal. It is noted that the reduced illumination light of the last pwm period cannot be continuous with the next illumination light of the backlight 15. Next, in step 34, the dimming controller 17 detects whether the frame rate has been restored to the preset rate. If so, normal (zone) dimming operation is resumed and flow returns to step 31. It is noted that the duration of the reduced illumination of the last pwm period may be fixed, random or dynamically calculated (depending on the content of the image to be displayed). Since the long irradiation light and the short irradiation light of fig. 2B do not alternate, flickering is not perceived.
Fig. 6B illustrates a timing diagram of an abnormal state synchronization control signal Vsync and a (multi-channel) multi-pwm control signal according to a third embodiment of the present invention, wherein the frame rate deviates from and is smaller than the predetermined rate (step 31), and the pwm frequency is no longer an integer multiple of the predetermined rate.
In this embodiment, the synchronization of the backlight driver 16 and the timing controller 14 is maintained at step 32A, and the duty cycle of the pwm control signal is maintained at step 36. In step 37, the dimming controller 17 determines whether the frame rate is greater than a preset rate. If not, in step 38B, a pulse width modulation period is increased among the periods of the synchronization control signal. It is noted that the illumination light of the increased pulse width modulation period cannot be continuous with the next illumination light of the backlight 15. Next, in step 34, the dimming controller 17 detects whether the frame rate has been restored to the preset rate. If so, normal (zone) dimming operation is resumed and flow returns to step 31. It is noted that the period of the illumination light of the added pwm period may be fixed, random or dynamically calculated (depending on the content of the image to be displayed). Since the long irradiation light and the short irradiation light of fig. 2B do not alternate, flickering is not perceived.
Fig. 7 illustrates a timing diagram of an abnormal state synchronization control signal Vsync and a (multi-channel) multi-pwm control signal according to a fourth embodiment of the present invention, wherein the frame rate deviates from and is smaller than the predetermined rate (step 31), and the pwm frequency is no longer an integer multiple of the predetermined rate.
In this embodiment, the synchronization of the backlight driver 16 and the timing controller 14 is maintained at step 32A, and the duty cycle of the pwm control signal is maintained at step 36. According to one of the features of the present embodiment, at step 39, at least two different channels of the backlight 15 are synchronized at different times during the period of the synchronization control signal. As illustrated in fig. 7, the first channel is synchronized with time t1, the second channel is synchronized with time t2, and the third channel is synchronized with time t3. Next, in step 34, the dimming controller 17 detects whether the frame rate has been restored to the preset rate. If so, normal (zone) dimming operation is resumed and flow returns to step 31.
In one embodiment, the synchronization time difference for the respective channels may be fixed, random, or dynamically calculated (based on the content of the image to be displayed). Since the different channels are irregularly synchronized to different times, flicker is not perceived even if part of the channels alternate with long and short illumination.
Fig. 8 illustrates a timing diagram of an abnormal state synchronization control signal Vsync and a (multi-channel) multi-pwm control signal according to a fifth embodiment of the present invention, wherein the frame rate deviates from and is smaller than the predetermined rate (step 31), and the pwm frequency is no longer an integer multiple of the predetermined rate.
In this embodiment, the synchronization of the backlight driver 16 and the timing controller 14 is maintained at step 32A, and the duty cycle of the pwm control signal is maintained at step 36. According to one of the features of the present embodiment, at least two different channels of the backlight 15 are irradiated at different times during the period of the synchronization control signal in step 40. In one embodiment, as illustrated in fig. 8, the odd channels are illuminated at time t4 and the even channels are illuminated at time t5, with a delay period equal to the non-illuminated period of the pwm period. It is noted that the delay period may be fixed, random or dynamically calculated (based on the content of the image to be displayed). Next, in step 34, the dimming controller 17 detects whether the frame rate has been restored to the preset rate. If so, normal (zone) dimming operation is resumed and flow returns to step 31. Since the irradiation times of the pwm control signals of the different channel groups irregularly occur at different times, flickering is not perceived even if part of the channel long irradiation light and short irradiation light alternate.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention; all such equivalent changes and modifications as come within the spirit of the disclosure are desired to be embraced within the scope of the appended claims.
Claims (10)
1. A backlit display system, the backlit display system comprising:
a panel including a plurality of pixels;
a backlight driver for controlling an irradiation light of the backlight using a pulse width modulation control signal; a kind of electronic device with high-pressure air-conditioning system
A timing controller synchronizing with the backlight driver through a synchronization control signal;
when the frame rate deviates from the preset rate, maintaining the synchronization of the backlight driver and the time schedule controller in the period of the synchronization control signal, and setting the working period of the pulse width modulation control signal to be 100 percent so that the backlight always irradiates light; the frame rate represents the frequency at which images are displayed on the panel.
2. The backlit display system of claim 1, further comprising:
and the dimming controller detects whether the frame rate is equal to the preset rate and controls the backlight driver according to the frame rate.
3. The backlit display system of claim 2, further comprising:
the source electrode driver is controlled by the time schedule controller and used for generating image signals to the panel;
the light modulation controller is arranged on the source electrode driver.
4. The backlit display system of claim 1, wherein the backlight is divided into a plurality of channels controlled by the backlight driver to illuminate the panels respectively.
5. The backlit display system of claim 1, wherein the backlight comprises a plurality of light emitting diodes.
6. A backlit display system, the backlit display system comprising:
a panel including a plurality of pixels;
a backlight driver for controlling an irradiation light of the backlight using a pulse width modulation control signal; a kind of electronic device with high-pressure air-conditioning system
A timing controller synchronizing with the backlight driver through a synchronization control signal;
wherein when the frame rate deviates from a preset rate, the synchronization of the backlight driver and the time schedule controller is not maintained in the period of the synchronization control signal, and the pulse width modulation frequency is maintained to be an integral multiple of the preset rate so as to restore the frame rate to the preset rate; the frame rate represents the frequency at which images are displayed on the panel.
7. The backlit display system of claim 6, further comprising:
and the dimming controller detects whether the frame rate is equal to the preset rate and controls the backlight driver according to the frame rate.
8. The backlit display system of claim 7, further comprising:
the source electrode driver is controlled by the time schedule controller and used for generating image signals to the panel;
the light modulation controller is arranged on the source electrode driver.
9. The backlit display system of claim 6, wherein the backlight is divided into a plurality of channels controlled by the backlight driver to illuminate the panels respectively.
10. The backlit display system of claim 6, wherein the backlight comprises a plurality of light emitting diodes.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010484102.0A CN113763890B (en) | 2020-06-01 | 2020-06-01 | Display system with backlight |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010484102.0A CN113763890B (en) | 2020-06-01 | 2020-06-01 | Display system with backlight |
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| CN113763890A CN113763890A (en) | 2021-12-07 |
| CN113763890B true CN113763890B (en) | 2023-08-22 |
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| CN202010484102.0A Active CN113763890B (en) | 2020-06-01 | 2020-06-01 | Display system with backlight |
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| CN115512669B (en) * | 2022-09-16 | 2023-11-17 | 北京显芯科技有限公司 | Control circuit and display device |
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