CN113745213B - Chip and electronic equipment - Google Patents
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- CN113745213B CN113745213B CN202010478613.1A CN202010478613A CN113745213B CN 113745213 B CN113745213 B CN 113745213B CN 202010478613 A CN202010478613 A CN 202010478613A CN 113745213 B CN113745213 B CN 113745213B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
The invention provides a chip and electronic equipment. The chip comprises a chip body, wherein the chip body comprises at least one first input/output area and at least one first input/output power supply area, the first input/output area is a closed area which takes the central point of the chip body as the center and is formed by sequentially arranging a plurality of signal input/output units around the center, and the first input/output power supply area is a closed area which takes the central point as the center and is formed by sequentially arranging a plurality of power supply input/output units around the center. By arranging the power supply input output unit and the signal input output unit in different areas respectively, the selection of the power supply input output unit and the selection of the signal input output unit are not mutually influenced, the power supply input output unit and the signal input output unit with different size specifications can be selected respectively, and the power supply input output unit and the signal input output unit on the periphery of the chip can be flexibly arranged.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a chip and an electronic device.
Background
With the development of integrated circuits, the functions of the chip are more and more complex, resulting in an increasing number of signal input/output units in the chip. With the smaller and smaller area of the chip, the layout of the signal input/output units needs to be fully considered, so that the chip can accommodate more signal input/output units. In the layout of the signal input/output units, a certain number of power supply input/output units are required to be laid out besides a certain number of signal input/output units, so that enough power is provided for the signal input/output units, and the signal input/output units are prevented from generating larger voltage drop and noise in the action process, so that logic errors in the chip are caused. Meanwhile, the power supply rail of the power supply input output unit is connected with the power supply rail of the signal input output unit, and the ground rail of the power supply input output unit is connected with the ground rail of the signal input output unit, so that when electrostatic discharge occurs, a large instant current is generated, and a chip is burnt.
In the prior art, the signal input and output units and the power supply input and output units are alternately arranged in the same area, and the structure ensures that the heights of the signal input and output units and the power supply input and output units are the same, so that the power supply rail of the signal input and output unit and the power supply rail of the power supply input and output unit can be connected, and the ground rail of the signal input and output unit and the ground rail of the power supply input and output unit are connected together. The signal input/output unit and the power supply input/output unit cannot be flexibly selected and cannot be flexibly arranged because the heights of the power supply input/output unit and the signal input/output unit are required to be the same.
Disclosure of Invention
In view of the above problems, embodiments of the present invention provide a chip and an electronic device, so as to solve the problem that in a chip layout, a signal input output unit and a power supply input output unit affect each other, and the layout cannot be flexibly performed.
The embodiment of the invention discloses a chip, which comprises: the chip comprises a chip body, a first power supply and a second power supply, wherein the chip body comprises at least one first input and output area and at least one first input and output power supply area;
the first input/output power supply area is a closed area which takes the central point of the chip body as the center and is formed by sequentially arranging a plurality of signal input/output units around the center, and the first input/output power supply area is a closed area which takes the central point as the center and is formed by sequentially arranging a plurality of power supply input/output units around the center;
the first input/output area and the first input/output power supply area are arranged in a nested manner, and the power supply input/output unit is used for providing power for the signal input/output unit.
Optionally, the first input/output region is adjacent to at least one of the first input/output power regions.
Optionally, the number of the first input/output power supply areas is multiple, one side of at least one first input/output power supply area close to the central point is adjacent to one first input/output power supply area of the multiple first input/output power supply areas, and one side of at least one first input/output power supply area far away from the central point is adjacent to another first input/output power supply area of the multiple first input/output power supply areas.
Optionally, the chip body further includes at least one target area, where the target area is an area of the chip body except the first input/output power supply area and the first input/output area, and the target area is composed of at least one signal input/output unit and at least one power supply input/output unit.
Optionally, the target area includes at least one second input/output area and at least one second input/output power area, the second input/output area includes at least one signal input/output unit, and the second input/output power area includes at least one power supply input/output unit.
Optionally, the second input-output region is adjacent to at least one of the second input-output power supply regions.
Optionally, the number of the second input/output power supply areas is plural, a first side of at least one of the second input/output power supply areas is adjacent to one of the plurality of second input/output power supply areas, a second side of at least one of the second input/output power supply areas is adjacent to another one of the plurality of second input/output power supply areas, and the first side and the second side are opposite sides of the at least one of the second input/output power supply areas.
Optionally, the device further comprises a connection unit, wherein the connection unit is located in a first input/output power supply area or a first input/output area closest to the central point, and the target area is connected to the first input/output power supply area or the first input/output area closest to the central point through the connection unit.
Optionally, the second input/output power supply area and/or the second input/output area is connected to the first input/output power supply area through the connection unit; or,
the second input/output power supply area and/or the second input/output area is connected to the first input/output area through the connecting unit.
The invention also provides electronic equipment comprising the chip.
The embodiment of the invention has the following advantages:
the chip comprises a chip body, the chip body comprises at least one first input and output area and at least one first input and output power supply area, the first input and output area is a closed area which takes the central point of the chip body as the center and is formed by sequentially arranging a plurality of signal input and output units around the center, the first input and output power supply area is a closed area which takes the central point as the center and is formed by sequentially arranging a plurality of power supply input and output units around the center, the first input and output area and the first input and output power supply area are nested, and the power supply input and output units are used for providing power for the signal input and output units. In the embodiment of the invention, the power supply input output units and the signal input output units are respectively distributed by arranging different areas, the ground track and the power supply track corresponding to the first input output area formed by the signal input output units form a closed structure, the ground track and the power supply track corresponding to the first input output power supply area formed by the power supply input output units form a closed structure, the independent closed structures are kept to be consistent in height, and different heights can be correspondingly different between different closed structures; the power supply track of the signal input/output unit can be connected with the power supply track of the power supply input/output unit in the adjacent area, and the ground track of the signal input/output unit can be connected with the ground track of the power supply input/output unit in the adjacent area, so that the signal input/output unit and the power supply input/output unit can respectively select different size specifications, and further the power supply input/output unit and the signal input/output unit at the periphery of the chip can be flexibly distributed.
Drawings
FIG. 1 shows a schematic diagram of the structure of a chip of the present invention;
FIG. 2 shows a schematic diagram of the circuit connection at position A in FIG. 1;
FIG. 3 shows a schematic diagram of another chip of the present invention;
FIG. 4 shows a schematic diagram of the structure of a further chip of the invention;
FIG. 5 shows a schematic diagram of the circuit connections in position B of FIG. 4;
fig. 6 shows a schematic diagram of the circuit connection at position C in fig. 4.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, a schematic diagram of the structure of a chip of the present invention is shown. As shown in fig. 1, the chip includes a chip body, and the chip body includes at least one first input/output area 201 and at least one first input/output power area 202, where the first input/output area 201 is a rectangular area formed by a plurality of small squares, and the first input/output power area 202 is a rectangular area covered by oblique lines as shown in fig. 1.
The first input/output region 201 is a closed region centered on the center point of the chip body 203 and formed by sequentially arranging a plurality of Signal input/output units 2011 (Signal IO) around the center. The first i/o power Supply region 202 is a closed region centered on the center point of the chip body 203 and composed of a plurality of power Supply i/o units 2021 (Supply IO) sequentially arranged around the center. The first input/output power supply area 202 and the first input/output area 201 are nested, and the power supply input/output unit 2021 is used to provide power for the signal input/output unit 2011. Here, one cross-hatched small square area represents one power supply input output unit 2021, and one white small square area represents one signal input output unit 2011.
Alternatively, the center point of the chip body 203 may be a standard center point, a specified center point, or an estimated center point. When the chip body 203 is in a regular shape, if the chip body 203 is a square, the center point of the chip body 203 is a standard center point, that is, the intersection point of two diagonal lines of the square, that is, the standard center point generally refers to the geometric center point of the chip body 203; when the chip body 203 is irregularly shaped, the center point of the chip body 203 may be an estimated approximate center point; further, whether or not the chip body 203 is of a regular shape, a center point may be manually set, and the set center point may be any specified position on the chip body 203, that is, the set center point is a specified center point.
In this embodiment, the chip body 203 may be, for example, a final execution unit such as a processor (CPU, central Processing Unit) for processing instructions, executing operations, controlling time, and processing data. The areas of the chip body 203 except the first input/output area 201 and the first input/output power area 202 are used for layout logic components, and the internal structure of the chip body 203 can refer to the prior art, which is not described in detail in this embodiment. The signal input/output unit 2011 is arranged around the chip body and is used for connecting the chip body with other devices outside the chip body so as to realize information interaction between the chip body and the external environment. The power supply input/output unit 2021 is connected to the signal input/output unit 2011, and is used for providing power to the signal input/output unit 2011, and the specific structure and function of the signal input/output unit 2011 and the power supply input/output unit 2021 may refer to the prior art, which will not be described in detail in this embodiment.
In the present embodiment, the first input/output power region 202 is used for laying out a plurality of power supply input/output units 2021, and the first input/output region 201 is used for laying out a plurality of signal input/output units 2011. The first input/output region 201 and the first input/output power region 202 are annular enclosed regions formed around the chip body 203 with the center point of the chip body 203 as the center.
As illustrated in fig. 1, the chip body 203 includes a first input-output region 201 and a first input-output power region 202. The chip body 203 is rectangular, and in the first input/output power supply area 202, a plurality of power supply input/output units 2021 are sequentially arranged around the chip body 203 to form a closed rectangular power supply input/output ring. The number of the power input/output units 2021 in the first input/output power region 202 may be set according to the size specification of the power input/output units 2021 and the size specification of the first input/output power region 202, which is not limited in this embodiment. The first input/output area 201 is nested at a side of the first input/output power area 202 far away from the chip body 203, and in the first input/output area 201, a plurality of signal input/output units 2011 are sequentially arranged around the first input/output power area 202 to form a closed rectangular input/output ring. The number of the signal input/output units 2011 in each of the first input/output regions 201 may be set according to the size specification of the signal input/output units 2011 and the size specification of the first input/output region 201, which is not limited in this embodiment.
It should be noted that the shape of the chip body may be set according to the requirement, for example, the chip body may be circular or elliptical, or polygonal such as triangle and pentagon. Correspondingly, the shapes of the first input/output power supply area and the first input/output area formed around the chip body are determined according to the shape of the chip body by taking the center point of the chip body as the center, for example, if the chip body is pentagonal, the first input/output power supply area and the first input/output area are formed as pentagonal annular closed areas.
In practical applications, the number of the first i/o regions 201 and the first i/o power supply regions 202 may be set according to requirements, for example, may include 2 first i/o regions 201 and one first i/o power supply region 202, or 2 first i/o regions 201 and 3 first i/o power supply regions 202, and the number of the first i/o regions 201 and the first i/o power supply regions 202 is not limited in this embodiment. Meanwhile, in fig. 1, the first i/o power region 201 is nested outside the first i/o power region 202 (on the side far from the center point of the chip body), the first i/o power region 202 is nested inside the first i/o power region 201 (on the side near the center point of the chip body), and in practical application, the positions of the first i/o region 201 and the first i/o power region 202 may be interchanged, for example, the first i/o power region 202 may be located outside the first i/o power region 201, and the relative positional relationship between the first i/o power region 201 and the first i/o power region 202 is not limited in this embodiment.
In the present embodiment, the power supply input output unit 2021 is used to supply power to the signal input output unit 2011. As shown in fig. 2, a schematic circuit connection diagram of the a position in fig. 1 is shown, and the power supply input output unit 2021 is adjacent to the adjacent signal input output unit 2011, for supplying power to the adjacent signal input output unit 2011. That is, the front driving ground rail (VSS) in the power supply input output unit 2021 is shorted with the front driving ground rail (VSS) in the adjacent signal input output unit 2011, the front driving power rail (VDD) in the power supply input output unit 2021 is shorted with the front driving power rail (VDD) in the adjacent signal input output unit 2011, the rear driving ground rail (VSSPST) in the power supply input output unit 2021 is shorted with the rear driving ground rail (VSSPST) in the adjacent signal input output unit 2011, and the rear driving power rail (VDDPST) in the power supply input output unit 2021 is shorted with the rear driving power rail (VDDPST) in the adjacent signal input output unit 2011, so as to realize power supply to the signal input output unit. In addition, in order to ensure the electrostatic discharge (ESD) protection characteristic of the chip body, as shown in fig. 2, in each of the first input/output power supply areas 202, adjacent power supply input/output units 2021 are adjacent to each other, that is, the front driving power supply rail (VDD) of the adjacent power supply input/output unit 2021 is shorted, the front driving ground rail (VSS) is shorted, the rear driving ground rail (VSSPST) is shorted, and the rear driving power supply rail (VDDPST) is shorted, so that a plurality of power supply input/output units 2011 in each of the first input/output power supply areas 202 form a complete power supply input/output ring, thereby improving the ESD protection characteristic of the chip. Meanwhile, in each of the first input-output regions 201, adjacent signal input-output units 2011 may be abutted, that is, a front driving power supply rail (VDD) of the adjacent signal input-output unit 2011 is shorted, a front driving ground rail (VSS) is shorted, a rear driving ground rail (VSSPST) is shorted, and a rear driving power supply rail (VDDPST) is shorted.
In actual use, since adjacent power supply input/output units are adjacent to each other, adjacent power supply input/output units 2021 may be adjacent to each other only in each first input/output power supply region 202, or adjacent signal input/output units may be adjacent to each other in each first input/output region 201. The adjacent manner between the power supply input output unit and the signal input output unit, the adjacent manner between the signal input output unit, and the adjacent manner between the power supply input output unit can refer to the prior art, and the present embodiment is not limited thereto.
In this embodiment, since the first input/output area includes only the signal input/output units, the heights of the signal input/output units in the first input/output area need only be guaranteed to be the same. In the same way, the first input/output power supply area only comprises a power supply input/output unit, the heights of the power supply input/output unit and the signal input/output unit in the first input/output power supply area are only required to be the same, and the heights of the signal input/output unit and the power supply input/output unit can be the same or different. In the chip layout process, since the power supply input output unit and the signal input output unit are respectively located in different areas, the size specifications of the power supply input output unit and the signal input output unit can be different, the size specification of the power supply input output unit is not limited by the size specification of the signal input output unit, and the size specification of the power supply input output unit can be flexibly selected so as to flexibly adjust the number of the power supply input output units in the first input output power supply area. Similarly, the size specification of the signal input/output unit is not limited by the size specification of the power supply input/output unit, and the size specification of the first signal input/output unit can be flexibly selected so as to flexibly adjust the number of the signal input/output units in the first input/output area.
In summary, the chip includes a chip body, where the chip body includes at least one first input/output area and at least one first input/output power area, the first input/output area is a closed area with a central point of the chip body as a center and formed by sequentially arranging a plurality of signal input/output units around the center, the first input/output power area is a closed area with a central point of the chip body as a center and formed by sequentially arranging a plurality of power supply input/output units around the center, and the first input/output area and the first input/output power area are nested and arranged, and the power supply input/output unit is used for providing power for the signal input/output unit. By arranging the power supply input output units and the signal input output units in different areas, the power supply rail of the signal input output units can be connected with the power supply rail of the power supply input output units in the adjacent areas, and the ground rail of the signal input output units can be connected with the ground rail of the power supply input output units in the adjacent areas, so that the signal input output units and the power supply input output units can be respectively selected in different sizes, and the power supply input output units and the signal input output units at the periphery of the chip can be flexibly arranged.
Referring to fig. 3, there is shown a schematic structural diagram of another chip of the present invention, and as shown in fig. 3, the chip includes a chip body including at least one first input output region 201 and at least one first input output power region 202.
As illustrated in fig. 3, the chip body may include two first input-output power supply regions 202 and two first input-output regions 201.
Optionally, the first input output region 201 is adjacent to at least one first input output power region 202.
In this embodiment, each of the first input/output regions 201 may be adjacent to at least one of the first input/output power regions 202, i.e., at least one of the first input/output power regions 202 adjacent to the first input/output region 201 is disposed inside or outside the first input/output region 201. As shown in fig. 3, the first input-output regions 201 and the first input-output power supply regions 202 may be alternately arranged such that each of the first input-output regions 201 is adjacent to at least one of the first input-output power supply regions 202. In actual use, the layout modes of the first input/output regions and the first input/output power supply regions can be adjusted according to the requirements, so that each first input/output region is adjacent to at least one input/output power supply region.
In practical applications, the power supply input/output unit 2021 in the first input/output power supply area 202 is configured to supply power to the signal input/output unit 2011 in the first input/output area 201, and when the distance between the power supply input/output unit 2021 and the signal input/output unit 2011 is far, the voltage drop between the power supply input/output unit 2021 and the signal input/output unit 2011 will increase, resulting in insufficient power supply of the signal input/output unit 2011 and affecting the performance of the signal input/output unit 2011. Therefore, each of the first input-output regions 201 is disposed adjacent to at least one of the first input-output power regions 202, and a problem of insufficient power supply of the signal input-output unit 2011 due to distance can be avoided.
Optionally, the number of the first input/output power supply areas is multiple, one side of at least one first input/output area close to the center point of the chip body is adjacent to one first input/output power supply area of the multiple first input/output power supply areas, and one side of the at least one first input/output area far from the center point of the chip body is adjacent to another first input/output power supply area of the multiple first input/output power supply areas.
By way of example, referring to fig. 4, a schematic diagram of a further chip of the present invention is shown, in which a chip body may include one first input output region 201 and two first input output power regions 202. The first input/output area 201 is located between two first input/output power areas 202, i.e., one side (inner side) of the first input/output area 201, which is close to the chip body, is provided with an adjacent first input/output power area 202, and one side (outer side) of the first input/output area 201, which is far from the chip body, is also provided with an adjacent other first input/output power area 202. In actual use, the layout modes of the first input/output area and the first input/output power supply area can be adjusted according to the requirements, so that the inner side and the outer side of the first input/output area are respectively provided with one adjacent first input/output power supply area.
In this embodiment, when the first input/output power supply areas are arranged on the inner side and the outer side of the first input/output area, the power supply input/output units in the first input/output power supply areas on the inner side and the outer side can supply power to the signal input/output units in the first input/output area at the same time. As shown in fig. 5, a schematic circuit connection diagram of the B position in fig. 4 is shown, where the signal input/output units in the first input/output area can simultaneously provide power through the power supply input/output units on both sides, so as to ensure that the signal input/output units in the first input/output area can obtain sufficient power, and improve the performance of the signal input/output units.
It should be noted that, in practical application, when the number of the first input/output areas is smaller, an adjacent first input/output power area may be disposed on at least one side of each first input/output area, so as to ensure the power requirement of each signal input/output unit. When the number of the first input/output power supply areas is larger, two adjacent first input/output power supply areas can be respectively arranged on two sides of part or all of the first input/output areas so as to provide sufficient power for each signal input/output unit and improve the performance of the signal input/output unit.
Optionally, the chip body may further include at least one target area, where the target area is an area of the chip body except the first input/output power supply area and the first input/output area, and the target area is composed of at least one signal input/output unit and at least one power supply input/output unit.
As an example, as shown in fig. 1, a target area 204 may be disposed in the chip body 203, where the target area 204 is configured to layout at least one signal input output unit 2011, and at least one power supply input output unit 2021 that provides power to the signal input output unit 2011 in the target area 204.
In practical applications, the number of the target areas 204 may be one or more, and the target areas 204 may be disposed at any position in the chip body except the first input/output area 201 and the first input/output power area 202, such as an intermediate position shown in fig. 1. The number of signal input/output units and power supply input/output units in the target area 204, and the specific position of the target area in the chip body may be set according to requirements, which is not limited in this embodiment.
In this embodiment, as shown in fig. 1, when the number of the signal input output units 2011 and the power supply input output units 2021 in the target area 204 is plural, the target area 204 may be composed of the signal input output units 2011 and the power supply input output units 2021 alternately arranged. When the target area 204 is formed by alternately arranging the signal input/output unit 2011 and the power supply input/output unit 2021, the connection method between the power supply input/output unit and the signal input/output unit can refer to the prior art, and this embodiment will not be described in detail.
When a blank area (an area where other components are not arranged) exists in the chip body 203, the target area 204 can be set in the blank area, and a certain number of signal input/output units and power supply input/output units are arranged in the target area 204, so that a certain number of signal input/output units can be added without increasing the chip area, and a richer chip interface is provided for the chip.
Alternatively, the target area may include at least one second input-output area including at least one signal input-output unit and at least one second input-output power area including at least one power supply input-output unit.
As an example, as shown in fig. 3, in the target area 204, one second input-output area 2041 and one second input-output power supply area 2042 may be provided, and the second input-output area 2041 and the second input-output power supply area 2042 are disposed side by side. The second input/output region 2041 may be formed by sequentially arranging a plurality of signal input/output units 2011, and the second input/output power region 2042 may be formed by sequentially arranging a plurality of power supply input/output units 2021. The connection manner between the power input/output unit in the second input/output power supply area and the signal input/output unit in the second input/output area can refer to fig. 2, and this embodiment will not be described in detail.
In this embodiment, when the target area 204 is composed of at least one second input/output area 2041 and at least one second input/output power area 2042, in the layout process of the target area 204, signal input/output units and power supply input/output units with different sizes can be selected respectively, so as to realize flexible layout of the target area.
Optionally, the second input output region is adjacent to at least one second input output power region.
In the present embodiment, in the layout of the target area 204, each of the second input-output areas 2041 may be disposed adjacent to at least one of the second power input-output areas 2042. As shown in fig. 3 and 4, adjacent second input-output regions 2042 may be laid out on one side and/or both sides of the second input-output region 2041 to provide sufficient power for the signal input-output cells in the second input-output region 2041. The principle and method of laying out the second input/output power supply areas adjacent to the second input/output areas can be referred to as the first input/output power supply areas adjacent to the first input/output areas, and this embodiment will not be described in detail.
Optionally, the number of the second input/output power supply areas is plural, a first side of at least one second input/output power supply area is adjacent to one of the plurality of second input/output power supply areas, and a second side of at least one second input/output power supply area is adjacent to another of the plurality of second input/output power supply areas.
For example, as shown in fig. 4, in the layout of the target area 204, when the number of the second input/output power supply areas 2042 is large, adjacent second input/output power supply areas 2042 may be respectively laid out on both sides of each second input/output area 2041 to provide sufficient power for the signal input/output units in the second input/output areas 2041. The principle and method of respectively arranging adjacent second input/output power supply areas on two sides of each second input/output area can be referred to as respectively arranging adjacent first input/output power supply areas on two sides of each first input/output area, which will not be described in detail in this embodiment.
Optionally, the chip further comprises a connection unit, wherein the connection unit is located in the first input/output power supply area or the first input/output area close to the center point of the chip body, and the target area is connected to the first input/output power supply area or the first input/output area close to the center point of the chip body through the connection unit.
Optionally, when the first input/output area (input/output area a) is the area closest to the center point of the chip body, the connection unit is located in the input/output area a, that is, the target area is connected to the input/output area a through the connection unit; similarly, when the first input/output power supply area (input/output power supply area a) is the area closest to the center point of the chip body, the connection unit is located in the input/output power supply area a, that is, the target area is connected to the input/output power supply area a through the connection unit. In addition, when the first input output region (input output region a) is the region closest to the center point of the chip body, the connection unit may also be located in the adjacent first input output power supply region closest to the input output region a; similarly, when the first input/output power supply area (input/output power supply area a) is the area closest to the center point of the chip body, the connection unit may also be located in the adjacent first input/output area closest to the input/output power supply area a, which is not described herein again.
In this embodiment, when the target area includes the second input/output area and the second input/output power area, the second input/output power area and/or the second input/output area is connected to the first input/output power area through the connection unit; or the second input/output power supply area and/or the second input/output area is connected to the first input/output area through the connecting unit.
As an example, as shown in fig. 4, the connection unit 205 may be a three-way input output unit (Triple IO) that may be disposed in the first input output power supply region 202. Referring to fig. 6, a schematic diagram of the circuit connection at the C position in fig. 4 is shown, and referring to fig. 4 and 5, the three-way input/output unit may select the same size specification as the power input/output unit 2021 in the first input/output power source region 202, so as to layout the three-way input/output unit in the first input/output power source region 202, where two connection ends of the three-way input/output unit are located in the first input/output power source region 202, and the other connection end is connected to the power input/output unit in the target region 204. Two connection ends of the three-way input-output unit located in the first input-output power supply area 202 are respectively adjacent to the adjacent power supply input-output units in the first input-output power supply area 202. Meanwhile, the other end of the three-way input-output unit is adjacent to the power supply input-output unit at one end of the second input-output power supply region 2042. The power supply input output unit in the second input output power supply area can be simply and conveniently connected to the first input output power supply area through the tee input output unit. Similarly, the signal input/output unit in the second input/output area may be connected to the first input/output power supply area.
In practical applications, when the target area is formed by alternately arranging a plurality of signal input/output units and a plurality of power supply input/output units, the method for connecting the target area to the first input/output area or the first input/output power area is the same as the method for connecting the second input/output power area to the first input/output power area, which is not described in detail in this embodiment.
The positions of the first input/output area and the first input/output power area can be interchanged, and the second input/output power area and/or the second input/output area can be connected to the first input/output area. The principle of accessing the second input/output power supply area and the second input/output area to the first input/output area is the same as that of accessing the second input/output power supply area, and this embodiment will not be described in detail.
In this embodiment, the second input/output power supply area and/or the second input/output area is connected to the first input/output area or the first input/output power supply area, so that more signal input/output units and power supply input/output units can be connected to the power supply network, and the ESD protection characteristic of the chip can be further improved. Meanwhile, the power supply input/output unit in the first input/output power supply area can be used for supplying power to the signal input/output unit in the target area, or the power supply input/output unit in the first input/output area can be used for supplying power to the signal input/output unit in the target area, so that the power supply performance of the chip is improved.
Alternatively, when the target area 204 is parallel to one side of the chip body 203, two ends of the second input/output power area 2042 and/or the second input/output area 2041 in the target area 204 may be connected to the first input/output power area (as shown in fig. 4), or connected to the first input/output area, respectively. The second input/output power supply area and/or two ends of the second input/output area are respectively connected to the first input/output power supply area or the first input/output area, so that the ESD protection characteristic of the chip can be further improved.
Optionally, an ESD protection circuit may be provided in the connection unit. The ESD protection circuit is arranged in the connection unit, so that the ESD protection characteristic of the chip can be further improved. The specific structure of the ESD protection circuit can refer to the prior art, and this embodiment is not limited thereto.
In summary, the chip includes a chip body, where the chip body includes at least one first input/output area and at least one first input/output power area, the first input/output area is a closed area with a central point of the chip body as a center and formed by sequentially arranging a plurality of signal input/output units around the center, the first input/output power area is a closed area with a central point of the chip body as a center and formed by sequentially arranging a plurality of power supply input/output units around the center, and the first input/output power area and the first input/output area are nested and arranged, and the power supply input/output unit is used for providing power for the signal input/output unit. The power supply input output unit and the signal input output unit are respectively distributed in different areas, the ground track and the power supply track corresponding to the first input output area formed by the signal input output unit form a closed structure, the ground track and the power supply track corresponding to the first input output power supply area formed by the power supply input output unit form a closed structure, the independent closed structures are kept consistent in height, and different heights can be corresponding to different closed structures; the power supply track of the signal input/output unit can be connected with the power supply track of the power supply input/output unit in the adjacent area, and the ground track of the signal input/output unit can be connected with the ground track of the power supply input/output unit in the adjacent area, so that the signal input/output unit and the power supply input/output unit can respectively select different size specifications, and further the power supply input/output unit and the signal input/output unit at the periphery of the chip can be flexibly distributed.
In this embodiment, an electronic device is further provided, including a chip as in any one of the foregoing embodiments.
The above describes a chip and an electronic device provided by the present invention in detail, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (9)
1. A chip, comprising: the chip comprises a chip body, a first power supply and a second power supply, wherein the chip body comprises at least one first input and output area and at least one first input and output power supply area;
the first input/output power supply area is a closed area which takes the central point of the chip body as the center and is formed by sequentially arranging a plurality of signal input/output units around the center, and the first input/output power supply area is a closed area which takes the central point as the center and is formed by sequentially arranging a plurality of power supply input/output units around the center;
the first input/output area and the first input/output power supply area are arranged in a nested manner, and the power supply input/output unit is used for providing power for the signal input/output unit;
the number of the first input/output power supply areas is multiple, one side of at least one first input/output power supply area close to the central point is adjacent to one first input/output power supply area in the plurality of first input/output power supply areas, and one side of at least one first input/output power supply area far away from the central point is adjacent to the other first input/output power supply area in the plurality of first input/output power supply areas.
2. The chip of claim 1, wherein the first input-output region is adjacent to at least one of the first input-output power regions.
3. The chip according to any one of claims 1-2, wherein the chip body further comprises at least one target area, the target area being an area of the chip body other than the first input-output power supply area and the first input-output area, the target area being composed of at least one of the signal input-output units and at least one of the power supply input-output units.
4. The chip of claim 3, wherein the target area comprises at least one second input-output area and at least one second input-output power area, the second input-output area comprising at least one of the signal input-output units, the second input-output power area comprising at least one of the power supply input-output units.
5. The chip of claim 4, wherein the second input-output region is adjacent to at least one of the second input-output power regions.
6. The chip of claim 4, wherein the number of the second input/output power supply areas is plural, a first side of at least one of the second input/output power supply areas is adjacent to one of the plurality of second input/output power supply areas, and a second side of at least one of the second input/output power supply areas is adjacent to another of the plurality of second input/output power supply areas, the first side and the second side being opposite sides of the at least one second input/output power supply area.
7. The chip of claim 4, further comprising a connection unit located within the first input output power region or the first input output region closest to the center point, the target region accessing the first input output power region or the first input output region closest to the center point through the connection unit.
8. The chip according to claim 7, wherein the second input-output power supply area and/or the second input-output area is connected to the first input-output power supply area through the connection unit; or,
the second input/output power supply area and/or the second input/output area is connected to the first input/output area through the connecting unit.
9. An electronic device comprising a chip as claimed in any one of claims 1-8.
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| US5422441A (en) * | 1992-04-01 | 1995-06-06 | Nec Corporation | Master slice integrated circuit having a reduced chip size and a reduced power supply noise |
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| JP2009026868A (en) * | 2007-07-18 | 2009-02-05 | Panasonic Corp | Semiconductor integrated circuit and its design method |
| WO2010125043A1 (en) * | 2009-04-27 | 2010-11-04 | St-Ericsson Sa (St-Ericsson Ltd) | Supply cell and integrated circuit comprising such supply cells |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2011065022A1 (en) * | 2009-11-30 | 2011-06-03 | パナソニック株式会社 | Semiconductor integrated circuit |
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|---|---|---|---|---|
| US5422441A (en) * | 1992-04-01 | 1995-06-06 | Nec Corporation | Master slice integrated circuit having a reduced chip size and a reduced power supply noise |
| US6222213B1 (en) * | 1998-06-29 | 2001-04-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device |
| JP2009026868A (en) * | 2007-07-18 | 2009-02-05 | Panasonic Corp | Semiconductor integrated circuit and its design method |
| WO2010125043A1 (en) * | 2009-04-27 | 2010-11-04 | St-Ericsson Sa (St-Ericsson Ltd) | Supply cell and integrated circuit comprising such supply cells |
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