CN113745125B - Measuring structure and forming method thereof - Google Patents
Measuring structure and forming method thereof Download PDFInfo
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- CN113745125B CN113745125B CN202010473416.0A CN202010473416A CN113745125B CN 113745125 B CN113745125 B CN 113745125B CN 202010473416 A CN202010473416 A CN 202010473416A CN 113745125 B CN113745125 B CN 113745125B
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000012360 testing method Methods 0.000 claims abstract description 229
- 238000005259 measurement Methods 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
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- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 47
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- 239000004065 semiconductor Substances 0.000 abstract description 20
- 238000012544 monitoring process Methods 0.000 abstract description 14
- 238000001514 detection method Methods 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 239000011295 pitch Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A measurement structure and method of forming the same, the measurement structure comprising: a substrate; a first dielectric layer on the substrate; a second dielectric layer on the first dielectric layer; a third dielectric layer on the second dielectric layer; a test plug in the third dielectric layer; and a metal gate structure is not formed in the second dielectric layer below the test plug. According to the scheme, the accuracy of optical measurement signal monitoring of the test plug can be improved, so that the accurate detection of the contact hole forming process can be realized, and the performance of the formed semiconductor structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor integrated circuits, and more particularly, to a measurement structure and a method for forming the same.
Background
At present, the conduction between different metal layers of a semiconductor device is achieved by forming a groove in a dielectric layer between two metal layers and filling a conductive material (such as copper) into the groove, so as to form a Contact Hole (CT) structure for conducting the two metal layers. And the contact hole technology leads out each electrode of various devices on the substrate to the dielectric layer, and leads out the electrode of the integrated circuit by utilizing multilayer metal interconnection so as to facilitate the subsequent encapsulation.
To ensure consistent device performance, the depth and width of the contact openings must be carefully controlled. Variations in contact opening size can lead to variations in contact resistance. If such contact resistance variation is too large, device performance may be affected, resulting in a reduction in product yield. Therefore, it is necessary to monitor the formation process of the contact hole.
In semiconductor manufacturing processes, optical Critical Dimension (OCD) measurement devices are typically used to optically measure test cells, so that the etch depth of a dielectric layer during formation of a via can be monitored in real-time on-line.
However, the existing measurement structure cannot accurately monitor the formation process of the semiconductor structure, and reduces the performance of the formed semiconductor structure.
Disclosure of Invention
The invention solves the problem of providing a measuring structure to realize accurate monitoring of a contact hole forming process and improve the performance of a formed semiconductor structure.
In order to solve the above problems, the present invention provides a measurement structure including:
a substrate;
a first dielectric layer on the substrate;
a second dielectric layer on the first dielectric layer;
a third dielectric layer on the second dielectric layer;
a test plug in the third dielectric layer; and a metal gate structure is not formed in the second dielectric layer below the test plug.
Optionally, the substrate includes a logic test region;
the test plug includes a first test plug; the first test plug is located in a third dielectric layer over the logic test region.
Optionally, the cross-section of the first test plug is square in shape.
Optionally, the first test plug is a plurality of; the first spacing of adjacent first test plugs in the first direction is the same, and the second spacing of adjacent first test plugs in the second direction is the same; the first direction is perpendicular to the second direction.
Optionally, the first direction is a width direction of the first test plug; the first spacing between adjacent first test plugs in the first direction is two to three times the width of the first test plugs.
Optionally, the cross-section of the first test plug has a dimension in the first direction of 20nm to 25nm; the first spacing between adjacent first test plugs in the first direction is 40 nm-75 nm.
Optionally, the substrate further includes SRAM test regions located on both sides of the logic test region along a first direction;
the test plug further comprises a second test plug; the second test plug is located over the SRAM test region.
Optionally, the number ratio of the second test plug on each SRAM test zone to the first test plug on the logic test zone is 1: 2-1: 1.
optionally, the cross-section of the second test plug is rectangular in shape.
Optionally, the second test plug has a dimension in the first direction that is greater than a dimension of the second test plug in the first direction.
Optionally, the cross-section of the second test plug has a dimension in the first direction of 20nm to 25nm, and the cross-section of the second test plug has a dimension in the second direction of 35nm to 40nm.
Optionally, the test plug penetrates the third dielectric layer.
Optionally, the bottom of the test plug is located in the third dielectric layer.
Optionally, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are the same or different.
Optionally, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are all low dielectric constant materials.
Optionally, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are all SiO2.
The embodiment of the invention also provides a method for forming the measuring structure, which comprises the following steps:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a second dielectric layer on the first dielectric layer;
forming a third dielectric layer on the second dielectric layer;
forming a test plug in the third dielectric layer; and a metal gate structure is not formed in the second dielectric layer below the test plug.
Optionally, the substrate includes a logic test region; forming a test plug in the third dielectric layer, including:
and forming a first test plug in the third dielectric layer above the logic test region.
Optionally, the substrate further comprises SRAM test areas positioned at two sides of the logic test area; forming a test plug in the third dielectric layer, further comprising:
and forming a second test plug in the third dielectric layer above the logic test region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the scheme, the metal gate structure is not formed in the second dielectric layer below the test plug, and the interference of the optical measurement signal of the metal gate structure on the optical measurement signal of the test plug can be eliminated due to the fact that the metal gate structure below the test plug is removed, so that the accuracy of monitoring the optical measurement signal of the test plug can be improved, accurate detection of a contact hole forming process can be achieved, and the performance of the formed semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of a measurement structure;
FIG. 2 is a top view of the measurement structure shown in FIG. 1;
FIG. 3 is a schematic diagram of a metal gate structure signal and a contact hole signal resolved from the spectrum signal of the measurement structure shown in FIG. 1;
FIG. 4 is a schematic diagram of a measurement structure in an embodiment of the invention;
FIG. 5 is a schematic diagram of a measurement structure in an embodiment of the invention;
fig. 6 to 9 are schematic views of intermediate structures corresponding to steps of a method for forming a measurement structure according to an embodiment.
Detailed Description
As described in the background art, the existing measurement structure has the problem of low test accuracy, and reduces the performance of the semiconductor structure.
Referring to fig. 1 and 2, a measurement structure includes: a substrate 100; a first dielectric layer 110 over the substrate; a second dielectric layer 120 over the first dielectric layer 110; the second dielectric layer 120 has a plurality of metal gate structures 125 formed therein and extending along the first direction; a third dielectric layer 130 over the second dielectric layer 110 and the metal gate structure 115, and a test plug 135 in the third dielectric layer 130.
In the above measurement structure, the metal gate structure 125 and the test plug 135 are made of metal materials. The optical measurement signal of the metal gate structure may interfere with the optical measurement signal of the test plug, which results in failure to accurately detect the formation process of the test plug.
Fig. 3 shows a schematic diagram of optical measurement signals of a metal gate structure and a test plug. Referring to fig. 3, the optical measurement signal S1 of the metal gate structure and the optical measurement signal S2 of the test plug are changed drastically at the same time in the same band interval. In addition, the inventor of the present application found through experiments that the correlation coefficient between the metal gate structure and the test plug is 0.7, which means that when the metal gate structure is changed, the 70% probability will affect the change of the test plug.
Therefore, the existing measuring structure cannot accurately monitor the forming process of the contact hole due to the interference of the optical measuring signal of the metal gate structure, and the performance of the formed semiconductor structure is reduced.
In order to solve the above problems, a measurement structure in an embodiment of the present invention includes: a substrate; a first dielectric layer on the substrate; a second dielectric layer over the first dielectric layer; a third dielectric layer over the second dielectric layer; and a test plug in the third dielectric layer.
In the measuring structure provided by the embodiment of the invention, the metal grid structure below the test plug is removed, so that the interference of the optical measuring signal of the metal grid structure on the optical measuring signal of the test plug can be eliminated, the accuracy of the optical measuring signal detection of the test plug is improved, the accurate detection of the contact hole forming process can be realized, and the performance of the formed semiconductor structure is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 shows a schematic diagram of a measurement structure in an embodiment of the invention. Referring to fig. 4, a measurement structure in an embodiment of the present invention may include: a substrate 400; a first dielectric layer 410 on the substrate 400; a second dielectric layer 420 on the first dielectric layer 410; a third dielectric layer 430 located over the second dielectric layer 420 and a test plug 440 located in the third dielectric layer 430; a metal gate structure is not formed in the second dielectric layer 420 under the test plug 440.
In an embodiment of the present invention, the substrate includes a main pattern area and a test pattern area located at a periphery of the main pattern area. The main pattern area is used for forming a semiconductor chip pattern; the test pattern area is used for forming a test pattern for monitoring the forming process of the semiconductor chip pattern on the main pattern area. Monitoring through a forming process of a test pattern arranged on the test area so as to enable the appearance of the semiconductor chip pattern formed on the main pattern area to be consistent with the appearance of a corresponding semiconductor chip design pattern.
The measuring structure in the embodiment of the invention is formed in the test area. In this embodiment, the measurement structure is a measurement unit for monitoring a process of forming a contact hole in the SRAM device. The transistor in the SRAM device is a fin field effect transistor, so that the control capability of the gate electrode to the channel is enhanced, and the short channel effect is well restrained.
In this embodiment, the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430 are in one-to-one correspondence with the three dielectric layers of the fin field effect transistor formed on the substrate, and are formed in the same process steps, respectively.
Fig. 5 shows a schematic top view of a measurement structure in an embodiment of the invention.
Referring to fig. 5, in this embodiment, the substrate includes a logic test region I. The logic test area I is located in a test area of the substrate. The logic test area I is arranged corresponding to a logic area in the SRAM main graph area of the substrate. Accordingly, the test plug includes a first test plug 441 located in the third dielectric layer 430 on the logic test region I. The first test plug 441 is used to monitor the formation process of the logic region contact hole of the SRAM device.
In the measurement structure provided in the embodiment of the present invention, the second dielectric layer 420 is not formed with a metal gate structure, i.e., the second dielectric layer 420 under the first test plug 441 is not formed with a metal gate structure. Because the metal gate structure below the first test plug 441 is removed, interference of the optical measurement signal of the metal gate structure on the optical measurement signal of the first test plug can be eliminated, and accuracy of optical measurement signal detection of the first test plug is improved, so that accurate detection of the first test plug forming process can be realized, and performance of the formed semiconductor structure is improved.
In this embodiment, the bottom of the first test plug 441 may be in contact with the second dielectric layer 420, i.e., the first test plug 441 penetrates the third dielectric layer 430. In other embodiments, the bottom of the first test plug 441 can also be free of contact with the second dielectric layer 420, i.e., the bottom of the first test plug 441 exposes the material of the third dielectric layer 430.
The shape of the cross section of the first test plug 441 in the logic test region I may be set according to actual needs. In this embodiment, the cross section of the first test plug 441 is square, and the cross section of the first test plug 441 is 20nm to 25nm in size in the first direction. In other embodiments, the first test plug 441 can be configured in other shapes according to process requirements.
When the number of the first test plugs 441 in the logic test area I is plural, the first pitches in the first direction between the adjacent first test plugs 441 are equal, and the second pitches in the second direction between the adjacent first test plugs 441 are equal. The first direction is perpendicular to the second direction. In this embodiment, when the first direction is a horizontal direction (e.g., an X direction in fig. 5), the second direction is a vertical direction (e.g., a Y direction in fig. 5) perpendicular to the horizontal direction. In other embodiments, the first direction is the vertical direction and the second direction is the horizontal direction.
In this embodiment, the first pitch between adjacent first test plugs 441 in the first direction is two to three times the size of the cross section of the first test plug 441 in the first direction. For example, when the cross-section of the first test plug 441 has a size of 21nm in the first direction, a first pitch between adjacent first test plugs 441 in the first direction may be set to 42nm to 63nm.
In the embodiment of the invention, the substrate further comprises SRAM test areas II positioned at two sides of the logic test area I. The test plug includes a second test plug 442 in the third dielectric layer 430 on the SRAM test region II. The second test plug 442 is used for monitoring the formation process of the contact hole of the SRAM region of the SRAM device.
The second dielectric layer 420 is not formed with a metal gate structure, so the second dielectric layer 420 under the second test plug 441 is also not formed with a metal gate structure. Similarly, by removing the metal gate structure, the interference of the optical measurement signal of the metal gate structure to the optical measurement signal of the second test plug 442 can be eliminated, and the accuracy of the optical measurement signal detection of the second test plug can be improved, so that the accurate detection of the forming process of the second test plug can be realized, and the performance of the formed semiconductor structure can be improved.
In this embodiment, the bottom of the second test plug 442 may be in contact with the second dielectric layer 420, i.e., the second test plug 442 penetrates the third dielectric layer 430. In other embodiments, the bottom of the second test plug 442 can also be free from contact with the second dielectric layer 420, i.e., the bottom of the second test plug 442 is located in the third dielectric layer 130.
The arrangement of the second test plugs 442 in the SRAM test region II may be set according to the monitoring requirement of the formation process of the SRAM contact hole in the main pattern region of the SRAM device. For example, arranged on the SRAM test region II, etc., in the same manner as the SRAM contact holes in the SRAM main pattern region.
In the embodiment of the present invention, the shape of the cross section of the second test plug 442 in the SRAM test area II may be set according to actual needs. In this embodiment, the cross section of the second test plug 442 is rectangular, and the cross section of the second test plug has a size of (20 nm-25 nm) x (35 nm-40 nm), that is, the cross section of the second test plug has a size of 20 nm-25 nm in the first direction, and the cross section of the second test plug has a size of 35 nm-40 nm in the second direction. In other embodiments, the cross-section of the second test plug 442 can be configured in other shapes depending on the process requirements.
In a specific implementation, the first test plug 441 in the logic test area I and the second test plug 442 in the SRAM test area II are arranged according to a predetermined number ratio. In the embodiment of the invention, the number ratio between the first test plug and the second test plug is 1: 2-1: 1. in this embodiment, the number ratio of the first test plug to the second test plug is 1:2. for example, the number of first test plugs located on the logic test area I is 2, and the number of second test plugs located on the SRAM test area II on both sides of the logic test area I is 4.
Although the figure shows 2 first test plugs per logical test area I and 4 second test plugs per SRAM test area II. It will be appreciated by those skilled in the art that the number of the first test plugs and the second test plugs in the measuring structure can be more or less, and can be set according to actual process requirements, which is not limited herein.
The test plug in the embodiment of the invention not only comprises the first test plug 441 located on the logic test area I, but also comprises the second test plug 442 located on the SRAM test area II, so that not only can the formation process of the logic area contact hole in the SRAM main pattern area be monitored, but also the formation process of the SRAM contact hole in the SRAM main pattern area can be monitored, thereby improving the application range of the measurement structure in the embodiment of the invention, and saving the working procedures and the cost.
More importantly, in the embodiment of the invention, the combination of the first test plug and the second test plug with different length-width ratios is adopted to form the basic optical measurement unit, so that the sensitivity of the contact Kong Guangxue measurement signal can be enhanced. Specifically, while the optical measurement signals of the test plugs shown in fig. 1 and fig. 2 have only one peak value in a corresponding wavelength region by using the Optical Critical Dimension (OCD) measurement device, in the embodiment of the present invention, the optical measurement signals of the first test plug and the second test plug have two or more peak values in different wavelength regions, which means that the optical signals of the test plugs in the embodiment of the present invention can be detected in a plurality of different wavelength regions, so the sensitivity of the detection of the optical measurement signals of the contact holes can be improved, and the accuracy of the optical measurement signals of the contact holes can be improved, so that more accurate monitoring of the formation process of the contact holes can be realized.
The method of forming the measurement structure in the embodiment of the present invention will be described in detail.
Referring to fig. 6, a substrate 400 is provided.
In this embodiment, the substrate provides a process platform for forming the measurement structure. In this embodiment, the measurement structure is a measurement unit for monitoring a process of forming a contact hole in the SRAM device. In this embodiment, the transistor in the SRAM device is a fin field effect transistor, so as to enhance the control capability of the gate to the channel, and better suppress the short channel effect.
In this embodiment, the substrate is a silicon substrate. In other implementations, the substrate may be a silicon substrate, germanium, silicon carbide, gallium arsenide, indium gallium, or a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or integration.
In this embodiment, the substrate includes a main pattern region and a test pattern region located at a periphery of the main pattern region. The main pattern area is used for forming a semiconductor chip pattern; the test pattern area is used for forming a test pattern for monitoring the forming process of the semiconductor chip pattern on the main pattern area.
Referring to fig. 7, a first dielectric layer 410 is formed on the substrate 400.
In this embodiment, the first dielectric layer 410 and the corresponding dielectric layer in the SRAM main pattern region are formed in the same process step.
In this embodiment, the first dielectric layer is silicon dioxide (SiO 2 ). In other embodiments, the material of the first dielectric layer can also be a low dielectric constant material. The low-dielectric-constant material is a dielectric material with a dielectric constant k less than 3.9.
The first dielectric layer forming process includes a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.
Referring to fig. 8, a second dielectric layer 420 is formed on the first dielectric layer 410.
In this embodiment, the second dielectric layer and the dielectric layer with the metal gate structure formed in the fin field effect transistor in the SRAM main pattern region are formed in the same process step.
The second dielectric layer is made of a low dielectric constant material. In this embodiment, the first dielectric layer is silicon dioxide (SiO 2 )。
The second dielectric layer forming process includes a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.
Referring to fig. 9, a third dielectric layer 430 is formed on the second dielectric layer 420.
In this embodiment, the third dielectric layer and the dielectric layer with the metal gate structure formed in the fin field effect transistor in the SRAM main pattern region are formed in the same process step.
In this embodiment, the third dielectric layer is SiO 2 . In other embodiments, the material of the third dielectric layer can also be a low dielectric constant material.
The second dielectric layer forming process includes a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.
With continued reference to fig. 4, a test plug 440 is formed on the third dielectric layer 430; a metal gate structure is not formed in the second dielectric layer 420 under the test plug 440.
With continued reference to fig. 5, in this embodiment, the substrate includes a logic test region I. The logic test area I is located in a test area of the substrate. The logic test area I is arranged corresponding to a logic area in the SRAM main graph area of the substrate. Accordingly, the test plug 440 includes a first test plug 441 located in the third dielectric layer 430 on the logic test region I.
In this embodiment, the substrate further includes an SRAM test region II located at two sides of the logic test region I. The test plug includes a second test plug 442 in the third dielectric layer 430 on the SRAM test region II. The second test plug 442 is used for monitoring the formation process of the contact hole of the SRAM region of the SRAM device.
The first test plug forming process and the contact hole of the logic test area in the corresponding SRAM device are formed through the same process, and the second test plug forming process and the contact hole of the SRAM test area in the corresponding SRAM device are formed through the same process.
Although the measurement structure in the embodiment of the present invention is different from the logic region in the SRAM main pattern region and the corresponding structure formed in the SRAM region, the first test plug in the embodiment of the present invention is formed by the same process in the same environment as the structure of the contact hole of the logic region in the SRAM main pattern region. Therefore, by monitoring the forming process of the first test plug and the second test plug in the implementation of the invention, accurate monitoring of the forming process of the logic region in the SRAM main pattern region and the contact hole in the SRAM region can be realized.
In this embodiment, the measurement structure is formed on a dicing street in the wafer for dividing different dies, so as to avoid the loss of the useful space of the wafer, improve the utilization rate of the wafer, and save the cost. In other embodiments, the measurement structure may be formed in the main pattern area, and those skilled in the art may set the measurement structure according to actual requirements, which is not limited herein.
According to the scheme provided by the embodiment of the invention, as the metal gate structure below the test plug is removed, the interference of the optical measurement signal of the metal gate structure on the optical measurement signal of the test plug can be eliminated, the accuracy of the detected optical measurement signal of the test plug is improved, the accurate detection of the contact hole forming process can be realized, and the performance of the formed semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A measurement structure, comprising:
a substrate;
a first dielectric layer on the substrate;
a second dielectric layer on the first dielectric layer;
a third dielectric layer on the second dielectric layer;
a test plug in the third dielectric layer; and a metal gate structure is not formed in the second dielectric layer below the test plug.
2. The measurement structure of claim 1, wherein the substrate comprises a logic test region; the test plug includes a first test plug; the first test plug is located in a third dielectric layer over the logic test region.
3. The measurement structure of claim 2, wherein the first test plug has a square cross-section.
4. A measurement structure according to claim 3, wherein the first test plug is a plurality; the first spacing of adjacent first test plugs in the first direction is the same, and the second spacing of adjacent first test plugs in the second direction is the same; the first direction is perpendicular to the second direction.
5. The measurement structure of claim 4, wherein the first direction is a width direction of the first test plug; the first spacing between adjacent first test plugs in the first direction is two to three times the width of the first test plugs.
6. The measurement structure of claim 5, wherein a dimension of a cross-section of the first test plug in the first direction is 20nm to 25nm; the first spacing between adjacent first test plugs in the first direction is 40 nm-75 nm.
7. The measurement structure of any one of claims 2 to 6, wherein the substrate further comprises SRAM test regions on both sides of the logic test region along a first direction;
the test plug further comprises a second test plug; the second test plug is located over the SRAM test region.
8. The measurement structure of claim 7, wherein a ratio of the number of second test plugs on each SRAM test zone to the number of first test plugs on the logic test zone is 1: 2-1: 1.
9. the measurement structure of claim 8, wherein the cross-section of the second test plug is rectangular in shape.
10. The measurement structure of claim 9, wherein a dimension of the second test plug in the first direction is greater than a dimension of the second test plug in the first direction.
11. The measurement structure of claim 10, wherein a cross-section of the second test plug has a dimension in a first direction of 20nm to 25nm and a cross-section of the second test plug has a dimension in a second direction of 35nm to 40nm.
12. The measurement structure of claim 1, wherein the test plug extends through the third dielectric layer.
13. The measurement structure of claim 1, wherein a bottom of the test plug is located in the third dielectric layer.
14. The measurement structure of claim 1, wherein the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are the same or different.
15. The measurement structure of claim 1, wherein the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are all low dielectric constant materials.
16. The measurement structure of claim 1, wherein the materials of the first, second and third dielectric layers are all SiO 2 。
17. A method of forming a measurement structure, comprising:
providing a substrate;
forming a first dielectric layer on the substrate;
forming a second dielectric layer on the first dielectric layer;
forming a third dielectric layer on the second dielectric layer;
forming a test plug in the third dielectric layer; and a metal gate structure is not formed in the second dielectric layer below the test plug.
18. The method of forming a measurement structure of claim 17, wherein the substrate comprises a logic test region; forming a test plug in the third dielectric layer, including:
and forming a first test plug in the third dielectric layer above the logic test region.
19. The method of forming a measurement structure of claim 18, wherein the substrate further comprises SRAM test regions on both sides of the logic test region; forming a test plug in the third dielectric layer, further comprising:
and forming a second test plug in the third dielectric layer above the logic test region.
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