CN113740809A - Multi-channel extensible broadband excitation generation device and method - Google Patents
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Abstract
The invention discloses a multi-channel extensible broadband excitation generating device and a method, wherein the device comprises a CPCI case, an embedded main control module, a clock and synchronous distribution module and more than three excitation generating modules, wherein the embedded main control module, the clock and synchronous distribution module and the excitation generating modules are arranged in the CPCI case; the control signals and the data signals among the embedded main control module, the clock and synchronous distribution module and each excitation generation module are transmitted through a CPCI bus; the clock and synchronous distribution module receives a clock signal, a time sequence signal and a synchronous signal which are input from the outside through a radio frequency coaxial cable; the embedded main control module controls each module to work according to the configuration parameters, so that each excitation generation module generates an excitation signal. The excitation generating device disclosed by the invention provides powerful support for the research of an active phased array radar system, and has great application potential in the fields of electrical engineering, industrial automation, intelligent control, communication electronics and the like.
Description
Technical Field
The invention belongs to the technical field of active phased array radar systems, and particularly relates to a multi-channel extensible broadband excitation signal generation device and method for an active phased array radar transmitting system in the field.
Background
The current excitation signal generating device is mainly implemented by a phase-locked frequency synthesis (PLL) technology, a direct digital frequency synthesis (DDS) technology, and the like. The phase-locked frequency synthesis technology is characterized in that the phase comparison is carried out on the output frequency and the reference frequency in a phase discriminator, and then the voltage-controlled oscillator is controlled by an error voltage generated after the phase comparison to output an excitation signal; and the phase-locked frequency synthesis technology can only generate discrete frequency, when the requirement on frequency resolution is high and output channels are more, a multi-loop frequency synthesizer is needed, and additional equipment is inevitably added, so that the system is complicated.
The direct digital frequency synthesis (DDS) directly generates signals of various frequencies by controlling a speed of change of a phase. The frequency conversion method is far superior to the traditional frequency synthesis technology in the aspects of broadband, frequency resolution, frequency conversion time, phase continuity (phase change continuity), modulation output (various modulations can be easily realized on output signals), integration and the like. However, the frequency and phase information are both represented by digital values in the DDS technology, which inevitably generates quantization precision errors and quantization noise, thereby causing amplitude distortion and phase distortion of output signals and causing larger stray of the output signals of the DDS; meanwhile, the output signal band of the DDS is limited (the highest frequency is less than 0.5fs, and higher fs requires higher operating frequency of the device), which is one of the main problems limiting the development and application of the DDS technology.
With the rapid development of scientific technology and the continuous improvement of automation degree, software radio technology is rapidly developed, and digital up-conversion (DUC) is used as the core technology of software radio, and has the advantages of high frequency resolution, wide frequency band, short frequency conversion time, capability of outputting any waveform, easiness in program control, flexibility in use, high cost performance, low power consumption, small size, light weight, high reliability and the like due to the fully digital structure, so that the DUC becomes the first choice of engineering application in the field of high-frequency signal generation.
In order to realize space power synthesis and antenna beam fast scanning, an active phased array radar system needs a radar excitation signal generation device with a precisely controllable multichannel phase as a support, and in order to realize multiple functions of early warning, tracking, guiding and even detecting, modern phased array radars put forward a very high requirement on the excitation signal generation device: the multi-channel phase-dependent controllable excitation signal generator can generate multi-channel phase-dependent controllable excitation signals; secondly, the expansion is convenient, and the system capacity expansion is convenient; thirdly, high frequency resolution is required to reach the micro hertz level; fourthly, high phase control precision is achieved; fifthly, the space beam scanning can be rapidly carried out, and the beam switching time is short; sixthly, any waveform can be generated according to the baseband signal; seventhly, the frequency can be swept quickly in a broadband range, and the frequency conversion time is short.
Disclosure of Invention
The invention aims to solve the technical problem of providing a multi-channel extensible broadband excitation generating device and method applied to a short-wave and ultrashort-wave active phased array radar system.
The invention adopts the following technical scheme:
in a multi-channel scalable broadband excitation generating device, the improvement comprising: the CPCI case comprises a CPCI case, an embedded main control module, a clock and synchronous distribution module and more than three excitation generation modules, wherein the embedded main control module, the clock and synchronous distribution module and the excitation generation modules are arranged in the CPCI case; the control signals and the data signals among the embedded main control module, the clock and synchronous distribution module and each excitation generation module are transmitted through a CPCI bus; the clock and synchronous distribution module receives a clock signal, a time sequence signal and a synchronous signal which are input from the outside through a radio frequency coaxial cable, and transmits the clock signal, the time sequence signal and the synchronous signal to each excitation generation module through the time sequence connection module; the embedded main control module controls each module to work according to the configuration parameters, so that each excitation generation module generates an excitation signal; the clock and synchronous distribution module comprises a main clock synchronous distribution circuit, a time sequence control circuit and a BIT detection circuit and is used for distributing clock signals and synchronous signals to each excitation generation module and generating system time sequence signals, and each excitation generation module has the same structure and comprises an FPGA and eight excitation generation circuits, the clock synchronous distribution circuit, the time sequence control circuit and the BIT detection circuit which are electrically connected with the FPGA.
Furthermore, the embedded main control module is a wide-temperature CPCI mainboard.
Furthermore, the clock and synchronous distribution module realizes the distribution of the clock and synchronous signals through an AD9516 chip, and the system time sequence signals are generated by controlling the FPGA through the PCI9054 by the embedded main control module.
Furthermore, the frequency range of the excitation signal output by the excitation generating module is 3 MHz-300 MHz, and the continuous wave, pulse, amplitude modulation, frequency modulation, 2ASK and 2FSK signal forms are output.
Furthermore, each excitation generating circuit of the excitation generating module has the same structure and comprises an AD9788 chip, a low-pass filter and an operational amplifier which are electrically connected with the FPGA, the generated excitation signal is sent to a radio frequency output channel, and the detection signal is sent to a BIT detection circuit.
Furthermore, a clock synchronization distribution circuit of the excitation generation module uses an AD9516 chip to distribute clocks and synchronization signals, the AD9516 chip outputs the clocks and synchronization signals to each AD9788 chip, the wiring length of the clocks and synchronization signals is equal, and the error is less than 10 mil.
Furthermore, the BIT detection circuit of the excitation generation module adopts a diode detection circuit to detect the amplitude of the clock signal and the synchronous signal output by the clock synchronous distribution circuit, adopts an FPGA counter to detect the frequency of the clock signal and the synchronous signal output by the clock synchronous distribution circuit, adopts the diode detection circuit to detect the amplitude of the excitation signal output by each excitation generation circuit, uses an FPGA control electronic switch to gate the excitation signal output by each excitation generation circuit to input into the diode detection circuit, and finally uses the FPGA to judge the detection result and report the detection result to the embedded main control module.
Furthermore, the excitation channel is expanded by adding an excitation generation module or a cascade device.
In a method of generating a stimulus using the apparatus described above, the improvement comprising the steps of:
the multichannel extensible broadband excitation generating device carries out periodic self-checking, the self-checking content comprises the amplitude and the frequency of a clock signal and a synchronous signal of each excitation generating module, the amplitude of an excitation signal output by each excitation generating circuit and the amplitude and the frequency of a clock signal and a synchronous signal output by a clock and synchronous distribution module, and if the detection signal is abnormal after self-checking, abnormal information can be displayed through the embedded main control module;
step 2, modulating baseband data to generate:
directly modulating a digital modulation signal to a radio frequency working frequency through digital up-conversion, firstly generating modulation baseband data in an embedded main control module, wherein the generated modulation baseband data comprises sine waves, square waves, half waves, triangular waves and the like;
and step 3: setting parameters:
the control parameters and data sent by the embedded main control module comprise: working frequency, working channels, channel phases and modulation baseband data, configuring an AD9788 chip by each excitation generation module through an SPI bus according to control parameters, storing the modulation baseband data in an RAM of an FPGA, and setting modulation timing sequence parameters by a clock and synchronous distribution module according to the modulation frequency;
step 4, a work flow:
firstly, the clock and synchronous distribution module outputs time sequence signals to each excitation generation module, the excitation generation modules synchronously output the time sequence signals to the FPGA, when the FPGA responds to a first time sequence signal, multichannel baseband data are simultaneously output to each AD9788 chip, the baseband data are subjected to frequency mixing modulation with the digital control oscillator after being subjected to interpolation and filtering in the AD9788 chip, and finally multichannel amplitude modulation signal output is realized according to the working frequency, amplitude and phase synchronization set by the register.
Go toStep 2, outputting a sine standard amplitude modulation signal and setting a carrier signal v0(t)＝V0cosω0t, wherein V0Is the amplitude, omega, of the carrier signal0Is the carrier signal angular frequency; modulated signal vΩ(t)＝VΩcos Ω t, wherein VΩIs the modulation signal amplitude, omega is the modulation signal angular frequency;
the amplitude of the standard amplitude-modulated signal is expressed as:
a mathematical expression of a standard amplitude-modulated signal is thus obtained: v (t) ═ V0[1+ma cosΩt]cosω0t, degree of modulation in formula
0＜ma≤1，KdIs a proportionality constant;
the discrete mathematical expression can be obtained by the mathematical expression of the standard amplitude modulation signal: v (n) ([ 1+ m)avΩ(n)]v0(n) wherein vΩ(n) is a discrete sequence of modulated signals, v0(n) is a discrete sequence of carrier signals, and the modulated signal v is known from a discrete expressionΩ(n) first and modulation maMultiplying, then adding with the quantization value, namely, the baseband data of the standard amplitude modulation signal can be obtained after a direct current level is superposed on the signal, the embedded main control module generates modulation baseband data according to the formula and the method and provides the modulation baseband data to the AD9788, the modulation baseband data is subjected to interpolation filtering processing and then is subjected to frequency mixing modulation with a carrier signal generated by a digital control oscillator in the AD9788, and the standard amplitude modulation signal is finally generated through DAC conversion.
The invention has the beneficial effects that:
the excitation generating device disclosed by the invention provides powerful support for the research of an active phased array radar system, has huge application potential in the fields of electrical engineering, industrial automation, intelligent control, communication electronics and the like, and has the following advantages compared with the traditional frequency synthesis technology:
(1) the device adopts a unique synchronization algorithm and a synchronization time sequence, and provides a solid guarantee for the application of the device in an active phased array radar system;
(2) the modularized design is adopted, and excitation channels can be expanded by adding an excitation generation module or a cascade device, so that the requirements of different phased array systems are met, and the maintenance is convenient;
(3) the signal forms are various, the conventional design outputs signal forms such as continuous waves, pulses, amplitude modulation, frequency modulation, 2ASK, 2FSK and the like, and the capacity of loading different baseband signals and outputting any waveform is realized;
(4) the working modes are various, and the device has the working modes of cyclic frequency sweep, round-trip frequency sweep, double-frequency double-beam, fast beam sweep, data/broadcast and the like;
(5) the frequency band is wide, the sampling clock frequency is 720MHz, and the theoretical output frequency can reach 360MHz at most;
(6) the frequency resolution is high, when the reference clock frequency is 180MHz, the sampling clock frequency is 720MHz, and the theoretical frequency resolution can reach 0.167 Hz;
(7) the output phase control precision is high, and the theoretical phase control precision can reach 0.005 ℃;
(8) the digital up-conversion technology is adopted to reduce the stray caused by factors such as the phase truncation error and the amplitude quantization error of the DDS, the non-ideal characteristic of the DAC and the like, and the higher signal spectrum purity can be realized;
(9) the frequency agility has phase continuity, the space beam scanning can be rapidly carried out, the beam switching time is extremely short and can reach nanosecond level; the frequency sweep can be rapidly carried out in a broadband range, and the frequency conversion time is extremely short and can reach nanosecond level; the operation is simple, the human-computer interface is good, and the BIT alarm function is realized; the equipment amount is less, the cost is low, and the reliability is high.
The excitation generating method disclosed by the invention is matched with the excitation generating device, can generate multi-path phase-related controllable excitation signals, and can be applied to short-wave and ultrashort-wave active phased array radar systems.
Drawings
FIG. 1 is a block diagram schematically showing the composition of a stimulus generating device disclosed in embodiment 1 of the present invention;
FIG. 2 is a block diagram schematically showing the clock and synchronization distribution module in the excitation generating apparatus according to embodiment 1 of the present invention;
FIG. 3 is a block diagram schematically showing the components of an excitation generating module in the excitation generating apparatus disclosed in embodiment 1 of the present invention;
FIG. 4 is a block diagram of a channel expansion cascade;
FIG. 5 is a schematic of amplitude modulation;
FIG. 6 is a flow chart of the operation of the stimulus control software.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In embodiment 1, this embodiment discloses a multi-channel scalable broadband excitation generating device, which employs a digital up-conversion (DUC) technology and a CPCI architecture, and as shown in fig. 1, hardware includes a CPCI chassis, an embedded main control module, a clock and synchronization distribution module, and a plurality of excitation generating modules, which are installed in the CPCI chassis. The control signals and the data signals among the embedded main control module, the clock and synchronous distribution module and each excitation generation module are transmitted through a CPCI bus, the clock and synchronous distribution module receives clock signals, timing signals and synchronous signals input from the outside through a radio frequency coaxial cable, and the clock and synchronous distribution module transmits the clock signals, the timing signals and the synchronous signals to each excitation generation module through the timing connection module. The power supply line and the control signal line of the excitation generating device are connected using a dedicated specification cable and a connector. The software includes stimulus control software, timing control software, and stimulus generation software. The excitation control software runs in the embedded main control module to provide a friendly human-computer interface and configuration parameters, the embedded main control module controls each module to work according to the configuration parameters, so that each excitation generation module generates excitation signals, the time sequence control software runs in an FPGA of the clock and synchronous distribution module, and the clock and synchronous distribution module is controlled to generate clocks, time sequences and synchronous signals according to the configuration parameters; and the excitation generating software runs in the FPGA of the excitation generating module and controls the excitation generating module to generate an excitation signal according to the configuration parameters. The clock and synchronous distribution module comprises a main clock synchronous distribution circuit, a time sequence control circuit and a BIT detection circuit and is used for distributing clock signals and synchronous signals to each excitation generation module and generating system time sequence signals, and each excitation generation module has the same structure and comprises an FPGA and eight excitation generation circuits, the clock synchronous distribution circuit, the time sequence control circuit and the BIT detection circuit which are electrically connected with the FPGA.
The embedded main control module is a wide-temperature 6U CPCI mainboard (CPCI-6210/710Q of the company of Leisha and Classification), and mainly has the functions of executing excitation control software instructions and bus communication.
The clock and synchronous distribution module is mainly used for generating and distributing a plurality of paths of reference clock signals, timing signals and synchronous signals and respectively providing the reference clock signals, the timing signals and the synchronous signals to each excitation generation module. As shown in fig. 2, the clock and synchronization distribution module realizes the distribution of the clock and synchronization signals through an AD9516 chip, the system timing signal is generated by the embedded main control module controlling the FPGA through the PCI9054, and each excitation generation module starts to work according to the timing signal.
As shown in fig. 3, the excitation generating module is a core module of the excitation generating device, and adopts a CPCI + FPGA + DAC architecture, and each excitation generating module performs digital up-conversion in the FPGA and the DAC, modulates a baseband signal to a medium-high frequency in a digital manner, and finally converts the baseband signal into an analog excitation signal through the DAC for output.
The excitation generating modules are identical in structure and respectively comprise an AD9788 chip, a low-pass filter and an operational amplifier which are electrically connected with the FPGA, the signal generating function is realized by adopting a digital up-conversion technology, the generated excitation signals are sent to a radio frequency output channel, and the detection signals are sent to a BIT detection circuit. The FPGA of the excitation generation module mainly realizes the functions of loading and calling the digital up-conversion baseband data, and the like, and the interpolation filtering and mixing of the digital up-conversion are realized by an AD9788 chip. The AD9788 chip is a dual-channel wide dynamic digital-to-analog converter (DAC) chip produced by ADI company, provides 800MS/s sampling rate, has very high integration level, is internally provided with NCO, has the highest output frequency of 400MHz and 32 bits of frequency control words, and has the frequency resolution of 0.167Hz, the phase control words of 16 bits and the phase control precision of 0.005 degree when the system clock is 150 MHz.
The low-pass filter is LDT-450W750 in model, the passband is DC-400 MHz, the cutoff frequency is 440MHz, the inhibition of the stopband 580-750 MHz is better than 20dB, the inhibition of the stopband 750-1800 MHz is better than 40dB, and the insertion loss is less than 0.3 dB. In order to ensure the phase amplitude consistency of multi-channel excitation signals, the phase consistency of low-pass filters produced in the same batch is required to be within 3 degrees, and the amplitude consistency is required to be within 1 dB.
The operational amplifier adopts SBF5089 to amplify, has wide voltage input, low distortion and good amplitude flatness, and is suitable for being used as the output drive of any waveform generator.
The clock synchronization distribution circuit of the excitation generation module realizes the distribution of clocks and synchronous signals by a plurality of AD9516 chips, in order to enable the phased array radar transmitting signal to achieve the maximum radiation power in a certain direction during working and realize the best space power synthesis effect, the phase synchronization of the excitation signals of all channels is important, so in order to ensure that each AD9788 chip can work synchronously, the reference clock signal and the synchronous signal output to each AD9788 chip by the AD9516 chip are required to be strictly equal in routing, and the error is less than 10 mil.
The timing control circuit of the excitation generating module is mainly realized by PCI9054 and FPGA, and the main function of the timing control circuit is to provide data and address buffering and forwarding for the excitation generating module and generate various control signals.
The phased array radar system adopts the DUC to output the excitation signal, and if the reference clock of the excitation signal is in fault, the excitation signal output by the DUC is inevitably incorrect, so that the power amplification part of the transmitting system can be damaged, and the BIT detection circuit of the excitation generation module is indispensable.
The BIT detection circuit mainly has the functions of detecting the amplitude and the frequency of a clock signal and a synchronous signal output by the clock synchronous distribution circuit and detecting the amplitude of each channel excitation signal output by the excitation generation circuit. The BIT detection circuit detects the amplitudes of the clock signal and the synchronous signal by adopting a diode detection circuit; and detecting the frequency of the clock signal and the synchronous signal by using an FPGA counter, and finally, comprehensively judging a detection result by the FPGA and reporting the detection result to the embedded main control module to excite the control software. The amplitude of each channel excitation signal is realized through a diode detection circuit, the FPGA controls an electronic switch to gate each channel excitation signal to be input into the diode detection circuit, and when the excitation signal is input, the diode detection circuit outputs high level to the FPGA.
The excitation generating module outputs excitation signals with the frequency range of 3 MHz-300 MHz and outputs continuous wave, pulse, amplitude modulation, frequency modulation, 2ASK and 2FSK signal forms. The integrated, modularized and miniaturized design is adopted, the work is stable and reliable, the shock resistance is considered in the structural design, and the integrated, modularized and miniaturized integrated ship-mounted and vehicle-mounted integrated anti-seismic fixing station can be used for both ship-mounted and vehicle-mounted vehicles and can also be used as a fixing station.
In order to enable the phased array radar to achieve the maximum radiation power in a certain direction when transmitting signals, and achieve the best space power synthesis effect, the phase synchronization of excitation signals of all channels is of great importance. As shown in fig. 4, the multi-channel extendable broadband excitation generating apparatus may extend the excitation channels by adding an excitation generating module or a cascade apparatus, so how to ensure stable phase synchronization of hundreds of output channel signals becomes a key for successful application of the apparatus. The device adopts a unique synchronization algorithm and a unique synchronization time sequence, and perfectly solves the problem of phase synchronization among a plurality of channels, a plurality of modules and a plurality of devices.
The specific synchronization process is that the upper control equipment generates a reference clock signal, a synchronization signal and a time sequence signal and simultaneously distributes each device and each excitation generating module in each device; the reference clock signal ensures that clocks used by devices at all levels and the excitation generating module are in synchronous phase coherence, and the synchronous correction algorithm is adopted to simultaneously multiply the frequency of the clock signal to 720MHz in an AD9788 chip, so that the device is ensured that no uncertain phase difference exists between clocks of all channels when being powered on and started each time; the time sequence signal, namely the working pulse signal of the equipment, is generated by the upper control equipment and is triggered and transmitted by the reference clock signals of all stages of devices and excitation generating modules, so that the synchronous output of the digital baseband signals of all the excitation generating modules FPGA is ensured, and the phase of the digital baseband signals and the reference clock signals are fixed without a metastable state; the last synchronization measure is that a synchronization signal is used for synchronizing DAC chips AD9788 of all excitation generating modules, the AD9788 chip has two master-slave synchronization signal modes of pulse and PN code (pseudo-random noise code) modulation and demodulation, and when the synchronization signal triggers an internal clock generating state machine of the AD9788 chip to the same state and the states of NCO phase accumulators are the same, a plurality of DACs complete synchronization mutually. The method finally solves the phase synchronization problem among a plurality of channels, a plurality of modules and a plurality of devices of the multi-channel extensible broadband excitation generating device.
The embodiment also discloses an excitation generation method, which uses the device and comprises the following steps:
the multichannel extensible broadband excitation generating device can carry out periodic self-checking, and the self-checking content comprises: after self-checking, if the detection signal is abnormal, the detection signal is displayed on an excitation control software interface;
step 2, modulating baseband data to generate:
the traditional analog modulation signal source mostly adopts analog circuits such as an analog multiplier and the like to realize amplitude modulation signals, and has the defects of low signal quality, unstable frequency, unquantized parameter setting, low precision, poor controllability, weak anti-interference capability and the like.
The amplitude modulation signal output by the multi-channel extensible broadband excitation generating device adopts a digital up-conversion technology, and the digital modulation signal is directly modulated to the radio frequency working frequency through the DUC, so that the purpose of analog modulation is achieved, and the defects of the traditional analog modulation signal source are overcome.
The multi-channel expandable broadband excitation generating device can output sine, square wave, half wave, triangular wave and other amplitude modulation signals, the sine standard amplitude modulation signals are output in the embodiment, and the amplitude modulation schematic diagram is shown in fig. 5.
Set carrier signal v0(t)＝V0 cosω0t, wherein V0Is the amplitude, omega, of the carrier signal0Is the carrier signal angular frequency; modulated signal vΩ(t)＝VΩcos Ω t, wherein VΩIs the modulation signal amplitude, omega is the modulation signal angular frequency;
the amplitude of the standard amplitude-modulated signal is expressed as:
a mathematical expression of a standard amplitude-modulated signal is thus obtained: v (t) ═ V0[1+ma cosΩt]cosω0t in the formula
Called modulation degree, is the main parameter of standard amplitude modulation, which characterizes the modulation depth of the modulated wave, 0 < ma≤1，KdIs a proportionality constant;
the discrete mathematical expression can be obtained by the mathematical expression of the standard amplitude modulation signal: v (n) ([ 1+ m)avΩ(n)]v0(n) wherein vΩ(n) is a discrete sequence of modulated signals, v0(n) is a discrete sequence of carrier signals, and the modulated signal v is known from a discrete expressionΩ(n) first and modulation maMultiplying, adding with quantized value (i.e. adding a DC level on the signal) to obtain baseband data of standard amplitude modulation signal, generating modulated baseband data by the embedded main control module according to the above formula and method and providing it to AD9788, interpolating, filtering, and generating with the digital controlled oscillator in AD9788And carrying out mixing modulation on the carrier signal, and finally generating a standard amplitude modulation signal through DAC conversion.
And step 3: setting parameters:
and exciting the control software to send control parameters and data, wherein the control parameters and the data comprise: the excitation generating software in each excitation generating module configures an AD9788 chip through an SPI bus according to control parameters and stores the modulation baseband data in an RAM of an FPGA, the operation flow of the excitation controlling software is shown in figure 6, and the timing sequence controlling software in a clock and synchronous distribution module sets modulation timing sequence parameters according to the modulation frequency;
step 4, a work flow:
after the excitation control software controls to start working, firstly, the clock and synchronous distribution module outputs a time sequence signal to each excitation generation module, the excitation generation modules synchronously output the time sequence signal to the FPGA, when the FPGA responds to the first time sequence signal, multichannel baseband data are simultaneously output to each AD9788 chip, the baseband data are subjected to interpolation and filtering in the AD9788 chip and then are subjected to frequency mixing modulation with NCO, and finally the purpose of outputting multichannel amplitude modulation signals can be achieved according to the working frequency, amplitude and phase synchronization set by the register.
Claims (10)
1. A multi-channel scalable broadband excitation generating device, characterized by: the CPCI case comprises a CPCI case, an embedded main control module, a clock and synchronous distribution module and more than three excitation generation modules, wherein the embedded main control module, the clock and synchronous distribution module and the excitation generation modules are arranged in the CPCI case; the control signals and the data signals among the embedded main control module, the clock and synchronous distribution module and each excitation generation module are transmitted through a CPCI bus, the clock and synchronous distribution module receives clock signals, timing signals and synchronous signals input from the outside through a radio frequency coaxial cable, and the clock and synchronous distribution module transmits the clock signals, the timing signals and the synchronous signals to each excitation generation module through a timing connection module; the embedded main control module controls each module to work according to configuration parameters, so that each excitation generation module generates excitation signals, the clock and synchronous distribution module comprises a main clock synchronous distribution circuit, a time sequence control circuit and a BIT detection circuit, the clock and synchronous distribution module is used for distributing clock signals and synchronous signals to each excitation generation module and generating system time sequence signals, the structures of the excitation generation modules are the same, and each excitation generation module comprises an FPGA and eight excitation generation circuits, a clock synchronous distribution circuit, a time sequence control circuit and a BIT detection circuit which are electrically connected with the FPGA.
2. The multi-channel scalable broadband excitation generating device of claim 1, wherein: the embedded main control module is a wide-temperature CPCI mainboard.
3. The multi-channel scalable broadband excitation generating device of claim 1, wherein: the clock and synchronous distribution module realizes the distribution of clock and synchronous signals through an AD9516 chip, and system time sequence signals are generated by an embedded main control module through controlling an FPGA through a PCI 9054.
4. The multi-channel scalable broadband excitation generating device of claim 1, wherein: the excitation generating module outputs excitation signals with the frequency range of 3 MHz-300 MHz and outputs continuous wave, pulse, amplitude modulation, frequency modulation, 2ASK and 2FSK signal forms.
5. The multi-channel scalable broadband excitation generating device of claim 1, wherein: the excitation generating modules are identical in structure and respectively comprise an AD9788 chip, a low-pass filter and an operational amplifier which are electrically connected with the FPGA, the generated excitation signals are sent to a radio frequency output channel, and the detection signals are sent to a BIT detection circuit.
6. The multi-channel scalable broadband excitation generating device of claim 5, wherein: the clock synchronization distribution circuit of the excitation generation module uses the AD9516 chip to distribute the clock and the synchronous signal, the AD9516 chip outputs the clock and the synchronous signal of each AD9788 chip, the wiring length is equal, and the error is less than 10 mil.
7. The multi-channel scalable broadband excitation generating device of claim 1, wherein: the BIT detection circuit of the excitation generation module adopts a diode detection circuit to detect the amplitude of a clock signal and a synchronous signal output by a clock synchronous distribution circuit, adopts an FPGA counter to detect the frequency of the clock signal and the synchronous signal output by the clock synchronous distribution circuit, adopts the diode detection circuit to detect the amplitude of an excitation signal output by each excitation generation circuit, uses an FPGA control electronic switch to gate the excitation signal output by each excitation generation circuit to input into the diode detection circuit, and finally judges a detection result by the FPGA and reports the detection result to the embedded main control module.
8. The multi-channel scalable broadband excitation generating device of claim 1, wherein: the excitation channel is expanded by adding an excitation generation module or a cascade device.
9. A method of generating a stimulus using the apparatus of claim 1, comprising the steps of:
step 1, equipment self-checking:
the multichannel extensible broadband excitation generating device carries out periodic self-checking, the self-checking content comprises the amplitude and the frequency of a clock signal and a synchronous signal of each excitation generating module, the amplitude of an excitation signal output by each excitation generating circuit and the amplitude and the frequency of a clock signal and a synchronous signal output by a clock and synchronous distribution module, and if the detection signal is abnormal after self-checking, abnormal information can be displayed through the embedded main control module;
step 2, modulating baseband data to generate:
directly modulating a digital modulation signal to a radio frequency working frequency through digital up-conversion, firstly generating modulation baseband data in an embedded main control module, wherein the generated modulation baseband data comprises sine waves, square waves, half waves and triangular waves;
and step 3: setting parameters:
the control parameters and data sent by the embedded main control module comprise: working frequency, working channels, channel phases and modulation baseband data, configuring an AD9788 chip by each excitation generation module through an SPI bus according to control parameters, storing the modulation baseband data in an RAM of an FPGA, and setting modulation timing sequence parameters by a clock and synchronous distribution module according to the modulation frequency;
step 4, a work flow:
firstly, the clock and synchronous distribution module outputs time sequence signals to each excitation generation module, the excitation generation modules synchronously output the time sequence signals to the FPGA, when the FPGA responds to a first time sequence signal, multichannel baseband data are simultaneously output to each AD9788 chip, the baseband data are subjected to frequency mixing modulation with the digital control oscillator after being subjected to interpolation and filtering in the AD9788 chip, and finally multichannel amplitude modulation signal output is realized according to the working frequency, amplitude and phase synchronization set by the register.
10. The excitation generation method according to claim 9, wherein: step 2, outputting a sine standard amplitude modulation signal and setting a carrier signal v0(t)＝V0 cosω0t, wherein V0Is the amplitude, omega, of the carrier signal0Is the carrier signal angular frequency; modulated signal vΩ(t)＝VΩcos Ω t, wherein VΩIs the modulation signal amplitude, omega is the modulation signal angular frequency;
the amplitude of the standard amplitude-modulated signal is expressed as:
a mathematical expression of a standard amplitude-modulated signal is thus obtained: v (t) ═ V0[1+macosΩt]cosω0t, degree of modulation in formula
KdIs a proportionality constant;
the discrete mathematical expression can be obtained by the mathematical expression of the standard amplitude modulation signal: v (n) ([ 1+ m)avΩ(n)]v0(n) wherein vΩ(n) is a discrete sequence of modulated signals, v0(n) is a discrete sequence of carrier signals, and modulation is known from discrete expressionsSignal vΩ(n) first with modulation maMultiplying, then adding with the quantization value, namely, the baseband data of the standard amplitude modulation signal can be obtained after a direct current level is superposed on the signal, the embedded main control module generates modulation baseband data according to the formula and the method and provides the modulation baseband data to the AD9788, the modulation baseband data is subjected to interpolation filtering processing and then is subjected to frequency mixing modulation with a carrier signal generated by a digital control oscillator in the AD9788, and the standard amplitude modulation signal is finally generated through DAC conversion.
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