CN113726706A - Method, device and storage medium for improving demodulation precision of D8PSK signal - Google Patents
Method, device and storage medium for improving demodulation precision of D8PSK signal Download PDFInfo
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Abstract
The application discloses a method, a device and a storage medium for improving demodulation precision of a D8PSK signal, relates to the technical field of signal demodulation, and solves the problems of slow frequency offset estimation time, long synchronization time and large resource consumption of an algorithm in the prior art, wherein the method comprises the following steps: acquiring an intermediate frequency sampling signal, performing down-conversion processing, and determining a zero intermediate frequency signal; eliminating inherent phase difference, generating relative phase, determining I, Q paths of zero phase difference signals, sampling the signals, determining I, Q paths of sampling signals, acquiring a plurality of sine and cosine values corresponding to synchronous sequence signals, performing correlation calculation with I, Q paths of sampling signals, determining a plurality of I, Q paths of correlation values, and calculating an average value and a synchronous time; compensating the correlation value data I, Q on the zero phase difference signal, performing arc tangent calculation, and determining an angle value; sampling the angle value, and outputting binary code elements of the angle value; the algorithm resources are saved, and the angle resolving precision is improved.
Description
Technical Field
The present application relates to the field of signal demodulation technologies, and in particular, to a method, an apparatus, and a storage medium for improving demodulation accuracy of a D8PSK signal.
Background
The VHF data broadcast signal is based on 8-in differential phase shift keying modulated burst signal, the D8PSK signal belongs to multi-system dependent keying signal, and the currently adopted method comprises coherent demodulation, differential demodulation and the like. The differential demodulation mode does not need to be generated locally on carriers with strictly same frequency and same direction at a transmitting end, and is relatively easy to realize. Coherent demodulation needs to generate coherent carriers with the same frequency and phase, and multiply the coherent carriers with received intermediate frequency signals to recover baseband signals.
However, in the process of implementing differential demodulation, the frequency deviation of the receiving end is not considered, and accurate demodulation cannot be implemented when the frequency deviation is large. At present, a coherent demodulation mode is adopted for a VDB signal, frequency offset is estimated through a signal front-end training sequence in a demodulation process, and frequency offset compensation is carried out on a local carrier.
Disclosure of Invention
By providing the method, the device and the storage medium for improving the demodulation precision of the D8PSK signal, the embodiments of the application solve the problems of slow frequency offset estimation time, long synchronization time and large resource consumption of an algorithm in the prior art, save algorithm resources and improve angle resolving precision.
In a first aspect, an embodiment of the present invention provides a method for improving demodulation accuracy of a D8PSK signal, where the method includes:
acquiring an intermediate frequency sampling signal;
performing down-conversion processing on the intermediate frequency sampling signal to determine a zero intermediate frequency signal;
eliminating inherent phase difference in the zero intermediate frequency signal, generating a relative phase, and determining an I path of zero phase difference signal and a Q path of zero phase difference signal;
sampling the I path of zero phase difference signal and the Q path of zero phase difference signal, and determining an I path of sampling signal and a Q path of sampling signal;
acquiring a plurality of sine and cosine values corresponding to a synchronous sequence signal, respectively carrying out correlation calculation on the sine and cosine values and the I path sampling signal and the Q path sampling signal, and determining a plurality of I path correlation values and a plurality of Q path correlation values;
calculating an average value of the I-path correlation values, and determining the peak time of the average value as the synchronization time;
compensating the I path correlation value and the Q path correlation value data to the I path zero phase difference signal and the Q path zero phase difference signal according to the phase of the synchronous moment, and determining an I path compensation signal and a Q path compensation signal;
performing arc tangent calculation on the I path compensation signal and the Q path compensation signal to determine an angle value;
and sampling the angle value, and outputting a binary code element to the angle value.
With reference to the first aspect, in a possible implementation manner, the down-converting the intermediate frequency sampling signal includes: and mixing the local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter.
With reference to the first aspect, in one possible implementation manner, the eliminating an inherent phase difference in the zero intermediate frequency signal to generate a relative phase includes:
delaying both the intermediate frequency sampling signal and the local carrier signal by one symbol period;
mixing and low-pass filtering the intermediate frequency sampling signal delayed by one symbol period by using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period;
determining a phase in the zero intermediate frequency signal delayed by one symbol period as the relative phase.
With reference to the first aspect, in a possible implementation manner, the determining an I-path zero-difference signal and a Q-path zero-difference signal includes: and performing cross product operation on the zero intermediate frequency signal.
With reference to the first aspect, in one possible implementation manner, the determining the I-path sampling signal and the Q-path sampling signal includes: and performing 100-time extraction on the I path of zero phase difference signal and the Q path of zero phase difference signal.
With reference to the first aspect, in a possible implementation manner, the calculating the average value of the I-path correlation values includes determining whether the synchronization sequence signal is aligned with the I-path sampling signal, and when the determination result is that the synchronization sequence signal is aligned, summing and averaging according to the I-path correlation values to determine the average value.
In a second aspect, an embodiment of the present invention provides an apparatus for improving demodulation accuracy of a D8PSK signal, where the apparatus includes:
the signal acquisition module is used for acquiring an intermediate frequency sampling signal;
the signal down-conversion module is used for performing down-conversion processing on the intermediate frequency sampling signal and determining a zero intermediate frequency signal;
the signal zero phase difference calculation module is used for eliminating inherent phase difference in the zero intermediate frequency signal, generating a relative phase, and determining an I path of zero phase difference signal and a Q path of zero phase difference signal;
the signal sampling module is used for sampling the I path of zero phase difference signal and the Q path of zero phase difference signal and determining an I path of sampling signal and a Q path of sampling signal;
the correlation value calculation module is used for acquiring a plurality of sine and cosine values corresponding to the synchronous sequence signals, respectively performing correlation calculation on the sine and cosine values and the I-path sampling signals and the Q-path sampling signals, and determining a plurality of I-path correlation values and a plurality of Q-path correlation values;
the average value determining module is used for calculating the average value of the I-path correlation values and determining the peak value time of the average value as the synchronization time;
the compensation module is used for compensating the I-path correlation value and the Q-path correlation value data to the I-path zero-phase difference signal and the Q-path zero-phase difference signal according to the phase of the synchronous moment, and determining an I-path compensation signal and a Q-path compensation signal;
the calculation module is used for performing arc tangent calculation on the I path of compensation signal and the Q path of compensation signal to determine an angle value;
and the output module is used for sampling the angle value and outputting a binary code element of the angle value.
With reference to the second aspect, in one possible implementation manner, the signal down conversion module is configured to: and mixing the local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter.
With reference to the second aspect, in one possible implementation manner, the signal zero phase difference calculation module is configured to eliminate an inherent phase difference in the zero intermediate frequency signal and generate a relative phase, and includes:
delaying both the intermediate frequency sampling signal and the local carrier signal by one symbol period;
mixing and low-pass filtering the intermediate frequency sampling signal delayed by one symbol period by using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period;
determining a phase in the zero intermediate frequency signal delayed by one symbol period as the relative phase.
With reference to the second aspect, in a possible implementation manner, the signal zero-phase difference calculation module is configured to determine an I-path zero-phase difference signal and a Q-path zero-phase difference signal, and includes: and performing cross product operation on the zero intermediate frequency signal.
With reference to the second aspect, in one possible implementation manner, the signal sampling module is configured to determine an I-path sampled signal and a Q-path sampled signal, and includes: and performing 100-time extraction on the I path of zero phase difference signal and the Q path of zero phase difference signal.
With reference to the second aspect, in a possible implementation manner, the mean value determining module is configured to calculate a mean value of the I-path correlation values, where the mean value determining module is configured to determine whether the synchronization sequence signal is aligned with the I-path sampling signal, and when a determination result is that the synchronization sequence signal is aligned with the I-path sampling signal, sum and take a mean value according to the I-path correlation values, and determine the mean value.
In a third aspect, an embodiment of the present invention provides a server for improving demodulation accuracy of a D8PSK signal, including a memory and a processor;
the memory is to store computer-executable instructions;
the processor is configured to execute the computer-executable instructions to implement the method of the first aspect.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where executable instructions are stored, and when the executable instructions are executed by a computer, the computer implements the method according to the first aspect.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:
the embodiment of the invention adopts a method for improving the demodulation precision of a D8PSK signal, and the method comprises the steps of obtaining an intermediate frequency sampling signal; performing down-conversion processing on the intermediate-frequency sampling signal to determine a zero intermediate-frequency signal; eliminating inherent phase difference in the zero intermediate frequency signal, generating a relative phase, and determining an I path of zero phase difference signal and a Q path of zero phase difference signal; sampling the I path of zero phase difference signal and the Q path of zero phase difference signal, and determining an I path of sampling signal and a Q path of sampling signal; acquiring a plurality of sine and cosine values corresponding to the synchronous sequence signal, respectively carrying out correlation calculation on the sine and cosine values and the I path sampling signal and the Q path sampling signal, and determining a plurality of I path correlation values and a plurality of Q path correlation values; calculating the average value of the multiple I-path correlation values, and determining the peak value time of the average value as the synchronization time; compensating I path correlation values and Q path correlation value data to I path zero phase difference signals and Q path zero phase difference signals according to the phase of the synchronous moment, and determining I path compensation signals and Q path compensation signals; performing arc tangent calculation on the I path of compensation signal and the Q path of compensation signal to determine an angle value; the angle value is sampled, and binary code elements are output to the angle value, so that the problems of slow frequency offset estimation time, long synchronization time and large algorithm resource consumption in the prior art are effectively solved, the algorithm resource is saved, and the angle resolving precision is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments of the present invention or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart illustrating steps of a method for improving demodulation accuracy of a D8PSK signal according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of an apparatus for improving demodulation accuracy of a D8PSK signal according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a server for improving demodulation accuracy of a D8PSK signal according to an embodiment of the present application.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A Local Area Augmentation System (LAAS) is an augmentation system that can provide high-precision positioning of the global positioning system in local areas. The basic working principle of the LAAS is that a reference station is arranged at a known place with accurate position, error enhancement information (including ranging information and differential correction information) is calculated for GPS constellation signals in a receiving range of the reference station and is sent out in a broadcasting mode, after an approaching aircraft receives a very high frequency broadcasting signal through a VDB receiver, the ranging and differential calculation result calibration is realized in the receiver by using the signal, and therefore the positioning performance of an airborne GPS receiver is improved.
The VDB is a burst signal modulated based on 8-ary Differential Phase shift keying (D8 PSK). The data transmission rate is 10500symbol/s, binary data are firstly combined into characters during coding, each character consists of 3 continuous binary data, and then the characters are converted into D8PSK modulation signals.
At present, in consideration of carrier frequency offset existing in a receiving process, a coherent demodulation method is usually adopted in engineering to demodulate a VDB signal, a local carrier in an ideal state is locally generated, and an input intermediate frequency signal is multiplied by the local carrier to obtain two paths of signals I and Q; low-pass filtering is carried out on the I, Q paths of signals respectively to complete digital down-conversion, baseband signals with frequency offset are generated, cross product and dot product calculation are carried out on the two paths of baseband signals to eliminate the phase difference of front and rear code elements, and a relative phase is generated; then, carrying out autocorrelation calculation on the I \ Q two paths and local 48-bit synchronous codes, capturing a maximum correlation peak value, and carrying out frame synchronization positioning; when the frame synchronization positioning is successful, cross product dot product calculation phase angle is carried out to obtain frequency offset to compensate the local carrier; and finally, sampling judgment is carried out to obtain a binary value. The problems brought by the prior art are that the medium frequency offset estimation time is slow, the synchronization time is long, and the algorithm consumes large resources.
Based on the above problem, an embodiment of the present invention provides a method for improving demodulation accuracy of a D8PSK signal, which includes the following steps as shown in fig. 1.
Step S101, acquiring an intermediate frequency sampling signal.
And step S102, performing down-conversion processing on the intermediate frequency sampling signal, and determining a zero intermediate frequency signal.
And step S103, eliminating the inherent phase difference in the zero intermediate frequency signal, generating a relative phase, and determining an I path of zero phase difference signal and a Q path of zero phase difference signal.
And step S104, sampling the I path of zero-phase difference signal and the Q path of zero-phase difference signal, and determining the I path of sampling signal and the Q path of sampling signal.
Step S105, obtaining a plurality of sine and cosine values corresponding to the synchronous sequence signal, and performing correlation calculation on the sine and cosine values and the I-path sampling signal and the Q-path sampling signal, respectively, to determine a plurality of I-path correlation values and a plurality of Q-path correlation values.
And step S106, calculating the average value of the I-path correlation values, and determining the peak time of the average value as the synchronization time.
And S107, compensating the I path of correlation values and the Q path of correlation value data to the I path of zero-phase difference signals and the Q path of zero-phase difference signals according to the phase of the synchronous time, and determining I path of compensation signals and Q path of compensation signals.
And step S108, performing arc tangent calculation on the I path of compensation signal and the Q path of compensation signal, and determining an angle value.
Step S109, samples the angle value, and outputs the angle value as a binary symbol.
The invention provides a method for improving the demodulation precision of a D8PSK signal, which can complete frame synchronization, bit synchronization and frequency offset estimation within 48 code element time, meets the requirements of a ten-thousandth error rate of large dynamic range change of-90 dB-0 dbm above a signal-to-noise ratio (SNR) 15dB, and solves the problems of slow frequency offset estimation time, long synchronization time, large algorithm resource consumption and the like in the prior art. In the method, in the frame synchronization judgment: in the traditional method, after correlation operation is carried out on two paths of I \ Q and a synchronization sequence, the minimum mean square error is solved, and the time of the minimum value is judged to be the synchronization time. In the invention, the judgment of frame synchronization can be completed only by using the I-path signal.
And the frequency offset compensation algorithm comprises the following steps: in the traditional method, the phase value is obtained by solving the inverse tangent of the two paths of I/Q values at the synchronous moment, and then the deviation is solved and compensated to the local DDS for correcting the frequency. The algorithm has huge calculation amount and influences the precision of the final phase angle. The algorithm directly compensates the value of the synchronous time I \ Q to the signal for angle calculation through trigonometric function operation, reduces the calculation amount and improves the angle calculation precision.
In step S102, the down-conversion processing is performed on the intermediate frequency sampled signal, and includes: and mixing the local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter.
In this application, the intermediate frequency sampling signal is denoted as:
wherein f is1Is VDThe frequency of the B signal is then used,
is the initial phase.
In step S103, eliminating the inherent phase difference in the zero intermediate frequency signal to generate a relative phase includes:
the intermediate frequency sample signal and the local carrier signal are each delayed by one symbol period. The intermediate frequency sampling signal delayed by one symbol period is mixed and low-pass filtered using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period. The phase in the zero intermediate frequency signal delayed by one symbol period is determined as the relative phase.
The input signal delayed by one symbol period is:
wherein, T is the code element period,
is the initial phase.
The local carrier signals are:
after frequency mixing and low-pass filtering:
in step S103, determining the I path of zero-phase difference signal and the Q path of zero-phase difference signal includes: and performing cross product operation on the zero intermediate frequency signal.
For the above-described calculation process, the order,
then it follows:
after the time delay difference, the phase deviation caused by the frequency deviation is a fixed value on each character, namely 2 pi delta fT, so that the influence of the frequency deviation on the synchronization effect can be eliminated.
In step S104, determining the I-path sampling signal and the Q-path sampling signal includes: and performing 100-time extraction on the I path of zero-phase difference signal and the Q path of zero-phase difference signal.
Sampling is carried out by adopting a sampling frequency of 2.1M, subsequent calculation amount is huge, and logic calculation resources are seriously consumed, so that 100 times of extraction is carried out on the I path of zero-phase difference signals and the Q path of zero-phase difference signals. The extraction of 100 times is to extract one sampling point for every 100 sampling points of the I path zero phase difference signal and the Q path zero phase difference signal, and the calculation result can be ensured not to be influenced while the calculation amount is reduced. Of course, the extraction of 100 times is a preferable scheme provided in the embodiment, and the extraction of the speed can be performed according to the requirement.
Combining the calculation to obtain a plurality of sine and cosine values to determine a plurality of I-path correlation values and a plurality of Q-path correlation values; the following is a detailed synchronization algorithm for the demodulated signal.
The local training sequence is:
correlating zero intermediate frequency signals with local training sequences
According to the trigonometric function principle, when the received signal is perfectly synchronized with the local training sequence, i.e. in the above formula,
the I sampled signal peaks.
At this time:
I＝cos(2πΔfT)
Q＝sin(2πΔfT)
in step S106, an average value of the I-path correlation values is calculated, which includes determining whether the synchronization sequence signal is aligned with the I-path sampling signal, and when the determination result is that the synchronization sequence signal is aligned, summing and averaging are performed according to the I-path correlation values to determine the average value.
The burst detection and the frame synchronization can be completed by detecting the I-path correlation peak value, and the optimal sampling point is obtained according to the position of the correlation peak, namely, the bit synchronization is realized while the correlation peak is captured, so that the burst detection, the frame synchronization and the bit synchronization are simultaneously realized through a group of synchronization code elements.
After bit synchronization, due to the existence of frequency offset, frequency offset estimation and correction must be performed, and it can be seen from the above calculation that the phase of I, Q is a constant value, which is 2 pi fT and is closely related to the system frequency offset, so that the frequency offset can be compensated by I, Q two-way values. Namely, it is
Calculating the arc tangent
And completing phase judgment through a constellation diagram.
An embodiment of the present invention provides an apparatus for improving demodulation accuracy of a D8PSK signal, where as shown in fig. 2, the apparatus 200 includes: the signal acquisition module 201: for obtaining intermediate frequency sampling signals. The signal down-conversion module 202: the device is used for carrying out down-conversion processing on the intermediate frequency sampling signal and determining a zero intermediate frequency signal. The signal zero phase difference calculation module 203: the method is used for eliminating the inherent phase difference in the zero intermediate frequency signal, generating the relative phase and determining the I path of zero phase difference signal and the Q path of zero phase difference signal. The signal sampling module 204: the circuit is used for sampling the I path of zero phase difference signals and the Q path of zero phase difference signals and determining the I path of sampling signals and the Q path of sampling signals. Correlation value calculation module 205: the device is used for acquiring a plurality of sine and cosine values corresponding to the synchronous sequence signal, respectively carrying out correlation calculation on the sine and cosine values and the I path sampling signal and the Q path sampling signal, and determining a plurality of I path correlation values and a plurality of Q path correlation values. The mean determination module 206: the device is used for calculating the average value of a plurality of I-path correlation values and determining the peak time of the average value as the synchronization time. The compensation module 207: and the I path of correlation value and the Q path of correlation value data are compensated to the I path of zero phase difference signal and the Q path of zero phase difference signal according to the phase of the synchronous moment, and the I path of compensation signal and the Q path of compensation signal are determined. The calculation module 208: and the device is used for performing arc tangent calculation on the I path compensation signal and the Q path compensation signal and determining an angle value. The output module 209: for sampling the angle value and outputting the angle value as binary code element.
In the device for improving the demodulation precision of the D8PSK signal, different innovation points are as follows: and frame synchronization judgment: in the traditional method, after correlation operation is carried out on two paths of I \ Q and a synchronization sequence, the minimum mean square error is solved, and the time of the minimum value is judged to be the synchronization time. In the invention, the judgment of frame synchronization can be completed only by using the I-path signal.
And the frequency offset compensation algorithm comprises the following steps: in the traditional method, the phase value is obtained by solving the inverse tangent of the two paths of I/Q values at the synchronous moment, and then the deviation is solved and compensated to the local DDS for correcting the frequency. The algorithm has huge calculation amount and influences the precision of the final phase angle. The algorithm directly compensates the value of the synchronous time I \ Q to the signal for angle calculation through trigonometric function operation, reduces the calculation amount and improves the angle calculation precision.
The signal down conversion module 202 is configured to: and mixing the local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter. A525K local carrier signal is preferably adopted in the signal down-conversion module, low-pass filtering is carried out after the local carrier signal is mixed with an input intermediate frequency sampling signal, a Kaiser window function filtering function is preferably adopted, the passband is 0.03MHz, the cutoff frequency is 0.3MHz, and the filter coefficient is quantized by 16 bits. After this step, a zero intermediate frequency signal can be generated.
The signal zero phase difference calculating module 203 is configured to eliminate an inherent phase difference in the zero intermediate frequency signal and generate a relative phase, and includes: delaying both the intermediate frequency sampling signal and the local carrier signal by one symbol period; mixing and low-pass filtering the intermediate frequency sampling signal delayed by one code element period by using a local carrier signal delayed by one code element period to obtain a zero intermediate frequency signal delayed by one code element period; the phase in the zero intermediate frequency signal delayed by one symbol period is determined as the relative phase.
The signal zero-phase difference calculating module 203 is configured to determine an I-path zero-phase difference signal and a Q-path zero-phase difference signal, and includes: and performing cross product operation on the zero intermediate frequency signal.
The signal sampling module 204 is used for determining the I-path sampling signal and the Q-path sampling signal, and includes: and performing 100-time extraction on the I path of zero-phase difference signal and the Q path of zero-phase difference signal.
The average determining module 206 is configured to calculate an average of the I-path correlation values, including determining whether the synchronization sequence signal is aligned with the I-path sampling signal, and when the determination result is that the synchronization sequence signal is aligned with the I-path sampling signal, summing and averaging according to the I-path correlation values to determine the average.
The embodiment of the invention provides a server for improving demodulation precision of a D8PSK signal, which comprises a memory 301 and a processor 302 as shown in FIG. 3; the memory 301 is used to store computer executable instructions; the processor 302 is configured to perform a method for improving demodulation accuracy of a D8PSK signal.
The embodiment of the invention provides a computer-readable storage medium, wherein executable instructions are stored in the computer-readable storage medium, and the computer executes and executes a method for improving the demodulation precision of a D8PSK signal.
The storage medium includes, but is not limited to, a Random Access Memory (RAM), a Read-Only Memory (ROM), a Cache, a Hard Disk (Hard Disk Drive), or a Memory Card (HDD). The memory may be used to store computer program instructions.
Although the present application provides method steps as described in an embodiment or flowchart, additional or fewer steps may be included based on conventional or non-inventive efforts. The sequence of steps recited in this embodiment is only one of many steps performed and does not represent a unique order of execution. When an actual apparatus or client product executes, it can execute sequentially or in parallel (e.g., in the context of parallel processors or multi-threaded processing) according to the methods shown in this embodiment or the figures.
The apparatuses or modules illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. The functionality of the modules may be implemented in the same one or more software and/or hardware implementations of the present application. Of course, a module that implements a certain function may be implemented by a plurality of sub-modules or sub-units in combination.
The methods, apparatus or modules described herein may be implemented in a computer readable program code means for a controller in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, Application Specific Integrated Circuits (ASICs), programmable logic controllers and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic for the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may therefore be considered as a hardware component, and the means included therein for performing the various functions may also be considered as a structure within the hardware component. Or even means for performing the functions may be regarded as being both a software module for performing the method and a structure within a hardware component.
Some of the modules in the apparatus described herein may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, classes, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
From the above description of the embodiments, it is clear to those skilled in the art that the present application can be implemented by software plus necessary hardware. Based on such understanding, the technical solutions of the present application may be embodied in the form of software products or in the implementation process of data migration, which essentially or partially contributes to the prior art. The computer software product may be stored in a storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to perform the methods described in the various embodiments or portions of the embodiments of the present application.
The embodiments in the present specification are described in a progressive manner, and the same or similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. All or portions of the present application are operational with numerous general purpose or special purpose computing system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet-type devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure.
Claims (9)
1. A method for improving demodulation accuracy of a D8PSK signal, comprising:
acquiring an intermediate frequency sampling signal;
performing down-conversion processing on the intermediate frequency sampling signal to determine a zero intermediate frequency signal;
eliminating inherent phase difference in the zero intermediate frequency signal, generating a relative phase, and determining an I path of zero phase difference signal and a Q path of zero phase difference signal;
sampling the I path of zero phase difference signal and the Q path of zero phase difference signal, and determining an I path of sampling signal and a Q path of sampling signal;
acquiring a plurality of sine and cosine values corresponding to a synchronous sequence signal, respectively carrying out correlation calculation on the sine and cosine values and the I path sampling signal and the Q path sampling signal, and determining a plurality of I path correlation values and a plurality of Q path correlation values;
calculating an average value of the I-path correlation values, and determining the peak time of the average value as the synchronization time;
compensating the I path correlation value and the Q path correlation value data to the I path zero phase difference signal and the Q path zero phase difference signal according to the phase of the synchronous moment, and determining an I path compensation signal and a Q path compensation signal;
performing arc tangent calculation on the I path compensation signal and the Q path compensation signal to determine an angle value;
and sampling the angle value, and outputting a binary code element to the angle value.
2. The method of claim 1, wherein the down-converting the intermediate frequency sampled signal comprises: and mixing the local carrier signal with the intermediate frequency sampling signal, and inputting the mixed signal into a low-pass filter.
3. The method of claim 1, wherein said removing the inherent phase difference in the zero intermediate frequency signal to produce a relative phase comprises:
delaying both the intermediate frequency sampling signal and the local carrier signal by one symbol period;
mixing and low-pass filtering the intermediate frequency sampling signal delayed by one symbol period by using the local carrier signal delayed by one symbol period to obtain a zero intermediate frequency signal delayed by one symbol period;
determining a phase in the zero intermediate frequency signal delayed by one symbol period as the relative phase.
4. The method of claim 3, wherein determining the I path zero-difference signal and the Q path zero-difference signal comprises: and performing cross product dot product operation on the zero intermediate frequency signal.
5. The method of claim 1, wherein determining the I sampled signal and the Q sampled signal comprises: and performing 100-time extraction on the I path of zero phase difference signal and the Q path of zero phase difference signal.
6. The method of claim 1, wherein the calculating the average value of the I-way correlation values comprises determining whether the synchronization sequence signal is aligned with the I-way sampling signal, and when the determination result is that the synchronization sequence signal is aligned, summing and averaging according to the I-way correlation values to determine the average value.
7. An apparatus for improving demodulation accuracy of a D8PSK signal, comprising:
the signal acquisition module is used for acquiring an intermediate frequency sampling signal;
the signal down-conversion module is used for performing down-conversion processing on the intermediate frequency sampling signal and determining a zero intermediate frequency signal;
the signal zero phase difference calculation module is used for eliminating inherent phase difference in the zero intermediate frequency signal, generating a relative phase, and determining an I path of zero phase difference signal and a Q path of zero phase difference signal;
the signal sampling module is used for sampling the I path of zero phase difference signal and the Q path of zero phase difference signal and determining an I path of sampling signal and a Q path of sampling signal;
the correlation value calculation module is used for acquiring a plurality of sine and cosine values corresponding to the synchronous sequence signals, respectively performing correlation calculation on the sine and cosine values and the I-path sampling signals and the Q-path sampling signals, and determining a plurality of I-path correlation values and a plurality of Q-path correlation values;
the average value determining module is used for calculating the average value of the I-path correlation values and determining the peak value time of the average value as the synchronization time;
the compensation module is used for compensating the I-path correlation value and the Q-path correlation value data to the I-path zero-phase difference signal and the Q-path zero-phase difference signal according to the phase of the synchronous moment, and determining an I-path compensation signal and a Q-path compensation signal;
the calculation module is used for performing arc tangent calculation on the I path of compensation signal and the Q path of compensation signal to determine an angle value;
and the output module is used for sampling the angle value and outputting a binary code element of the angle value.
8. A server for improving the demodulation precision of a D8PSK signal is characterized by comprising a memory and a processor;
the memory is to store computer-executable instructions;
the processor is configured to execute the computer-executable instructions to implement the method of any of claims 1-6.
9. A computer-readable storage medium having stored thereon executable instructions that, when executed by a computer, are capable of implementing the method of any one of claims 1-6.
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