CN113722264A - Communication method between single-chip microcomputers - Google Patents
Communication method between single-chip microcomputers Download PDFInfo
- Publication number
- CN113722264A CN113722264A CN202110976441.5A CN202110976441A CN113722264A CN 113722264 A CN113722264 A CN 113722264A CN 202110976441 A CN202110976441 A CN 202110976441A CN 113722264 A CN113722264 A CN 113722264A
- Authority
- CN
- China
- Prior art keywords
- communication line
- level
- voltage
- communication
- chip microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004891 communication Methods 0.000 title claims abstract description 251
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 229910002059 quaternary alloy Inorganic materials 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Small-Scale Networks (AREA)
- Bidirectional Digital Transmission (AREA)
Abstract
The invention provides a communication method between single-chip microcomputers, which comprises the following steps: receiving a plurality of first levels transmitted by the first singlechip according to the first communication line and a plurality of second levels transmitted by the second communication line; the first level and the second level are both high level or low level, the high level is represented by a binary value 1, and the low level is represented by a binary value 0; correspondingly combining the plurality of first levels and the plurality of second levels to form a plurality of quadruple values; and combining the four-input numbers of the formed plurality of the first level or the second level according to the transmission sequence of the first level or the second level to form data information and finish communication. With the transmission of effective improvement data, and solve all need adopt the limitation that UART serial port communication and IIC bus just can communicate between the current singlechip, increase the mode of communication between the singlechip, the user of being convenient for uses.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of communication, in particular to a communication method between single-chip microcomputers.
[ background of the invention ]
As is well known, the existing single chip microcomputer and the single chip microcomputer generally adopt two-wire communication, such as a Universal Asynchronous Receiver Transmitter (UART) and an integrated circuit bus (IIC). The UART serial communication is characterized in that a transmitting line and a receiving line are directly separated, one line is a transmitting line, the other line is a receiving line, the two lines are high-speed and do not influence each other, the two lines travel on respective paths, however, the UART serial communication is adopted, two singlechips have to define baud rates in advance to realize normal communication, namely, the communication between the two singlechips needs to define clock pulses to be used for data segmentation. The IIC bus communication uses one line as a data clock line and the other line as a data line, and the data line is used for receiving and transmitting data.
Both communications are implemented in binary, where the symbols are 0 and 1, and the 0 and 1 are distinguished by the clock pulse. Furthermore, when transferring one byte, the UART serial communication and the IIC bus communication both require 8 shifts. Because a bit of 0 or 1 is sent, two time pulses, namely 8 displacements of UART serial port communication and IIC bus communication, are needed, and corresponding 16 voltage pulses are needed. This communication mode, it is inefficient, and need the singlechip between two communications all to have UART serial ports or IIC bus just can realize the communication between the two, and then let the communication between the singlechip have the limitation.
Accordingly, the prior art is in need of improvement and development.
[ summary of the invention ]
The invention aims to provide a communication method between single-chip microcomputers, which is used for solving the problem of limitation that communication between the existing single-chip microcomputers needs UART serial ports or IIC buses to be communicated and the problem of low communication efficiency between the existing single-chip microcomputers.
The technical scheme of the invention is as follows:
in one aspect, the invention provides a communication method between singlechips, comprising the following steps:
receiving a plurality of first levels transmitted by the first singlechip according to the first communication line and a plurality of second levels transmitted by the second communication line; the first level and the second level are both high levels or low levels, the high levels are represented by binary values of 1, and the low levels are represented by binary values of 0;
correspondingly combining the plurality of first levels and the plurality of second levels to form a plurality of quadruple values;
and combining the four-input numbers of the formed plurality of the first level or the second level according to the transmission sequence of the first level or the second level to form data information and finish communication.
Further, in the receiving of the plurality of first levels transmitted by the first singlechip from the first communication line and the plurality of second levels transmitted by the second communication line,
if the first level transmitted by the first communication line is consistent with the first level transmitted last time and the second level transmitted by the second communication line is consistent with the second level transmitted last time, detecting whether the voltage on the first communication line is a first preset voltage or detecting whether the voltage on the second communication line is a second preset voltage;
and if the voltage on the first communication line is the first preset voltage or the voltage on the second communication line is not the second preset voltage, distinguishing the first level from the second level in two times.
Further, before receiving a plurality of first levels transmitted by the first single chip microcomputer from the first communication line and a plurality of second levels transmitted by the second communication line, the method further comprises the following steps:
the first single chip microcomputer divides the communication data in the quaternary form to be transmitted into a first level and a second level.
Further, before the first single chip microcomputer splits the communication data in the quaternary form to be transmitted into a first level and a second level, the method further includes:
collecting a first voltage of a first communication line and a second voltage on a second communication line;
judging whether the first voltage is a third preset voltage or not, and judging whether the second voltage is a fourth preset voltage or not;
if the first voltage is not the third preset voltage or the second voltage is not the fourth preset voltage, the first singlechip U1 is not communicated with the first voltage, or data is sent to the first singlechip.
Further, after the communication is completed, the voltage of the first communication line and the voltage on the second communication line are collected.
Further, the quartic values include 0, 1, 2, and 3; if the first level and the second level sent by the first communication line and the second communication line are both 0, the first level and the second level are combined to form 0 in the quadruple numerical value; if the first level and the second level sent by the first communication line and the second communication line are 0 and 1 respectively, the first level and the second level are combined to form 1 in the quadruple numerical value; if the first level and the second level sent by the first communication line and the second communication line are 1 and 0 respectively, the first level and the second level are combined to form 2 in the quadruple numerical value; the first level and the second level are 1 and 1, respectively, and then combine to form 3 of the quadruple values.
On the other hand, the invention also provides a communication device for executing the communication method between the single-chip microcomputers.
In one aspect, the invention further provides a system for communication between single-chip microcomputers, which comprises a first communication line, a second communication line, a first single-chip microcomputer and a second single-chip microcomputer, wherein the first single-chip microcomputer and the second single-chip microcomputer are used for executing the communication method;
one IO pin of the first single chip microcomputer is connected with one IO pin of the second single chip microcomputer through a first communication line, and the other IO pin of the first single chip microcomputer is connected with the other IO pin of the second single chip microcomputer through a second communication line; the first single chip microcomputer is further connected with a first communication line and a second communication line respectively and used for detecting the voltage of the first communication line and the voltage of the second communication line respectively, and the second single chip microcomputer is further connected with the first communication line and the second communication line respectively and used for detecting the voltage of the first communication line and the voltage of the second communication line respectively.
Furthermore, the communication system further comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a power supply end, the power supply end is grounded after sequentially passing through the first resistor and the second resistor, the power supply end is grounded after sequentially passing through the third resistor and the fourth resistor, the first communication line is respectively connected with the output end of the first resistor and the input end of the second resistor, and the second communication line is respectively connected with the output end of the third resistor and the input end of the fourth resistor.
Further, the first single chip microcomputer is respectively and electrically connected with the first communication line and the second communication line through two AD pins, and the second single chip microcomputer is respectively and electrically connected with the first communication line and the second communication line through two AD pins.
The invention has the beneficial effects that: compared with the prior art, the four-input system data transmission method has the advantages that the four-input system data are split into two binary data values, the two binary data values are respectively transmitted by the two communication lines, namely one byte is transmitted, only 4 voltage pulses are needed, the data transmission is effectively improved, and the transmission efficiency can be improved by 2-4 times. And the limitation that communication can be realized only by adopting UART serial port communication and IIC bus between the existing single-chip microcomputers can be solved, the communication condition between the single-chip microcomputers is reduced, and the use by users is convenient.
[ description of the drawings ]
FIG. 1 is a schematic diagram of a system for communication between singlechips according to the present invention.
FIG. 2 is a flow chart of the communication method between the single-chip microcomputers according to the invention.
[ detailed description ] embodiments
The invention is further described with reference to the following figures and embodiments.
Referring to fig. 1, a system for communication between singlechips in an embodiment of the present invention is shown.
The system for communication among the single-chip microcomputers comprises a first communication line 1, a second communication line 2, a first single-chip microcomputer U1 and a second single-chip microcomputer U2. An IO pin IO11 of the first single-chip microcomputer U1 is connected with an IO pin IO21 of the second single-chip microcomputer U2 through a first communication line 1, and another IO pin IO12 of the first single-chip microcomputer U1 is connected with another IO pin IO22 of the second single-chip microcomputer U2 through a second communication line 2. The first single chip microcomputer U1 is further connected with a first communication line 1 and a second communication line 2 respectively for detecting voltages of the first communication line 1 and the second communication line 2 respectively, and the second single chip microcomputer U2 is further connected with the first communication line 1 and the second communication line 2 respectively for detecting voltages of the first communication line 1 and the second communication line 2 respectively.
Because the data IO port on the single chip microcomputer can only identify the logic high level 1 and the logic low level 0, the data transmission between the single chip microcomputers can be realized by utilizing the IO port, namely, the communication between the two single chip microcomputers is realized.
Based on the communication system between the single-chip microcomputers, the communication method between the single-chip microcomputers of the embodiment of the invention can be obtained.
Referring to fig. 2, now, the first single chip microcomputer U1 sends data to the second single chip microcomputer U2, wherein the second single chip microcomputer U2 is used as an executed operation object to describe a communication method between the single chip microcomputers, which specifically includes the following steps:
s10, receiving a plurality of first levels transmitted by the first singlechip U1 according to the first communication line 1 and a plurality of second levels transmitted by the second communication line 2.
Namely, the first singlechip U1 sends a plurality of transmitted first levels to the second singlechip U2 through the first communication line 1, and sends a plurality of transmitted second levels to the second singlechip U2 through the second communication line 2. The first level and the second level are both high level or low level, that is, the second single chip microcomputer U2 can obtain two pulse signals sent from the first single chip microcomputer U1 through the first communication line 1 and the second communication line 2, and further can obtain high level 1 or low level 0 continuously sent from the first single chip microcomputer U1, and the two groups of pulse signals have the same period and the same cycle number, but the levels may not be the same.
And S20, correspondingly combining the first levels and the second levels to form a plurality of quadruple numerical values.
The second single chip microcomputer U2 combines the high level 1 or the low level 0 respectively acquired from the first communication line 1 and the second communication line 2, wherein the periods of the combined first level and the second level are consistent and are correspondingly combined. If the first level and the second level sent by the first communication line 1 and the second communication line 2 are both 0, the first level and the second level are correspondingly combined to form 0 in the quadruple numerical value; if the first level and the second level sent by the first communication line 1 and the second communication line 2 are respectively 0 and 1, the first level and the second level are correspondingly combined to form 1 in the quadruple numerical value; if the first level and the second level sent by the first communication line 1 and the second communication line 2 are respectively 1 and 0, the first level and the second level are correspondingly combined to form 2 in the quadruple numerical value; if the first level and the second level transmitted by the first communication line 1 and the second communication line 2 are both 1, 3 of the quadruple values are formed by combination, that is, the existing quadruple values 0, 1, 2 and 3 are formed.
And S30, combining the four-input numbers according to the transmission sequence of the first level or the second level to form data information and finish communication.
For the convenience of understanding the above technical solutions, the description is now made. For example, the first single chip microcomputer U1 transmits a decimal 238 to the second single chip microcomputer U2 through the first communication line 1 and the second communication line 2, if the quaternary system is 3232, the first single chip microcomputer U1 splits the quaternary system 3 into a first level and a second level in advance, that is, two binary 1 s; the quaternary 2 is split into a first level and a second level, i.e. 0 and 1 being binary, and the split binary values are transferred via a first communication line 1 and a second communication line 2, as shown in the following table:
| logic level transferred by first communication line | 1 | 1 | 1 | 1 |
| Logic level conveyed by the second communication line | 1 | 0 | 1 | 0 |
| Four-step numerical value | 3 | 2 | 3 | 2 |
And sent to a second singlechip U2 according to the order of the quaternary 3232. The second single chip microcomputer U2 then sequentially executes steps S10, S20, and S30 to combine the first level and the second level sent by the first communication line 1 and the second communication line 2 to form a quaternary 3232, so as to implement data transmission and complete communication.
That is, before the second single chip microcomputer U2 executes the step S10, the communication method further includes the steps of: the first single chip microcomputer U1 splits the quaternary form communication data to be transmitted to the second single chip microcomputer U2 into a first level and a second level, and the first level and the second level are transmitted through a first communication line 1 and a second communication line 2 respectively, so that the quaternary form communication between the single chip microcomputers is realized.
In one embodiment, in order to prevent the first singlechip U1 from sequentially transmitting the same quadruple numbers twice to the second singlechip U2, i.e. the two first levels transmitted one after the other by means of the first communication line 1 and the two second levels transmitted one after the other by means of the second communication line 2 coincide, that is, the successively transmitted levels are identical and cannot be distinguished by the second single chip microcomputer U2, so that in order to inform the second single chip microcomputer U2 that two successively identical quad values are transmitted, which is convenient for the second single chip microcomputer U2 to distinguish, in step S20, when the first level transmitted by the first communication line 1 coincides with the first level of the previous transmission and the second level transmitted by the second communication line 2 coincides with the second level of the previous transmission, the second single chip microcomputer U2 detects that the voltage on the first communication line 1 is the first preset voltage, and detects that the voltage on the second communication line 2 is the second preset voltage. If the voltage on the first communication line is the first preset voltage or the voltage on the second communication line is the second preset voltage, the division of the first level and the second level in the two times before and after is realized, namely, the division of the first level and the second level in the two times before and after is realized.
Because the high-level voltage transmitted by the first single chip microcomputer U1 is VCC, and the low-level voltage is 0V, in order to generate a split signal, the voltages transmitted by the first communication line 1 or the second communication line 2 can be changed, and the voltages on the first communication line 1 and the second communication line 2 can be detected in real time by using the second single chip microcomputer U2, that is, when the second single chip microcomputer U2 detects that the voltage on the first communication line 1 is the first preset voltage and the voltage on the second communication line 2 is the second preset voltage, it can be determined that the first single chip microcomputer U1 transmits two consistent quadruple numerical values. For example, when the first single chip microcomputer U1 needs to send a decimal 255, that is, the quaternary system is 3333, and further, division needs to be performed once between every two adjacent quaternary values, as shown in the following table:
therefore, according to the communication method between the single-chip microcomputers, the four-way numerical value is divided into two binary numerical values, and the two binary numerical values are transmitted by using two communication lines, namely one byte is transmitted, so that only four pulses are needed under the state that data division is not needed, such as 3232, and time pulse assistance is not needed. In the state that data division is required once for each pulse transmission, for example, 3333, only 4 pulses are required, but the power source terminal + VCC is used to cooperate to realize data division, which is equivalent to 8 voltage pulses. But for the communication between the existing single-chip microcomputers, the UART serial port communication and the IIC bus communication both need 16 voltage pulses, so that the data transmission can be effectively improved, and the transmission efficiency is improved by 2 to 4 times. The communication method between the single-chip microcomputers can solve the limitation that the existing single-chip microcomputers can communicate only by adopting UART serial port communication and IIC buses, so that the communication mode between the single-chip microcomputers is increased, and the communication method is convenient for users to use.
In order to generate voltages different from VCC and 0V on the first communication line 1 or the second communication line 2, the system for communication between single-chip microcomputers of the present invention further comprises: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a power supply terminal + VCC. The power supply end + VCC is grounded after sequentially passing through the first resistor R1 and the second resistor R2, the power supply end + VCC is grounded after sequentially passing through the third resistor R3 and the fourth resistor R4, the first communication line 1 is respectively connected with the output end of the first resistor R1 and the input end of the second resistor R2, and the second communication line 2 is respectively connected with the output end of the third resistor R3 and the input end of the fourth resistor R4.
When the division signal needs to be generated, the power supply end + VCC is electrified, namely the first communication line 1 or the second communication line 2 is electrified, the voltage required by the first communication line 1 or the second communication line 2 can be customized by utilizing the voltage division of the second resistor R2 and the fourth resistor R4, and the voltage on the first communication line 1 or the second communication line 2 is detected in real time by combining the second single chip microcomputer U2, so that the situation that the quadruple numerical values transmitted by the second single chip microcomputer U2 in sequence are consistent can be informed.
It should be noted that the voltage of the first preset voltage may be set to be different from VCC and 0V, and the second preset voltage keeps the voltage output by the first single chip microcomputer U1 consistent (high level VCC or low level 0V). Or the voltage of the second preset voltage is different from VCC and 0V, and the first preset voltage keeps the voltage output by the first single chip microcomputer U1 consistent (high level VCC or low level 0V), and the like, which is not limited herein.
In order to simplify the communication system between the single-chip microcomputers, the first single-chip microcomputer U1 is directly and electrically connected with the first communication line 1 and the second communication line 2 through two AD pins, and the second single-chip microcomputer U2 is directly and electrically connected with the first communication line 1 and the second communication line 2 through two AD pins, so that the voltages on the first communication line 1 and the second communication line 2 can be detected.
In one embodiment of the communication method between the singlechips, for the confirmation of the communication direction, whether the first singlechip U1 transmits data to the second singlechip U2 or whether the second singlechip U2 transmits data to the first singlechip U1 is confirmed. Before executing step S10, the method further includes the steps of:
s01, collecting a first voltage of the first communication line 1 and a second voltage on the second communication line 2;
s02, judging whether the first voltage is a third preset voltage or not, and judging whether the second voltage is a fourth preset voltage or not;
s03, if the first voltage is not the third preset voltage or the second voltage is not the fourth preset voltage, the first single chip microcomputer U1 is not communicated with the first single chip microcomputer U1, and the voltage is continuously detected; or send data to the first singlechip.
When the first single-chip microcomputer U1 and the second single-chip microcomputer U2 do not communicate with each other, that is, no logic level is output by IO pins on the first single-chip microcomputer U1 and the second single-chip microcomputer U2, a first preset voltage or a second preset voltage different from the logic level can be supplied to the first communication line 1 and the second communication line 2 by using the power supply terminal + VCC through an artificial switch or software program control, that is, both the third preset voltage and the fourth preset voltage are different from the logic level.
Therefore, the first single-chip microcomputer U1 and the second single-chip microcomputer U2 judge that the two do not communicate at the moment according to the voltages on the first communication line 1 and the second communication line 2 detected in real time. If the first preset voltage and the second preset voltage are respectively 0V and a voltage different from a logic level when the voltages on the first communication line 1 and the second communication line 2 are applied, namely the first singlechip U1 sends data to the second singlechip U2; when the first preset voltage or the second preset voltage is a voltage different from the logic level and 0V, respectively, the second single chip microcomputer U2 sends data to the first single chip microcomputer, and the first preset voltage and the second preset voltage can be defined according to the requirement, and are not limited herein.
In addition, in an embodiment, the communication method between the single-chip microcomputers in the embodiment of the present invention further includes the steps of:
after the communication is finished, the voltage of the first communication line 1 is detected to be a third preset voltage, and the voltage on the second communication line 2 is detected to be a fourth preset voltage, and then data are transmitted to the first single chip microcomputer U1 through the first communication line 1 and the second communication line 2.
After the first single chip microcomputer U1 transmits data to the second single chip microcomputer U2, and after communication is completed, no communication exists between the first single chip microcomputer U1 and the second single chip microcomputer U2, according to the mode, through manual switching or software program control and the like, the power supply end + VCC can provide a voltage for the first communication line 1 and the second communication line 2, namely a third preset voltage and a fourth preset voltage, namely the third preset voltage and the fourth preset voltage are respectively 0V and a voltage different from a logic level, namely the first single chip microcomputer U1 transmits data to the second single chip microcomputer U2; when the third preset voltage or the sixth preset voltage is a voltage different from the logic level and 0V, respectively, the second mcu U2 sends data to the first mcu U2, which is not limited herein.
On the other hand, the embodiment of the invention also provides a communication device for executing the communication method between the single-chip microcomputers, and the communication device is the second single-chip microcomputer U2. In addition, it should be noted that the communication device may also be a first single chip microcomputer U1, and the above-mentioned "first" and "second" are only used for distinguishing, so as to clearly illustrate the technical solution of the present embodiment.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A communication method between single-chip microcomputers is characterized by comprising the following steps:
receiving a plurality of first levels transmitted by the first singlechip according to the first communication line and a plurality of second levels transmitted by the second communication line; the first level and the second level are both high levels or low levels, the high levels are represented by binary values of 1, and the low levels are represented by binary values of 0;
correspondingly combining the plurality of first levels and the plurality of second levels to form a plurality of quadruple values;
and combining the four-input numbers of the formed plurality of the first level or the second level according to the transmission sequence of the first level or the second level to form data information and finish communication.
2. The method of claim 1, wherein, in receiving a plurality of first levels transmitted from a first communication line by a first single chip microcomputer and a plurality of second levels transmitted from a second communication line,
if the first level transmitted by the first communication line is consistent with the first level transmitted last time and the second level transmitted by the second communication line is consistent with the second level transmitted last time, detecting whether the voltage on the first communication line is a first preset voltage or detecting whether the voltage on the second communication line is a second preset voltage;
and if the voltage on the first communication line is the first preset voltage or the voltage on the second communication line is not the second preset voltage, distinguishing the first level from the second level in two times.
3. The method according to claim 2, wherein before receiving the first levels transmitted from the first communication line by the first single chip microcomputer and the second levels transmitted from the second communication line, the method further comprises the steps of:
the first single chip microcomputer divides the communication data in the quaternary form to be transmitted into a first level and a second level.
4. The method according to claim 3, wherein before the first single chip microcomputer splits the quaternary form communication data to be transmitted into a first level and a second level, the method further comprises:
collecting a first voltage of a first communication line and a second voltage on a second communication line;
judging whether the first voltage is a third preset voltage or not, and judging whether the second voltage is a fourth preset voltage or not;
if the first voltage is not the third preset voltage or the second voltage is not the fourth preset voltage, the first singlechip U1 is not communicated with the first voltage, or data is sent to the first singlechip.
5. The method according to claim 4, wherein after the communication is completed, the voltage of the first communication line and the voltage of the second communication line are collected.
6. The communication method between the single-chip microcomputers according to claim 5, wherein the quad values include 0, 1, 2 and 3; if the first level and the second level sent by the first communication line and the second communication line are both 0, the first level and the second level are combined to form 0 in the quadruple numerical value; if the first level and the second level sent by the first communication line and the second communication line are 0 and 1 respectively, the first level and the second level are combined to form 1 in the quadruple numerical value; if the first level and the second level sent by the first communication line and the second communication line are 1 and 0 respectively, the first level and the second level are combined to form 2 in the quadruple numerical value; and if the first level and the second level sent by the first communication line and the second communication line are both 1, combining to form 3 in the quadruple numerical value.
7. A communication apparatus for performing a communication method between the single-chip microcomputers according to any one of claims 1 to 6.
8. A system for communication between single-chip microcomputers is characterized by comprising a first communication line, a second communication line, a first single-chip microcomputer and a second single-chip microcomputer, wherein the first single-chip microcomputer and the second single-chip microcomputer are used for executing the communication method according to any one of claims 1-6;
one IO pin of the first single chip microcomputer is connected with one IO pin of the second single chip microcomputer through a first communication line, and the other IO pin of the first single chip microcomputer is connected with the other IO pin of the second single chip microcomputer through a second communication line; the first single chip microcomputer is further connected with a first communication line and a second communication line respectively and used for detecting the voltage of the first communication line and the voltage of the second communication line respectively, and the second single chip microcomputer is further connected with the first communication line and the second communication line respectively and used for detecting the voltage of the first communication line and the voltage of the second communication line respectively.
9. The system according to claim 8, wherein the communication system further comprises a first resistor, a second resistor, a third resistor, a fourth resistor, and a power source, the power source is grounded after passing through the first resistor and the second resistor in sequence, the power source is grounded after passing through the third resistor and the fourth resistor in sequence, the first communication line is connected to an output terminal of the first resistor and an input terminal of the second resistor, and the second communication line is connected to an output terminal of the third resistor and an input terminal of the fourth resistor.
10. The system of claim 9, wherein the first one-chip microcomputer is electrically connected to the first communication line and the second communication line through two AD pins, and the second one-chip microcomputer is electrically connected to the first communication line and the second communication line through two AD pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110976441.5A CN113722264B (en) | 2021-08-24 | 2021-08-24 | Communication method between singlechips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110976441.5A CN113722264B (en) | 2021-08-24 | 2021-08-24 | Communication method between singlechips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113722264A true CN113722264A (en) | 2021-11-30 |
| CN113722264B CN113722264B (en) | 2024-03-15 |
Family
ID=78677824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110976441.5A Active CN113722264B (en) | 2021-08-24 | 2021-08-24 | Communication method between singlechips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113722264B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103893868A (en) * | 2012-12-27 | 2014-07-02 | 北京谊安医疗***股份有限公司 | Respirator serial interface extension device |
| WO2016026231A1 (en) * | 2014-08-22 | 2016-02-25 | 江苏省电力公司常州供电公司 | Intelligent polarity detection apparatus and method for four-star type voltage transformer |
| CN108092741A (en) * | 2017-12-12 | 2018-05-29 | 深圳和而泰数据资源与云技术有限公司 | Communication means, terminal and communication equipment based on audio interface |
| CN111404569A (en) * | 2020-03-06 | 2020-07-10 | 深圳盈特创智能科技有限公司 | Efficient single-wire communication method between single-chip microcomputers |
| CN112882976A (en) * | 2020-12-11 | 2021-06-01 | 南京交通职业技术学院 | Method for reducing memory occupied by single chip microcomputer communication |
-
2021
- 2021-08-24 CN CN202110976441.5A patent/CN113722264B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103893868A (en) * | 2012-12-27 | 2014-07-02 | 北京谊安医疗***股份有限公司 | Respirator serial interface extension device |
| WO2016026231A1 (en) * | 2014-08-22 | 2016-02-25 | 江苏省电力公司常州供电公司 | Intelligent polarity detection apparatus and method for four-star type voltage transformer |
| CN108092741A (en) * | 2017-12-12 | 2018-05-29 | 深圳和而泰数据资源与云技术有限公司 | Communication means, terminal and communication equipment based on audio interface |
| CN111404569A (en) * | 2020-03-06 | 2020-07-10 | 深圳盈特创智能科技有限公司 | Efficient single-wire communication method between single-chip microcomputers |
| CN112882976A (en) * | 2020-12-11 | 2021-06-01 | 南京交通职业技术学院 | Method for reducing memory occupied by single chip microcomputer communication |
Non-Patent Citations (2)
| Title |
|---|
| R. SCHOBER等: "Noncoherent receivers for multichip differentially encoded DS-CDMA", 《IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS》 * |
| 孙建鑫: "单片机与PC机的串行通信设计", 《中国科技信息》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113722264B (en) | 2024-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208985152U (en) | Communication system | |
| CN101719112A (en) | Half-duplex automatic receiving-transmitting switching circuit of RS485 | |
| CN202372976U (en) | Switching circuit of time-share multiplexing serial port | |
| CN101310314B (en) | Control/monitor signal transmission system | |
| CN107908584B (en) | Multi-path RS-485 communication network | |
| CN109417521B (en) | Low power multi-level driver | |
| CN201557127U (en) | RS485 half-duplex transmit-receive automatic switch circuit | |
| CN113722264A (en) | Communication method between single-chip microcomputers | |
| US5668716A (en) | Controller for two-way serial transmission and adapter for serial port | |
| CN106105120A (en) | Dispensing device and communication system | |
| CN203057158U (en) | 485 communication circuit and communication system | |
| CN106372025B (en) | Bus type communicating circuit | |
| CN212811729U (en) | On-board communication circuit and device based on CAN communication | |
| CN213367785U (en) | On-board communication circuit and device based on CAN communication | |
| CN210327615U (en) | Communication circuit | |
| CN105488010A (en) | Real-time synchronous interface protocol of backboard | |
| CN101738988B (en) | Communication circuit of programmer for electric vehicle controller | |
| CN217587897U (en) | Polarity conversion device and non-polarity communication system | |
| CN112148321A (en) | Anti-interference upgrading system and method for automobile intelligent electronic equipment microcontroller | |
| CN216527161U (en) | Single-wire serial port communication circuit and electric equipment with same | |
| CN215067812U (en) | CAN network based on CAN controller and gate circuit are constituteed | |
| CN116418363A (en) | UART-based single-wire communication system, while-drilling instrument downhole system and communication method | |
| CN113169919B (en) | On-board communication circuit and on-board communication device | |
| CN212811730U (en) | On-board communication circuit and on-board communication device | |
| CN103973370A (en) | 485 communication circuit and communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |