CN113708761B - Data weighted average algorithm and digital-to-analog conversion circuit - Google Patents
Data weighted average algorithm and digital-to-analog conversion circuit Download PDFInfo
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- CN113708761B CN113708761B CN202111004792.6A CN202111004792A CN113708761B CN 113708761 B CN113708761 B CN 113708761B CN 202111004792 A CN202111004792 A CN 202111004792A CN 113708761 B CN113708761 B CN 113708761B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
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Abstract
The invention provides a data weighted average algorithm and a digital-to-analog conversion circuit, wherein the algorithm comprises the following steps: defining an initial index PA of an odd period and an initial index PB of an even period; if the current period is an odd number period, starting from the position of the initial index PA, according to the input signal number S of the digital-to-analog converter in Selecting the number of corresponding elements, and calculating the index moving step number S step ＝M‑S in The new index of the next odd period is obtained as PA' =pa-S step The method comprises the steps of carrying out a first treatment on the surface of the If the period is even, the index moving step number S is calculated from the position of the initial index PB step ＝M‑S in A new index PB' =pb-S for the next even period is obtained step The method comprises the steps of carrying out a first treatment on the surface of the M is the number of elements in the digital-to-analog converter, and the initial index PA of the odd cycle and the initial index PB of the even cycle are shifted in opposite directions. The invention can eliminate the mismatch error of the passive device, reduce the switching rate of the element, and reduce the intersymbol interference effect while improving the linearity.
Description
Technical Field
The disclosure relates to the technical field of dynamic element matching, and in particular relates to a data weighted average algorithm and a digital-to-analog conversion circuit.
Background
The elements in the analog-digital converter and the digital-analog converter such as resistor, capacitor and current source can generate gradient error and random deviation due to limited process manufacturing precision and layout, the conversion linearity is affected, and the spurious-free dynamic range is reduced.
Dynamic Element Matching (DEM) is a temperature code type selection of unit elements, typically equal-valued resistors, capacitors or current sources, and is typically added up after random selection using temperature code input. The Data Weighted Average (DWA) algorithm is one of the DEM algorithms, and has the advantages of high rotation speed and fast error calibration. The DWA algorithm uses indexes, and like all input codes, the content update is to add new input codes into the input registers, so that the spatial mismatch is converted into the temporal mismatch, so that the harmonic wave in the output frequency spectrum is converted into noise, and the spurious-free dynamic range is improved.
A conventional DWA algorithm element selection diagram is shown in fig. 1, represented for simplicity by 7 elements (EL 1, EL2, …, EL 7), with selected elements represented by shaded boxes and unselected elements represented by blank boxes. Sin represents the input of the DAC, and nseli=1 when element i (1.ltoreq.i.ltoreq.7) is selected; when element i is selected again after 7 elements have been used 1 pass, nseli=2. When DAC inputs (S in ) In the case of 2, 3, 4, 5, 6, 5, 4, and 3 in this order, as shown in fig. 1, the switching rate (toggle rate) is 5, 7, 5, 3, 5, and 7 from the second input of the DAC, respectively, and the total switching rate is 35.
Therefore, the conventional DWA method has a high switching rate, so that inter-symbol interference (ISI) effect is aggravated, and linearity is worsened. In addition, the conventional DWA has only one index, and may generate tones associated with the input signal, reducing SFDR.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a data weighted average algorithm and a digital-to-analog conversion circuit, which can eliminate the mismatch error of passive devices, reduce the switching rate of the devices, and reduce the inter-symbol interference (ISI) effect while improving the linearity.
In order to achieve the above object, the present invention provides the following technical solutions:
a data weighted average algorithm applied to a digital-to-analog converter, comprising:
defining an initial index PA of an odd period and an initial index PB of an even period in elements of the digital-to-analog converter;
judging whether the current period is an odd period or an even period;
if the period is odd, starting from the position of the initial index PA, according to the input signal number S of the digital-to-analog converter in Selecting the number of corresponding elements to determine whether S in +PA>M, if yes, calculating index movement step number S step ＝M-S in And shift the initial index PA position by S step The new index of the next odd period is obtained by the elements and is PA' =PA-S step ；
If the period is even, starting from the position of the initial index PB, according to the input signal number S of the digital-to-analog converter in Selecting the number of corresponding elements to determine whether S in >PB, if yes, calculating the index movement step number S step ＝M-S in And shifts the initial index PB position by S step Elements, get the new index of the next even period to be PB' =PB-S step ；
Wherein M is the number of elements in the digital-to-analog converter, and the initial index PA of the odd cycle and the initial index PB of the even cycle are moved in opposite directions.
Further, if the cycle is an odd cycle, judging whether S is in +PA>M, if not, obtaining the new index of the next odd cycle as PA' =PA+S in 。
Further, if it is an even number period, it is determined whether S in >If not, obtaining a new index of PB' =PB-S of the next even period in 。
Further, the initial index PA of the odd-numbered period is set to 1, and the initial index PB of the even-numbered period is set to M.
The invention also provides a digital-to-analog conversion circuit applying the data weighted average algorithm, comprising,
an index register for receiving an input signal and defining an initial index PA of an odd period and an initial index PB of an even period;
the clock period counter circuit is connected with the index register, and is used for counting the input clock period, judging whether the current period is an odd period or an even period and outputting a result to the index register;
a step number calculating circuit connected with the index register for receiving the input signal and the odd-numbered period initial index PA or even-numbered period initial index PB outputted by the index register, and calculating the index moving step number S of the odd-numbered period initial index PA or even-numbered period initial index PB step ；
And the selection circuit is respectively connected with the clock cycle counter circuit and the step number calculation circuit and is used for controlling elements in the digital-to-analog conversion circuit and selecting corresponding elements as new indexes of the next cycle according to the index moving step number output by the step number calculation circuit.
Further, the method also comprises the steps of,
a comparison circuit connected with the selection circuit for receiving the input signals and then counting the number S of the input signals in And comparing the number M of the elements in the digital-to-analog conversion circuit, and judging whether the initial index PA of the odd period and the initial index PB of the even period need to be moved or not.
Further, the number S of the input signals in After comparing with the number M of elements in the digital-to-analog conversion circuit,
if S in <N, the initial index PA of the odd period and the initial index PB of the even period need to be moved to obtain a new index of the next period;
if S in The index register is inactive, and all elements are selected for the next cycle.
Further, the method also comprises the steps of,
and the odd-even accumulator is connected with the selection circuit at the input end, is connected with the step number calculation circuit at the output end, and is used for accumulating the number of elements used in the odd-numbered period and the even-numbered period, judging whether all the elements are used up once in the period and feeding back to the step number calculation circuit.
Further, if all elements are used up once in the present period, the parity accumulator outputs a signal to the parity accumulatorThe step number calculating circuit sends out trigger signal, and calculates index moving step number S step ＝M-S in If not, S step ＝0。
The data weighted average algorithm and the digital-to-analog conversion circuit can overcome the intersymbol interference effect and reduce the tone by introducing two indexes and moving the indexes after all elements are used up each time, thereby improving the spurious-free dynamic range of the digital-to-analog converter.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a conventional DWA algorithm element selection;
FIG. 2 is a flowchart of an algorithm according to the present invention;
FIG. 3 is a schematic diagram of an algorithm circuit according to the present invention;
FIG. 4 is a schematic diagram of DAC elements according to the present invention;
FIG. 5 is a schematic diagram of the selection of algorithm elements in the present invention.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
As shown in fig. 2, which is a flowchart of an algorithm proposed in this embodiment, a data weighted average algorithm in this embodiment of the present disclosure is applied to a digital-to-analog converter, after a system is powered on, a multi-bit signal is input to a DAC, where the DAC has M elements, an initial index PA set 1 for an odd period and an initial index PB set M for an even period are defined. The counter then determines whether the current period is an odd period. If the period is odd, starting from the position of index PA, the corresponding number of elements is selected according to the input of DAC. First judge whether S in +PA>M, if so, the step number calculation circuit calculates S step ＝M-S in And shift the index initial PA position to the right S step The new index of the next odd period is obtained by the elements and is PA' =PA-S step . If S in +PA.ltoreq.M, obtaining a new index of PA' =PA+S for the next odd cycle in . And finally, selecting the corresponding number of elements from the new index to the right. Also if it is an even period, starting from the position of index PB, selecting the number of corresponding elements according to the DAC input, and first judging whether S is in >PB, if yes, step number calculation circuit calculates S step ＝M-S in And shift the index PB position to the left S step Elements, new index PB' =pb-S step . If Sin is less than or equal to PB, a new index of PB' =PB-S is obtained for the next even period in And finally, selecting the corresponding number of elements from the new index to the left.
As shown in fig. 3, a circuit configuration diagram of the present embodiment to which the above-described data weighted average algorithm is applied is shown in fig. 3. DAC input S in Into the index register 410, an initial index of an odd cycle is defined as PA, and an initial index of an even cycle is defined as PB. The elements of the odd cycles are selected from left to right (or right to left), and the elements of the even cycles are selected in the opposite direction to the odd cycles. The clock CLK is input to a clock cycle counter circuit 420 having a parity cycle determination that counts CLK cycles, separating odd and even cycles to produce PA and PB for the index register 410. Comparison circuit 430 compares S in And M is the total number of DAC elements, if S in =m, index register is inactive, all elements are selected for the next cycle; if S in <M, the index register works normally. S is S in PA and PB as inputs to the step count calculation circuit 440, step number S if all elements are fully used in an odd cycle step ＝M-S in If there are other components not used, S step =0; the method of even period is the same as that of odd period, S step ＝M-S in The use of odd periodic elements requires shifting to the right S whenever an element is used up one pass step (also canTo the left), the direction of movement of the even periods is opposite to that of the odd periods. The selection of the elements is accomplished by selection circuit 450, and parity accumulator 460 provides a trigger signal S each time N elements are all selected once ST Step number calculating circuit starts calculating S step ＝M-S in The method comprises the steps of carrying out a first treatment on the surface of the If there are more elements not used in the selection S ST The step number calculation circuit will S step Set to 0. Element 401 is the M elements (EL 1, EL2, …, ELM) of the DAC, controlled by selection circuit 450.
As shown in fig. 4, a DAC element schematic is shown in fig. 4. Taking x+4 cells as an example, the selected elements are indicated by shaded boxes and the unselected elements are indicated by blank boxes.
As shown in fig. 5, a schematic diagram of algorithm element selection proposed by the present invention is shown in fig. 5. As in the conventional method, 7 elements (EL 1, EL2, …, EL 7) are also represented, wherein selected elements are represented by shaded boxes and unselected elements are represented by blank boxes. The DAC inputs (Sin) are also sequentially 2, 3, 4, 5, 6, 5, 4, 3, as shown in fig. 5, the switching rate (toggle rate) is 5, 3, respectively, from the second DAC input, the total switching rate is 23, and the conventional DWA algorithm of fig. 1 has a total switching rate of 35. The DWA algorithm switching rate of the invention is obviously lower than that of the traditional DWA algorithm, and the influence of ISI effect is reduced.
The invention rotates in opposite directions by introducing two indexes (PA, PB), the direction of rotation being alternating each cycle. An odd period may be defined as a right rotation and an even period as a left rotation, and also if an odd period is defined as a left rotation, an even period is defined as a right rotation. Both directions have separate index pointers and rotate independently. The input-related tones are attenuated. And, in PA index period (assuming PA corresponds to odd period) when all elements are used, the pointer is advanced in the next odd period; after all elements are used in the PB index period (assuming PB corresponds to an even period), the pointer is advanced in the next even period. Thus, when a new component is present, the previously selected component will be restarted for the cycle. Thus reducing the switching rate and the variation is randomized, reducing ISI effects. Therefore, the data weighted average algorithm of the invention reduces the element switching rate so as to reduce the ISI effect, and simultaneously can reduce the tone related to the input, thus being suitable for multi-bit DAC.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the disclosure are intended to be covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (6)
1. A method for weighted averaging of data applied to a digital-to-analog converter, comprising:
defining an initial index PA of an odd period and an initial index PB of an even period in elements of the digital-to-analog converter, wherein the initial index PA of the odd period is set to 1, and the initial index PB of the even period is set to M;
judging whether the current period is an odd period or an even period;
if the period is odd, starting from the position of the initial index PA, according to the input signal number S of the digital-to-analog converter in Selecting the number of corresponding elements to determine whether S in +PA>M, if yes, calculating index movement step number S step ＝M-S in And shift the initial index PA position by S step The new index of the next odd period is obtained by the elements and is PA' =PA-S step Wherein, judge S in +PA>M, if not, obtaining the new index of the next odd cycle as PA' =PA+S in ；
If the period is even, starting from the position of the initial index PB, according to the input signal number S of the digital-to-analog converter in Selecting the number of corresponding elements to determine whether S in >PB, if yes, calculating the index movement step number S step ＝M-S in And shifts the initial index PB position by S step Elements, get the new index of the next even period to be PB' =PB-S step WhereinDetermine whether or not S in >If not, obtaining a new index of PB' =PB-S of the next even period in ；
Wherein M is the number of elements in the digital-to-analog converter, and the initial index PA of the odd cycle and the initial index PB of the even cycle are moved in opposite directions.
2. A digital-to-analog conversion circuit applying the data weighted average method as claimed in claim 1, comprising,
an index register for receiving an input signal and defining an initial index PA of an odd period and an initial index PB of an even period;
the clock period counter circuit is connected with the index register, and is used for counting the input clock period, judging whether the current period is an odd period or an even period and outputting a result to the index register;
a step number calculating circuit connected with the index register for receiving the input signal and the odd-numbered period initial index PA or even-numbered period initial index PB outputted by the index register, and calculating the index moving step number S of the odd-numbered period initial index PA or even-numbered period initial index PB step ；
And the selection circuit is respectively connected with the clock cycle counter circuit and the step number calculation circuit and is used for controlling elements in the digital-to-analog conversion circuit and selecting corresponding elements as new indexes of the next cycle according to the index moving step number output by the step number calculation circuit.
3. The digital to analog conversion circuit of claim 2, further comprising,
a comparison circuit connected with the selection circuit for receiving the input signals and then counting the number S of the input signals in And comparing the number M of the elements in the digital-to-analog conversion circuit, and judging whether the initial index PA of the odd period and the initial index PB of the even period need to be moved or not.
4. According toA digital-to-analog conversion circuit as claimed in claim 3, characterized in that the number of input signals S in After comparing with the number M of elements in the digital-to-analog conversion circuit,
if S in <N, the initial index PA of the odd period and the initial index PB of the even period need to be moved to obtain a new index of the next period;
if S in The index register is inactive, and all elements are selected for the next cycle.
5. The digital to analog conversion circuit of claim 4, further comprising,
and the odd-even accumulator is connected with the selection circuit at the input end, is connected with the step number calculation circuit at the output end, and is used for accumulating the number of elements used in the odd-numbered period and the even-numbered period, judging whether all the elements are used up once in the period and feeding back to the step number calculation circuit.
6. The digital to analog conversion circuit of claim 5, wherein if all elements are used up once in the present period, said parity accumulator sends a trigger signal to said step number calculation circuit, said step number calculation circuit calculates an index move step number S step ＝M-S in If not, S step ＝0。
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| EP2339754A1 (en) * | 2009-12-23 | 2011-06-29 | Nxp B.V. | A converter |
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| CN103401558A (en) * | 2013-08-26 | 2013-11-20 | 华为技术有限公司 | Method and device for processing DWA (data-weighted averaging) in digital-to-analogue conversion |
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