CN113708687A

CN113708687A - Voltage vector adjusting method and device, motor controller and storage medium

Info

Publication number: CN113708687A
Application number: CN202111015648.2A
Authority: CN
Inventors: 陈俊桦; 洪伟鸿; 王豪浩; 周超; 彭国彬; 钟明胜
Original assignee: GD Midea Heating and Ventilating Equipment Co Ltd; Hefei Midea Heating and Ventilating Equipment Co Ltd
Current assignee: GD Midea Heating and Ventilating Equipment Co Ltd; Hefei Midea Heating and Ventilating Equipment Co Ltd
Priority date: 2021-08-31
Filing date: 2021-08-31
Publication date: 2021-11-26

Abstract

The application is applicable to the technical field of motors, and provides a voltage vector adjusting method, a voltage vector adjusting device, a motor controller and a storage medium, wherein an original comparison value is obtained according to the amplitude and the phase angle of a target voltage vector; determining a sub-sector where the target voltage vector is located according to the original comparison value, wherein the sub-sector is a sub-sector in one sector of the space voltage vector plane; when the sub-sector is positioned in the sampling blind area, a new comparison value is obtained by adopting a pulse width adjusting method corresponding to the sub-sector, so that the duration time of two effective vectors forming the target voltage vector in a half-carrier period is larger than the minimum sampling time, the deviation of the target voltage vector before and after adjustment can be effectively reduced, and the current harmonic wave introduced by the voltage vector deviation is reduced.

Description

Voltage vector adjusting method and device, motor controller and storage medium

Technical Field

The present application belongs to the field of motor technology, and in particular, to a voltage vector adjustment method, device, motor controller, and storage medium.

Background

High-performance motor control algorithms such as vector control algorithms, direct torque control algorithms, model predictive control algorithms, and the like generally rely on accurately detecting the phase current of the motor and perform closed-loop control based on the phase current detection values. In order to detect the phase current magnitudes, at least two current sensors are required in a three-phase motor system. However, the cost of the current sensor is high, and the overall cost of the motor controller is obviously increased; in addition, if a plurality of current sensors are adopted at the same time, the difference of different current sensors, such as the error existing in gain and zero position, will reduce the motor current control effect.

The single bus current detection technology is a technology for reducing the cost of a current sensor. The single-bus current detection only detects the bus current on a direct current bus in the motor controller, and determines the correlation between the bus current and the phase current of the motor according to the switching state of a three-phase bridge arm of the inverter, so as to estimate the phase current of the motor. The single-bus current detection method only needs one current sensor, so that the cost is greatly reduced, and the method is widely applied to cost-sensitive industries such as compressors of air conditioners, fans, motors of washing machines and the like.

The single bus current detection method has an inherent drawback in that the current on the bus can be corresponded to the phase current of the motor only when the voltage vector applied to the motor is an effective voltage vector. In consideration of disturbance caused by the switching action of the inverter and inherent delay of the analog-to-digital converter in the current detection process, the single-bus current detection method has minimum requirements on the vector pulse width of the effective voltage output by the inverter. In addition, in the reconstruction process of the motor phase current, the bus current needs to be continuously collected twice so as to be converted into two-phase current and calculate a third-phase current. However, when the output voltage is low or the output voltage is close to the space coordinate vector, the problem that the bus current cannot be effectively sampled due to the short duration of the effective space voltage vector exists, and the current reconstruction is invalid, namely, the current sampling dead zone is formed.

In the prior art, the problem of sampling blind areas is solved by a method for adjusting the pulse width of an effective space voltage vector. However, the voltage vector pulse width adjusting method in the prior art ignores the current harmonic problem caused by the voltage vector deviation between the effective space voltage vectors before and after adjustment.

Disclosure of Invention

The embodiment of the application provides a voltage vector adjusting method, a voltage vector adjusting device, a motor controller and a storage medium, and aims to solve the problem that current harmonics caused by voltage vector deviation between effective space voltage vectors before and after adjustment are ignored in a voltage vector pulse width adjusting method in the prior art.

A first aspect of an embodiment of the present application provides a voltage vector adjustment method, including:

obtaining an original comparison value according to the amplitude and the phase angle of the target voltage vector;

determining a sub-sector where the target voltage vector is located according to the original comparison value, wherein the sub-sector is a sub-sector in one sector of a space voltage vector plane;

and when the sub-sector is positioned in the sampling blind area, obtaining a new comparison value by adopting a pulse width adjusting method corresponding to the sub-sector, so that the duration time of two effective vectors forming the target voltage vector in a half-carrier period is greater than the minimum sampling time.

A second aspect of an embodiment of the present application provides a voltage vector adjustment apparatus, including:

the original value acquisition unit is used for acquiring an original comparison value according to the amplitude and the phase angle of the target voltage vector;

a sub-sector determining unit, configured to determine, according to the original comparison value, a sub-sector in which the target voltage vector is located, where the sub-sector is a sub-sector in a sector of a space voltage vector plane;

and the new value acquisition unit is used for acquiring a new comparison value by adopting a pulse width regulation method corresponding to the sub-sector when the sub-sector is positioned in the sampling blind area, so that the duration time of two effective vectors forming the target voltage vector in a half-carrier period is greater than the minimum sampling time.

A third aspect of embodiments of the present application provides a motor controller, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the voltage vector adjustment method of the first aspect of embodiments of the present application when executing the computer program.

A fourth aspect of embodiments of the present application provides a computer-readable storage medium, which stores a computer program that, when executed by a processor, implements the steps of the voltage vector adjustment method according to the first aspect of embodiments of the present application.

According to the voltage vector adjusting method provided by the first aspect of the embodiment of the application, an original comparison value is obtained according to the amplitude value and the phase angle of a target voltage vector; determining a sub-sector where the target voltage vector is located according to the original comparison value, wherein the sub-sector is a sub-sector in one sector of the space voltage vector plane; when the sub-sector is positioned in the sampling blind area, a new comparison value is obtained by adopting a pulse width adjusting method corresponding to the sub-sector, so that the duration time of two effective vectors forming the target voltage vector in a half-carrier period is larger than the minimum sampling time, the deviation of the target voltage vector before and after adjustment can be effectively reduced, and the current harmonic wave introduced by the voltage vector deviation is reduced.

It is understood that the beneficial effects of the second to fourth aspects can be seen from the description of the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a motor controller provided in an embodiment of the present application;

FIG. 2 is a first flowchart of a voltage vector adjustment method according to an embodiment of the present disclosure;

FIG. 3 is a table of calculation formulas of three-phase comparison values of a target voltage vector in six sectors of a space vector plane according to an embodiment of the present application;

FIG. 4 is a PWM waveform of a switching tube in a carrier period when a target voltage vector provided by an embodiment of the present application is located in a first sector of a space vector plane;

FIG. 5 is a PWM waveform of a switching tube in a carrier period after adjustment when a target voltage vector provided by an embodiment of the present application is located in a first sector of a space vector plane;

FIG. 6 is a second flowchart of a voltage vector adjustment method according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of region division of a first sector of a space vector plane according to an embodiment of the present application;

FIG. 8 is a third flowchart of a voltage vector adjustment method according to an embodiment of the present disclosure;

FIG. 9 is a fourth flowchart illustrating a voltage vector adjustment method according to an embodiment of the present disclosure;

fig. 10 is a fifth flowchart illustrating a voltage vector adjustment method according to an embodiment of the present application;

fig. 11 is a schematic diagram illustrating a principle of adjusting a sampled voltage vector when a target voltage vector provided by an embodiment of the present application is located in a first sub-region of a class of sampling dead zones;

FIG. 12 is a schematic diagram illustrating a principle of adjusting a sampled voltage vector when a target voltage vector is located in a second sub-region of a class of sampling dead zones according to an embodiment of the present application;

fig. 13 is a schematic diagram illustrating a regulation principle of a sampled voltage vector when a target voltage vector provided by an embodiment of the present application is located in a first sub-region of two types of sampling dead zones;

fig. 14 is a schematic diagram illustrating a regulation principle of a sampled voltage vector when a target voltage vector provided by an embodiment of the present application is located in a second sub-region of two types of sampling dead zones;

fig. 15 is a schematic diagram illustrating a regulation principle of a sampled voltage vector when a target voltage vector provided by an embodiment of the present application is located in a third sub-region of a second-type sampling dead zone;

fig. 16 is a schematic diagram illustrating a regulation principle of a sampling voltage vector when a target voltage vector provided by an embodiment of the present application is located in a first sub-region of a non-equivalent sampling dead zone;

fig. 17 is a schematic diagram illustrating a regulation principle of a sampling voltage vector when a target voltage vector provided by an embodiment of the present application is located in a second sub-region of a non-equivalent sampling dead zone;

fig. 18 is a schematic structural diagram of a voltage vector adjustment device according to an embodiment of the present application;

fig. 19 is a schematic structural diagram of a motor controller according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

The embodiment of the application provides a voltage vector adjusting method, which can be executed by a processor of a motor controller when running a corresponding computer program, is used for determining a sub-sector of a target voltage vector in a sector of a space vector plane when single-bus current detection is carried out, adjusting an original comparison value by adopting a pulse width adjusting method corresponding to the sub-sector of the target voltage vector when the sub-sector of the target voltage vector is positioned in a sampling blind area, obtaining a new comparison value, adjusting the pulse widths of two effective vectors forming the target voltage vector in a carrier cycle according to the new comparison value, so that the duration time of the two effective vectors in a half carrier cycle is greater than the minimum sampling time, effectively reducing the deviation of the target voltage vector before and after adjustment, reducing current harmonics introduced by the deviation of the voltage vector, and thus reducing the current harmonics, and eliminating the dead zone of single bus current sampling.

In application, the motor controller can be applied to an air conditioner, a fan and a washing machine and is used for driving and controlling the motor of the air conditioner, the fan and the motor of the washing machine, and the motor controller can be specifically a frequency converter.

As shown in fig. 1, a schematic diagram of a motor controller is exemplarily shown;

the motor controller comprises a processor, a current sensor and an inverter;

the current sensor is electrically connected with the negative electrode of the direct current bus and is used for detecting bus current on the direct current bus, and the current sensor is exemplarily shown in fig. 1 to be realized by a sampling resistor which is connected in series on the negative electrode of the direct current bus;

the first input end of the inverter is electrically connected with the positive pole of the direct current bus, the second input end of the inverter is electrically connected with the negative pole of the direct current bus, the six controlled ends of the inverter are electrically connected with the processor, the three output ends of the inverter are respectively electrically connected with the three phase current and phase voltage input ends of the motor, the inverter exemplarily shown in fig. 1 includes three-phase bridge arms (a-phase bridge arm, b-phase bridge arm and c-phase bridge arm), each of which includes two switching tubes (an upper switching tube and a lower switching tube), input ends of the upper switching tubes of the three-phase bridge arms are connected in common to constitute a first input end of the inverter, output ends of the lower switching tubes of the three-phase bridge arms are connected in common to constitute a second input end of the inverter 3, a controlled end of each switching tube constitutes one controlled end of the inverter, and an output end of the upper switching tube and an input end of the lower switching tube of each phase bridge arm are connected in common to constitute one output end of the inverter;

the processor is configured to:

acquiring target phase voltages (a-phase voltage, b-phase voltage and c-phase voltage) required to be applied to a stator according to a target rotor speed required to be reached by a motor so as to generate corresponding target phase currents (a-phase current ia, b-phase current ib and c-phase current ic) at the stator;

a Space Vector Pulse Width Modulation (SVPWM) method is adopted to determine a target voltage Vector according to a rotor angle and a target phase voltage, a three-phase comparison value is obtained through a comparison value calculation method based on the SVPWM method according to a target voltage Vector amplitude and a phase angle, then a triangular carrier is adopted to compare with the three-phase comparison value obtained through calculation, a generated Pulse Width Modulation (PWM) signal for driving a switching tube of a corresponding phase is generated, the on-off states of six switching tubes of a three-phase bridge arm of an inverter are controlled, and therefore three-phase voltages are output to a motor.

Controlling the on-off states of six switching tubes of a three-phase bridge arm of the inverter according to the PWM signals, so that the actual voltage of the bus voltage acting on the stator is equivalent to the target phase voltage, correspondingly, the actual current of the bus current acting on the stator is equivalent to the target phase current, and further the stator generates a corresponding magnetic field to drive the rotor to rotate at the target rotor speed; in order to improve the control precision of the motor, the bus current on the direct current bus needs to be acquired through a current sensor to obtain the magnitude of the bus current on the direct current bus, so that the magnitude of the actual phase current applied to the stator can be estimated based on the magnitude of the bus current, and by comparing the actual phase current with the target phase current, the target phase current may be adjusted based on a deviation between the actual phase current and the target phase current, and based on the adjusted target phase current, the adjusted target phase voltage can be obtained, the adjusted target voltage vector can be determined by combining a space vector pulse width modulation method, and generating an adjusted pulse width modulation signal according to the adjusted target voltage vector, controlling the on-off states of six switching tubes of a three-phase bridge arm of the inverter according to the adjusted pulse width modulation signal, and finally realizing feedback control on the motor.

In application, the switch tube has a function of turning on or off under the trigger of an electrical signal (PWM signal), and is used to play a role of an electronic switch, and specifically may be an Insulated Gate Bipolar Transistor (IGBT), a triode (Bipolar Junction Transistor, BJT), a Field Effect Transistor (FET), a Thyristor (Thyristor), or the like, where the IGBT is a composite fully-controlled voltage-driven power Semiconductor device composed of a Bipolar Transistor and an Insulated Gate Field Effect Transistor, and has advantages of both a high input impedance of the Insulated Gate Field Effect Transistor and a low on-state voltage drop of the Bipolar Transistor, and the FET may be a Metal-Oxide Semiconductor Field Effect Transistor (MOS-FET for short).

As shown in fig. 2, the voltage vector adjustment method provided in the embodiment of the present application includes the following steps S201 to S203:

step S201, obtaining an original comparison value according to the amplitude value and the phase angle of the target voltage vector.

In application, the original comparison value can be obtained by a comparison value calculation method based on the SVPWM method according to the magnitude and phase angle of the target voltage vector. The following describes a SVPWM comparison value calculation method in detail:

if the magnitude of the target voltage vector is Vr and the phase angle is θ 1, the modulation factor m1 is calculated by:

wherein Vdc is the bus voltage;

if theta 1 is greater than 0 and theta 1 is not greater than 1/3 x pi, the target voltage vector is located in a first sector of the space vector plane, and an angle theta m relative to the first sector is equal to theta 1;

if theta 1 is greater than 1/3 and theta 1 is less than or equal to 2/3, the target voltage vector is located in a second sector of the space vector plane, and the angle theta m relative to the second sector is theta 1-1/3;

if theta 1 is greater than 2/3 and theta 1 is less than or equal to 3/3, the target voltage vector is located in a third sector of the space vector plane, and the angle theta m relative to the third sector is theta 1-2/3;

if theta 1 is greater than 3/3 and theta 1 is less than or equal to 4/3, the target voltage vector is located in a fourth sector of the space vector plane, and the angle theta m relative to the fourth sector is theta 1-3/3;

if theta 1 is greater than 4/3 and theta 1 is less than or equal to 5/3, the target voltage vector is located in a fifth sector of the space vector plane, and the angle theta m relative to the fifth sector is theta 1-4/3;

if theta 1 is greater than 5/3 and theta 1 is less than or equal to 2, the target voltage vector is located in a sixth sector of the space vector plane, and an angle theta m relative to the sixth sector is theta 1-5/3;

and calculating the duration ratio Tm1 and Tm2 of the two effective vectors in the carrier period based on m1 and thetam:

wherein Tm is the maximum value of the carrier counter, that is, the maximum carrier cycle count value;

the calculation method of the duration ratio Tm0 of the zero vector comprises the following steps:

Tm0＝0.5*(1-Tm1-Tm2)*Tm

as shown in fig. 3, an exemplary calculation formula table showing three-phase comparison values (i.e., original comparison values) of the target voltage vector in six sectors of the space vector plane; wherein, the comparison value of the phase A at the carrier falling edge is DDA0, and the comparison value of the carrier rising edge is DUA 0; the comparison value of the phase B at the carrier falling edge is DDB0, and the comparison value of the carrier rising edge is DUB 0; the comparison value of the C phase at the carrier falling edge is DDC0, and the comparison value at the carrier rising edge is DUC 0. In the symmetric sampling mode, the comparison value of the carrier falling edge is the same as the comparison value of the carrier rising edge, that is, DDA0 ═ DUA0, DDB0 ═ DUB0, and DDC0 ═ DUC 0.

In application, the triangular carrier wave is used for comparing with the three-phase comparison value obtained through calculation, and PWM waveforms for driving the switching tubes of the corresponding phases are generated. For convenience of expression, a carrier period is defined as Ts, a half-carrier period is defined as Tsh, and a carrier maximum value is defined as DT. The SVPWM sampling mode is asymmetric sampling, that is, the comparison values corresponding to the carrier falling edge and the carrier rising edge may be different. The carrier wave comparison action generates the PWM waveform of the three-phase switch tube to form the PWM waveform of the traditional 7-segment switch tube, and the vector action sequence of the carrier falling edge is as follows: zero vector → significant vector 1 → significant vector 2 → zero vector; the vector action sequence of the rising edge of the carrier wave is as follows: zero vector → significant vector 2 → significant vector 1 → zero vector.

As shown in fig. 4, the PWM waveform of the switching tube in the SVPWM carrier period is exemplarily shown when the target voltage vector is located in the first sector of the space vector plane; wherein, the effective vector 1 is a space voltage vector 100, and the duration is T1; the active vector 2 is a space voltage vector 110 with a duration T2, Tmin represents the minimum sampling time, Tsh represents the half carrier period, and Ts represents the carrier period.

In application, based on a single bus current detection method, bus currents in the duration of two adjacent effective vectors (namely effective vector 1 and effective vector 2) are respectively detected, and corresponding motor phase currents are estimated. The relationship between the bus current sensing and the phase current and space voltage vector is:

if the voltage at the bus current detection moment is the space voltage vector 100, the bus current is equal to the phase A current;

if the voltage at the bus current detection moment is the space voltage vector 110, the bus current is equal to the negative C-phase current;

if the voltage at the bus current detection moment is the space voltage vector 101, the bus current is equal to the negative B-phase current;

if the voltage at the bus current detection moment is a space voltage vector 010, the bus current is equal to the phase B current;

if the voltage at the bus current detection moment is the space voltage vector 011, the bus current is equal to the negative A-phase current;

if the voltage at the bus current detection time is the space voltage vector 001, the bus current is equal to the C-phase current.

In order to realize the motor phase current reconstruction based on the single bus current detection method, the duration of the two effective vectors needs to meet the condition related to the minimum sampling time Tmin required for sampling, namely, T1 and T2 are both greater than or equal to Tmin. However, during actual operation of the motor, there are cases where either T1 or T2 is less than Tmin, in which case motor phase current reconstruction based on the single bus current detection method will fail, defined as a sampling dead zone.

In application, in order to solve the problem of failure of motor phase current reconstruction in a sampling blind area, the pulse width of the PWM waveform of the switching tube corresponding to the two effective vectors needs to be adjusted, so that the duration T1 and T2 of the two effective vectors are both greater than or equal to Tmin. A sampling blind area processing mode is as follows: by adjusting the three-phase comparison values, the duration of both effective vectors is greater than Tmin.

As shown in fig. 5, the PWM waveform of the switching tube in the adjusted SVPWM carrier period when the target voltage vector is located in the first sector of the space vector plane is exemplarily shown; wherein, the comparison value of the adjusted A phase on the carrier falling edge is DDA, and the comparison value of the adjusted A phase on the carrier rising edge is DUA; the comparison value of the adjusted B phase on the falling edge of the carrier wave is DDB, and the comparison value of the adjusted B phase on the rising edge of the carrier wave is DUB; the comparison value of the adjusted C phase at the falling edge of the carrier wave is DDC, and the comparison value of the adjusted C phase at the rising edge of the carrier wave is DUC.

In application, if T1 is smaller than Tmin, the comparison value DDA of the adjusted a phase at the falling edge of the carrier is:

DDA＝DDB0+Dmin

where Dmin represents the magnitude of the variation in which Tmin is reflected on the carrier. Meanwhile, in order to keep the output voltage of the phase a constant, the adjustment amount of the comparison value of the phase a at the falling edge of the carrier needs to be reduced, that is:

DUA＝DUA0-(DDA-DDA0)

it is understood that the comparison value of the a phase in the carrier period may also be adjusted by increasing the comparison value of the a phase at the carrier falling edge and decreasing the comparison value of the a phase at the carrier rising edge, that is, the DUA-DUB 0+ Dmin and the DDA-DDA 0- (DUA-DUA 0).

Step S202, determining a sub-sector where the target voltage vector is located according to the original comparison value, wherein the sub-sector is a sub-sector in one sector of the space voltage vector plane;

step S203, when the sub-sector is located in the sampling blind area, a new comparison value is obtained by adopting a pulse width adjusting method corresponding to the sub-sector, and the duration time of two effective vectors forming the target voltage vector in a half-carrier period is larger than the minimum sampling time.

In application, the blind area processing mode shown in fig. 5 ignores the current harmonic problem caused by the voltage vector deviation between the effective space voltage vectors before and after adjustment, so that a mode of further partitioning each sector of the space vector plane is adopted, the original comparison value is adjusted by adopting a corresponding pulse width adjusting method for different partitions to obtain a new comparison value, the pulse width of the effective vector in a carrier period is adjusted according to the new comparison value, and the deviation of the target voltage vector before and after adjustment is reduced, so that the current harmonic caused by the voltage vector deviation can be reduced, a triangular carrier is compared with the new three-phase comparison value to generate a PWM signal for controlling the inverter, and the inverter is controlled to output three-phase voltage to the motor.

As shown in fig. 6, in one embodiment, step S202 includes the following steps S601 and S602:

step S601, determining the duration of two effective vectors forming a target voltage vector in a half-carrier period according to the original comparison value;

step S602, determining the sub-sector where the target voltage vector is located according to the duration of the two effective vectors.

In application, the duration of two valid vectors is obtained from the ratio of the duration of two valid vectors within a carrier period Tm1 and Tm2 and the carrier period. The duration of the two effective vectors is different, the current sampling effect is different, each sector of the space vector plane is further divided into a plurality of sub-sectors according to the difference of the current sampling effect in the space vector plane, and when the duration of the two effective vectors meets different relations, the corresponding target voltage vectors are in different sub-sectors.

As shown in fig. 7, an exemplary region partition diagram of a first sector of a space vector plane is shown; the first sector is divided into 8 sub-sectors of R1-R8, R5 is a sampling area, R2 is a first sub-area in a first type of sampling dead zone, R8 is a second sub-area in a first type of sampling dead zone, R1 is a first sub-area in a second type of sampling dead zone, R4 is a second sub-area in a second type of sampling dead zone, R6 is a third sub-area in the second type of sampling dead zone, R3 is a first sub-area in a non-equivalent sampling dead zone, and R7 is a second sub-area in the non-equivalent sampling dead zone.

It should be understood that the region partition rule of other sectors of the space vector plane is the same as the region partition rule of the first sector, and may be derived according to the region partition rule of the first sector, and is not described herein again.

As shown in fig. 8, in one embodiment, the two effective vectors include a first effective vector (i.e., effective vector 1) and a second effective vector (i.e., effective vector 2), and the step S602 includes the following steps S801 to S808:

and S801, when the duration of the two effective vectors is larger than the minimum sampling time, determining that the target voltage vector is in a sampling area.

In use, the region R5 shown in fig. 7 is a sampleable region. If the target voltage vector is located in the region R5 shown in fig. 7, the durations T1 and T2 of the two effective vectors constituting the target voltage vector in the half carrier period are both longer than the minimum sampling time Tmin, and the current sampling operation can be performed directly without performing voltage vector adjustment.

S802, when the duration time of the first effective vector is less than the minimum sampling time and the two effective vectors meet a first relation, determining a first sub-area of the target voltage vector in a class of sampling blind areas;

and S803, when the duration of the second effective vector is less than the minimum sampling time and the two effective vectors meet a second relation, determining that the target voltage vector is in a second sub-area in the class-I sampling blind area.

In application, one type of sampling dead zone includes the first sub-zone R2 and the second sub-zone R8 shown in fig. 7;

if the target voltage vector is located in the region of R2 shown in fig. 7, the duration T2 of the first valid vector constituting the target voltage vector is less than the minimum sampling time Tmin, and T1 and T2 satisfy the following first relationship:

3*Tmin≤T1+2*T2≤2*Tsh-Tmin

if the target voltage vector is located in the region of R8 shown in fig. 7, the duration T2 of the second valid vector constituting the target voltage vector is less than the minimum sampling time Tmin, and T1 and T2 satisfy the following second relationship:

3*Tmin≤T2+2*T1≤2*Tsh-Tmin。

s804, when the two effective vectors meet a third relation, determining a first sub-area of the target voltage vector in the second type of sampling blind area;

s805, when the duration of the first effective vector is less than the minimum sampling time, the duration of the second effective vector is less than the minimum sampling time obtained by subtracting 0.5 times from the half-carrier period, and the two effective vectors meet a fourth relation, determining that the target voltage vector is in a second sub-area in the second-class sampling dead zone;

and S806, when the duration of the second effective vector is less than the minimum sampling time, the duration of the first effective vector is less than the minimum sampling time obtained by subtracting 0.5 times from the half-carrier period, and the two effective vectors meet a fifth relation, determining that the target voltage vector is in a third sub-region of the second-class sampling dead zone.

In application, the second type of sampling dead zone includes the first sub-zone R1, the second sub-zone R4, and the third to sector R6 shown in fig. 7;

if the target voltage vector is located in the region R1 shown in fig. 7, the durations T1 and T2 of the two effective vectors constituting the target voltage vector within a half carrier period satisfy the following third relationship:

T1+2*T2≤3*Tmin

if the target voltage vector is located in the region of R4 shown in fig. 7, the duration T1 of the first effective vector constituting the target voltage vector is less than the minimum sampling time Tmin, the duration T2 of the second effective vector constituting the target voltage vector is less than the minimum sampling time Tmin of the half-carrier period Tsh minus 0.5 times, and T1 and T2 satisfy the following fourth relationship:

T1+2*T2≥2*Tsh-Tmin

if the target voltage vector is located in the region R6 shown in fig. 7, the duration T2 of the second effective vector constituting the voltage vector is less than the minimum sampling time Tmin, the duration T1 of the first effective vector constituting the target voltage vector is less than the minimum sampling time Tmin of the half-carrier period Tsh minus 0.5 times, and T1 and T2 satisfy the following fifth relationship:

T2+2*T1≥2*Tsh-Tmin。

s807, when the duration of the first effective vector is less than 0.5 times of the minimum sampling time and the duration of the second effective vector is greater than the half-carrier period minus 0.5 times of the minimum sampling time, determining a first sub-area of the target voltage vector in the nonequivalent sampling dead zone;

and S808, when the duration of the second effective vector is less than 0.5 times of the minimum sampling time and the duration of the first effective vector is greater than the half-carrier period minus 0.5 times of the minimum sampling time, determining a second sub-area of the target voltage vector in the nonequivalent sampling dead zone.

In application, the nonequivalent sampling dead zone comprises the first sub-region R3 and the second sub-region R7 shown in fig. 7;

if the target voltage vector is located in the region R3 shown in fig. 7, the duration T1 of the first active vector constituting the target voltage vector is less than 0.5 times the minimum sampling time Tmin, and the duration T2 of the second active vector constituting the target voltage vector is greater than the half-carrier period Tsh minus 0.5 times the minimum sampling time Tmin;

if the target voltage vector is located in the region R7 shown in fig. 7, the duration T2 of the second active vector constituting the target voltage vector is less than 0.5 times the minimum sampling time Tmin, and the duration T1 of the first active vector constituting the target voltage vector is greater than the half-carrier period Tsh minus 0.5 times the minimum sampling time Tmin.

As shown in fig. 9, in one embodiment, step S203 includes the following steps S901 to S904:

step S901, when the sub-sector is positioned in the sampling blind area, a pulse width adjusting method corresponding to the sub-sector is adopted to obtain a sampling voltage vector in a first half carrier period;

step S902, obtaining a new comparison value in the first half carrier period according to the sub-sector, the original comparison value in the first half carrier period and the sampling voltage vector;

step S903, obtaining a compensation voltage vector in a second half-carrier period according to the sampling voltage vector, and enabling the deviation between a synthetic vector of the sampling voltage vector and the compensation voltage vector and a target voltage vector to be minimum;

step S904, obtaining a new comparison value in the second half-carrier period according to the sub-sector, the original comparison value in the second half-carrier period, and the compensation voltage vector.

In application, when a target voltage vector Vr is obtained through calculation by an SVPWM (space vector pulse width modulation) method, aiming at the target voltage vector positioned in a sampling blind zone, two voltage vectors are output by adopting an asymmetric sampling method in a carrier period Ts, one of the two voltage vectors is defined as a sampling voltage vector Vs, and duration time T1 and T2 of the two effective voltage vectors forming the target voltage vector are both greater than minimum sampling time Tmin; the other voltage vector is defined as a compensation voltage vector Vc for synthesizing the target space vector Vr with the sampling voltage vector Vs in order to make the actual voltage vector output within the carrier period equivalent to the target voltage vector Vr.

In application, if the target voltage vector Vr is located in any sampling blind area, the pulse width adjustment of the effective vector of the carrier rising edge or the carrier falling edge is required. The first half carrier period and the second half carrier period are respectively one of a carrier rising edge period and a carrier falling edge period, that is, the sampling voltage vector Vs can be located in the carrier falling edge period, and the compensation voltage vector Vc is located in the carrier rising edge period of the same carrier period; the sampling voltage vector Vs may also be located in a rising edge period of the carrier, and the compensation voltage vector Vc is located in a falling edge period of the carrier in the same carrier period.

In application, different pulse width adjusting methods are respectively adopted according to the region where the target voltage vector Vr is located to obtain a sampling voltage vector Vs, and a compensation voltage vector Vc is obtained based on the sampling voltage vector Vs, so that the deviation between a synthetic vector of the sampling voltage vector Vs and the target voltage vector Vr is minimum, namely, an actual voltage vector output in a carrier period is equivalent to the target voltage vector Vr as much as possible. And then calculating new comparison values in the corresponding half-carrier period in the regions where the compensation voltage vector Vc and the target voltage vector Vr are respectively obtained according to the sampling voltage vector Vs.

As shown in fig. 10, in one embodiment, step S901 includes the following steps S1001 to S1003:

step S1001, when the sub-sector is located in a sampling blind area of the same type, in a space vector plane, the terminal point of the target voltage vector is used as a first vertical line of a first boundary line adjacent to the target voltage vector in the sampling area, and the intersection point of the first vertical line and the first boundary line is used as the terminal point of the sampling voltage vector.

As shown in fig. 11, an exemplary schematic diagram illustrates the adjustment principle of the sampled voltage vector when the target voltage vector is located in the first sub-region of the sampling dead zone; the target voltage vector Vr is located in a first sub-area R2 of a sampling dead zone, the end point of the target voltage vector Vr is taken as a first vertical line of a first boundary line O1O2 adjacent to the target voltage vector Vr in the sampling region R5 in the space vector plane, and the intersection point of the first vertical line and the first boundary line O1O2 is taken as the end point of the sampling voltage vector Vs.

As shown in fig. 12, an exemplary schematic diagram illustrating the adjustment principle of the sampled voltage vector when the target voltage vector is located in the second sub-region of the sampling dead zone; the target voltage vector Vr is located in a second sub-area R8 of the sampling dead zone, the end point of the target voltage vector Vr is taken as a first vertical line of a first boundary line O1O3 adjacent to the target voltage vector Vr in the sampling region R5 in the space vector plane, and the intersection point of the first vertical line and the first boundary line O1O3 is taken as the end point of the sampling voltage vector Vs.

Step S1002, when the sub-sector is located in the second-class sampling blind area, in the space vector plane, taking the end point, closest to the end point of the target voltage vector, in the sampling area as the end point of the sampling voltage vector.

As shown in fig. 13, an exemplary schematic diagram of the adjustment principle of the sampled voltage vector when the target voltage vector is located in the first sub-region of the two types of sampling dead zones is shown; the target voltage vector Vr is located in a first sub-area R1 of the second type of sampling dead zone, and an endpoint O1 closest to the endpoint of the target voltage vector Vr in the sampling zone R5 is taken as the endpoint of the sampling voltage vector Vs in the space vector plane.

As shown in fig. 14, an exemplary schematic diagram of the adjustment principle of the sampled voltage vector when the target voltage vector is located in the second sub-region of the two types of sampling dead zones is shown; the target voltage vector Vr is located in a second sub-area R4 of the second type of sampling dead zone, and an endpoint O2 closest to the endpoint of the target voltage vector Vr in the sampling zone R5 is taken as the endpoint of the sampling voltage vector Vs in the space vector plane.

As shown in fig. 15, an exemplary schematic diagram of the adjustment principle of the sampled voltage vector when the target voltage vector is located in the third sub-region of the two types of sampling dead zones is shown; the target voltage vector Vr is located in a third sub-area R6 of the second-type sampling dead zone, and an endpoint O3, which is closest to the endpoint of the target voltage vector Vr in the sampling area R5, is taken as the endpoint of the sampling voltage vector Vs in the space vector plane.

And step S1003, when the sub-sector is located in the nonequivalent sampling blind area, in a space vector plane, the end point of the target voltage vector is used as a second perpendicular line of a second boundary line adjacent to the target voltage vector in the second type of sampling blind area, the intersection point of the second perpendicular line and the second boundary line is used as the end point of the corrected target voltage vector, and the end point, closest to the end point of the corrected target voltage vector, in the sampling-capable area is used as the end point of the sampling voltage vector.

As shown in fig. 16, an exemplary schematic diagram of the adjustment principle of the sampled voltage vector when the target voltage vector is located in the first sub-region of the non-equivalent sampling dead zone is shown; the target voltage vector Vr is located in a first sub-area R3 of the nonequivalent sampling dead zone, in the space vector plane, a second perpendicular line of a second boundary line O4O5 adjacent to the target voltage vector Vr in a first sub-area R3 of which the end point of the target voltage vector Vr is a second type of sampling dead zone, the intersection point of the second perpendicular line and the second boundary line O4O5 is used as the end point of the corrected target voltage vector Vr1, and the end point O2, which is closest to the end point of the corrected target voltage vector Vr1, in the sampling area R5 is used as the end point Vs of the sampling voltage vector.

As shown in fig. 17, an exemplary schematic diagram illustrating the adjustment principle of the sampled voltage vector when the target voltage vector is located in the second sub-region of the non-equivalent sampling dead zone is shown; the target voltage vector Vr is located in the second sub-region R7 of the nonequivalent sampling dead zone, in the space vector plane, a second perpendicular line of a second boundary line O6O7 adjacent to the target voltage vector Vr in the second sub-region R7 of which the end point of the target voltage vector Vr is a second type of sampling dead zone, the intersection point of the second perpendicular line and the second boundary line O6O7 is used as the end point of the corrected target voltage vector Vr1, and the end point O3, which is closest to the end point of the corrected target voltage vector Vr1, in the sampling region R5 is used as the end point Vs of the sampling voltage vector.

In one embodiment, when the sub-sector is located in the first-type sampling blind area or the second-type sampling blind area, the calculation formula of the compensation voltage vector is as follows:

Vc＝2*Vr-Vs

when the sub-sector is located in the nonequivalent sampling blind area, the calculation formula of the compensation voltage vector is as follows:

Vc＝2*Vr1-Vs

where Vc denotes the compensation voltage vector, Vr denotes the target voltage vector, Vr1 denotes the corrected target voltage vector, and Vs denotes the sampling voltage vector.

In application, in order to make the actual voltage vector output in the carrier period equivalent to the target voltage vector, the compensation voltage vector may be obtained by vector subtraction.

In one embodiment, when the sub-sector is located in the first sub-region of a class of sampling dead zones, the new comparison value in the first half-carrier period is calculated as:

DDA＝DDA1-DDS，DDB＝DDB1-DDS，DDC＝DDC1-DDS

DDA1＝DDB0+Dmin，DDB1＝DDB0，DDC1＝DDC0+0.5*(Dmin-DDA1)

DDS＝0.5*DT-0.5(DDMAX-DDMIN)

when the sub-sector is located in the second sub-region in the first type of sampling dead zone, the calculation formula of the new comparison value in the first half carrier period is as follows:

DDA＝DDA1-DDS，DDB＝DDB1-DDS，DDC＝DDC1-DDS

DDA1＝DDB0-0.5*(Dmin-DDC0)，DDB1＝DDB0，DDC1＝DDB0-Dmin

DDS＝0.5*DT-0.5(DDMAX-DDMIN)

the DDA, DDB and DDC represent three-phase new comparison values in a first half carrier period, the DDA0, DDB0 and DDC0 represent three-phase original comparison values in the first half carrier period, the DDA1, DDB1 and DDC1 represent three-phase comparison values to be adjusted in the first half carrier period, the DDS represents the offset of the three-phase comparison values to be adjusted in the first half carrier period, the Dmin represents the size of the minimum sampling time Tmin reflected on the carrier, the DT represents the maximum value of the carrier, and the DDMAX and DDMIN represent the maximum value and the minimum value of the DDA1, the DDB1 and the DDC1 respectively.

In application, when the sub-sector where the target voltage vector Vr is located in the first sub-region R2 in one type of sampling dead zone, the method for calculating the three-phase comparison value corresponding to the sampling voltage vector Vs (i.e. the three-phase comparison value to be adjusted in the first half carrier period) is as follows:

DDA1＝DDB0+Dmin，DDB1＝DDB0，DDC1＝DDC0+0.5*(Dmin-DDA1)

because the adjusted comparison value has a risk of exceeding the maximum value DT of the carrier and being lower than zero, the three-phase comparison value corresponding to the sampled voltage vector Vs needs to be centered, and an offset DDS of the sampled voltage vector Vs is defined, and the calculation method is as follows:

DDS＝0.5*DT-0.5(DDMAX-DDMIN)

and adjusting the three-phase comparison value corresponding to the sampling voltage vector after centering into:

DDA＝DDA1-DDS，DDB＝DDB1-DDS，DDC＝DDC1-DDS；

similarly, when the sub-sector where the target voltage vector Vr is located in the second sub-sector R8 in the sampling dead zone, the method for calculating the three-phase comparison value corresponding to the sampling voltage vector Vs includes:

DDA1＝DDB0-0.5*(Dmin-DDC0)，DDB1＝DDB0，DDC1＝DDB0-Dmin

DDS＝0.5*DT-0.5(DDMAX-DDMIN)

then the three-phase comparison value corresponding to the centered sampled voltage vector Vs is adjusted to be:

DDA＝DDA1-DDS，DDB＝DDB1-DDS，DDC＝DDC1-DDS。

in one embodiment, when the sub-sector is located in a type of sampling blind area, the new comparison value in the second half-carrier period is calculated as:

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS

DUA1＝DUA0-(DDA1-DDA0)，DUB1＝DUB0-(DDB1-DDB0)，DUC1＝DUC0-(DDC1-DDC0)

DUS＝0.5*DT-0.5(DUMAX-DUMIN)

the DUA, the DUB and the DUC represent new three-phase comparison values in the second half-carrier period, the DUA0, the DUB0 and the DUC0 represent original three-phase comparison values in the second half-carrier period, the DUA1, the DUB1 and the DUC1 represent three-phase comparison values to be adjusted in the second half-carrier period, the DUS represents offset of the three-phase comparison values to be adjusted in the second half-carrier period, and the DUMAX and the DUMIN represent maximum values and minimum values in the DUA1, the DUB1 and the DUC1 respectively.

In application, when the sub-sector where the target voltage vector Vr is located in the first sub-region R2 and the second sub-region R8 in the first-class sampling dead zone, the calculation method of the compensation voltage vector Vc is the same, and the calculation method of the three-phase comparison value (that is, the three-phase comparison value to be adjusted in the second half-carrier period) corresponding to the compensation voltage vector Vc is as follows:

DUA1＝DUA0-(DDA1-DDA0)，DUB1＝DUB0-(DDB1-DDB0)，DUC1＝DUC0-(DDC1-DDC0)

because the adjusted comparison value has a risk of exceeding the maximum value DT of the carrier and being lower than zero, the three-phase comparison value corresponding to the compensation voltage vector Vc needs to be centered, and an offset DUS of the compensation voltage vector Vc is defined, and the calculation method is as follows:

DUS＝0.5*DT-0.5(DUMAX-DUMIN)

then the three-phase comparison value corresponding to the centered compensation voltage vector Vc is adjusted to be:

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS。

in one embodiment, when the sub-sector is located in the first sub-region of the second type of sampling shadow region, the new comparison value in the first half carrier period is calculated as:

DDA＝DDB0+Dmin，DDB＝DDB0，DDC＝DDB0-Dmin

when the sub-sector is located in the second sub-region in the second type of sampling dead zone, the calculation formula of the new comparison value in the first half carrier period is as follows:

DDA＝DT，DDB＝DT-Dmin，DDC＝0

when the sub-sector is located in the third sub-region in the second type of sampling dead zone, the calculation formula of the new comparison value in the first half carrier period is as follows:

DDA＝DT，DDB＝Dmin，DDC＝0

wherein DDA, DDB, and DDC represent three-phase new comparison values in the first half carrier period, DDA0, DDB0, and DDC0 represent three-phase original comparison values in the first half carrier period, Dmin represents the magnitude of the minimum sampling time on the carrier, and DT represents the maximum value of the carrier.

In one embodiment, when the sub-sector is located in the class ii sampling blind region, the new comparison value in the second half-carrier period is calculated as:

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS

DUA1＝DUA0-(DDA1-DDA0)，DUB1＝DUB0-(DDB1-DDB0)，DUC1＝DUC0-(DDC1-DDC0)

DUS＝0.5*DT-0.5(DUMAX-DUMIN)

In application, when the sub-sectors where the target voltage vector Vr is located are located in the first sub-sector R2, the second sub-sector R4 and the third sub-sector R6 in the two types of sampling dead zones, the calculation method of the compensation voltage vector Vc is the same, and the calculation method of the three-phase comparison value (that is, the three-phase comparison value to be adjusted in the second half-carrier period) corresponding to the compensation voltage vector Vc is as follows:

DUA1＝DUA0-(DDA1-DDA0)，DUB1＝DUB0-(DDB1-DDB0)，DUC1＝DUC0-(DDC1-DDC0)

DUS＝0.5*DT-0.5(DUMAX-DUMIN)

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS。

in one embodiment, when the sub-sector is located in the first sub-region in the nonequivalent sampling dead zone, the new comparison value in the first half-carrier period is calculated by the formula:

DDA＝DT，DDB＝DT-Dmin，DDC＝0

when the sub-sector is located in the second sub-region in the nonequivalent sampling dead zone, the calculation formula of the new comparison value in the first half carrier period is as follows:

DDA＝DT，DDB＝Dmin，DDC＝0

wherein DDA, DDB and DDC represent the new comparison values of the three phases in the first half-carrier period, Dmin represents the magnitude of the minimum sampling time on the carrier, and DT represents the maximum value of the carrier.

In one embodiment, when the sub-sector is located in the nonequivalent sampling blind area, the new comparison value in the second half-carrier period is calculated as:

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS

DUA1＝DUA0-(DDA1-DDA0)，DUB1＝DUB0-(DDB1-DDB0)，DUC1＝DUC0-(DDC1-DDC0)

DUS＝0.5*DT-0.5(DUMAX-DUMIN)

the DUA, the DUB and the DUC represent three-phase new comparison values in a second half-carrier period, the DDA0, the DDB0 and the DDC0 represent three-phase original comparison values in the first half-carrier period obtained according to the corrected target voltage vector, the DUA0, the DUB0 and the DUC0 represent three-phase original comparison values in the second half-carrier period obtained according to the corrected target voltage vector, the DUA1, the DUB1 and the DUC1 represent three-phase comparison values to be adjusted in the second half-carrier period, the DUS represents three-phase comparison value offset to be adjusted in the second half-carrier period, and the DUMAX and the DUMIN represent maximum values and minimum values in the DUA1, the DUB1 and the DUC1 respectively.

In application, when the sub-sector where the target voltage vector Vr is located in the first sub-region R3 and the second sub-region R7 in the nonequivalent sampling dead zone, the calculation method of the compensation voltage vector Vc is the same, and the calculation method of the three-phase comparison value (that is, the three-phase comparison value to be adjusted in the second half-carrier period) corresponding to the compensation voltage vector Vc is as follows:

DUA1＝DUA0-(DDA1-DDA0)，DUB1＝DUB0-(DDB1-DDB0)，DUC1＝DUC0-(DDC1-DDC0)

DUS＝0.5*DT-0.5(DUMAX-DUMIN)

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS。

it should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

In the above embodiments, only the voltage vector adjustment method when the target voltage vector is located in the first sector of the space vector plane is exemplarily described, the voltage vector adjustment method when the target voltage vector is located in the other sectors may be derived according to the same principle, and in the above embodiments, only the new comparison value calculation method when the first half carrier period is the carrier falling edge period and the second half carrier period is the carrier rising edge period and the new comparison value calculation method when the first half carrier period is the carrier rising edge period and the second half carrier period is the carrier falling edge period may be derived according to the same principle, which is not repeated in this embodiment.

The embodiment of the application further provides a voltage vector adjusting device, which is applied to a motor controller and used for executing the steps in the method embodiment. The device may be a virtual appliance (virtual appliance) in the motor controller, run by a processor of the motor controller, or the motor controller itself.

As shown in fig. 18, the voltage vector adjustment apparatus 100 according to the embodiment of the present application includes:

an original value obtaining unit 101, configured to obtain an original comparison value according to an amplitude and a phase angle of the target voltage vector;

a sub-sector determining unit 102, configured to determine, according to the original comparison value, a sub-sector in which the target voltage vector is located, where the sub-sector is a sub-sector in a sector of the space voltage vector plane;

and a new value obtaining unit 103, configured to obtain a new comparison value by using a pulse width modulation method corresponding to the sub-sector when the sub-sector is located in the sampling blind area, so that the durations of two effective vectors forming the target voltage vector in a half-carrier period are both longer than the minimum sampling time.

In application, each component in the above apparatus may be a software program unit, may also be implemented by different logic circuits integrated in a processor or a separate physical component connected to the processor, and may also be implemented by a plurality of distributed processors.

As shown in fig. 19, an embodiment of the present application further provides a motor controller 200, including: at least one processor 201 (only one processor is shown in fig. 19), a memory 202, and a computer program 203 stored in the memory 202 and executable on the at least one processor 201, the steps in the various method embodiments described above being implemented when the computer program 203 is executed by the processor 201.

In an application, the motor controller may include, but is not limited to, a processor and a memory, and may also include the current sensor and inverter shown in fig. 1, and/or may also include a filter, a PWM driver, an analog-to-digital converter, and the like. It will be understood by those skilled in the art that fig. 19 is merely an example of a motor controller, and does not constitute a limitation of a motor controller, and may include more or less components than those shown, or combine some components, or different components, for example, input-output devices, network access devices, etc. The input and output device can comprise the human-computer interaction device and can also comprise a display screen for displaying the working parameters of the motor controller. The network access device may include a communication module for the motor controller to communicate with the client.

In an Application, the Processor may be a Central Processing Unit (CPU), and the Processor may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

In application, the memory may in some embodiments be an internal storage unit of the motor controller, such as a hard disk or a memory of the motor controller. The memory may also be an external storage device of the motor controller in other embodiments, such as a plug-in hard disk provided on the motor controller, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. The memory may also include both an internal storage unit of the motor controller and an external storage device. The memory is used for storing an operating system, an application program, a Boot Loader (Boot Loader), data, and other programs, such as program codes of computer programs. The memory may also be used to temporarily store data that has been output or is to be output.

In application, the Display may be a Thin Film Transistor Liquid Crystal Display (TFT-LCD), a Liquid Crystal Display (LCD), an Organic electroluminescent Display (OLED), a Quantum Dot Light Emitting diode (QLED) Display, a seven-segment or eight-segment digital tube, and the like.

In application, the communication module can be set as any device capable of directly or indirectly carrying out long-distance wired or wireless communication with the client according to actual needs, so that a user can control the working state of the motor by operating the client through the motor controller, and further control the working states of equipment such as an air conditioner, a fan, a washing machine and the like applied to the motor. The Communication module may provide a solution for Communication applied to the network device, including Wireless Local Area Networks (WLANs) (e.g., Wi-Fi Networks), bluetooth, Zigbee, mobile Communication Networks, Global Navigation Satellite Systems (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), Infrared (IR), and the like. The communication module may include an antenna, and the antenna may have only one array element, or may be an antenna array including a plurality of array elements. The communication module can receive electromagnetic waves through the antenna, frequency-modulate and filter electromagnetic wave signals, and send the processed signals to the processor. The communication module can also receive a signal to be sent from the processor, frequency-modulate and amplify the signal, and convert the signal into electromagnetic waves through the antenna to radiate the electromagnetic waves.

It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/modules, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and reference may be made to the part of the embodiment of the method specifically, and details are not described here.

It will be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely illustrated, and in practical applications, the above function distribution may be performed by different functional modules according to needs, that is, the internal structure of the apparatus is divided into different functional modules to perform all or part of the above described functions. Each functional module in the embodiments may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module, and the integrated module may be implemented in a form of hardware, or in a form of software functional module. In addition, specific names of the functional modules are only used for distinguishing one functional module from another, and are not used for limiting the protection scope of the application. The specific working process of the modules in the system may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.

The embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

Embodiments of the present application provide a computer program product, which when run on a motor controller, enables the motor controller to implement the steps in the above-described method embodiments.

The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a motor controller, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and in actual implementation, there may be other divisions, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A voltage vector adjustment method, comprising:

2. The voltage vector adjustment method of claim 1, wherein when the sub-sector is located in a sampling blind area, obtaining a new comparison value by a pulse width adjustment method corresponding to the sub-sector comprises:

when the sub-sector is positioned in a sampling blind area, obtaining a sampling voltage vector in a first half carrier period by adopting a pulse width adjusting method corresponding to the sub-sector;

obtaining a new comparison value in the first half carrier period according to the sub-sector, the original comparison value in the first half carrier period and the sampling voltage vector;

according to the sampling voltage vector, obtaining a compensation voltage vector in a second half carrier period, and enabling the deviation between the synthesized vector of the sampling voltage vector and the compensation voltage vector and the target voltage vector to be minimum;

and obtaining a new comparison value in the second half-carrier period according to the sub-sector, the original comparison value in the second half-carrier period and the compensation voltage vector.

3. The voltage vector adjustment method of claim 2, wherein obtaining the sampled voltage vector using a pulse width adjustment method corresponding to the sub-sector when the sub-sector is located in a sampling blind area comprises:

when the sub-sector is positioned in a sampling blind area of one type, in a space vector plane, the terminal point of the target voltage vector is used as a first vertical line of a first boundary line adjacent to the target voltage vector in a sampling area, and the intersection point of the first vertical line and the first boundary line is used as the terminal point of the sampling voltage vector;

when the sub-sector is positioned in a second-class sampling blind area, taking an end point which is closest to the end point of the target voltage vector in a sampling area as the end point of the sampling voltage vector in a space vector plane;

when the sub-sector is located in a non-equivalent sampling blind area, in a space vector plane, the end point of the target voltage vector is used as a second perpendicular line of a second boundary line adjacent to the target voltage vector in the two types of sampling blind areas, the intersection point of the second perpendicular line and the second boundary line is used as the end point of the corrected target voltage vector, and the end point, closest to the end point of the corrected target voltage vector, in the sampling area is used as the end point of the sampling voltage vector.

4. The voltage vector adjustment method of claim 3, wherein when the sub-sector is located in a first-type sampling dead zone or a second-type sampling dead zone, the compensation voltage vector is calculated by:

Vc＝2*Vr-Vs

Vc＝2*Vr1-Vs

wherein Vc represents the compensation voltage vector, Vr represents the target voltage vector, Vr1 represents the modified target voltage vector, and Vs represents the sampled voltage vector.

5. The voltage vector adjustment method of claim 3, wherein when the sub-sector is located in a first sub-region in a class of sampling dead zones, the new comparison value in the first half carrier period is calculated by:

DDA＝DDA1-DDS，DDB＝DDB1-DDS，DDC＝DDC1-DDS

DDA1＝DDB0+Dmin，DDB1＝DDB0，DDC1＝DDC0+0.5*(Dmin-DDA1)

DDS＝0.5*DT-0.5(DDMAX-DDMIN)

when the sub-sector is located in a second sub-region in a class of sampling dead zones, the calculation formula of the new comparison value in the first half carrier period is as follows:

DDA＝DDA1-DDS，DDB＝DDB1-DDS，DDC＝DDC1-DDS

DDA1＝DDB0-0.5*(Dmin-DDC0)，DDB1＝DDB0，DDC1＝DDB0-Dmin

DDS＝0.5*DT-0.5(DDMAX-DDMIN)

wherein DDA, DDB, and DDC represent three-phase new comparison values in the first half carrier period, DDA0, DDB0, and DDC0 represent three-phase original comparison values in the first half carrier period, DDA1, DDB1, and DDC1 represent three-phase comparison values to be adjusted in the first half carrier period, DDS represents an offset of the three-phase comparison values to be adjusted in the first half carrier period, Dmin represents a size of the minimum sampling time Tmin reflected on the carrier, DT represents a maximum value of the carrier, and DDMAX and DDMIN represent maximum and minimum values in DDA1, DDB1, and DDC1, respectively;

when the sub-sector is located in a class of sampling blind area, the calculation formula of the new comparison value in the second half carrier period is as follows:

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS

DUA1＝DUA0-(DDA1-DDA0)，DUB1＝DUB0-(DDB1-DDB0)，DUC1＝DUC0-(DDC1-DDC0)DUS＝0.5*DT-0.5(DUMAX-DUMIN)

wherein, DUA, DUB and DUC represent three-phase new comparison values in the second half-carrier period, DUA0, DUB0 and DUC0 represent three-phase original comparison values in the second half-carrier period, DUA1, DUB1 and DUC1 represent three-phase comparison values to be adjusted in the second half-carrier period, DUS represents three-phase comparison value offset to be adjusted in the second half-carrier period, and DUMAX and DUMIN represent maximum values and minimum values in DUA1, DUB1 and DUC1, respectively.

6. The voltage vector adjustment method of claim 3, wherein when the sub-sector is located in a first sub-region of a class II sampling dead zone, the new comparison value in the first half carrier period is calculated by:

DDA＝DDB0+Dmin，DDB＝DDB0，DDC＝DDB0-Dmin

when the sub-sector is located in a second sub-region of the second-type sampling dead zone, a calculation formula of a new comparison value in the first half carrier period is as follows:

DDA＝DT，DDB＝DT-Dmin，DDC＝0

when the sub-sector is located in a third sub-region of the second-type sampling dead zone, a calculation formula of a new comparison value in the first half carrier period is as follows:

DDA＝DT，DDB＝Dmin，DDC＝0

wherein DDA, DDB, and DDC represent three-phase new comparison values in the first half carrier period, DDA0, DDB0, and DDC0 represent three-phase original comparison values in the first half carrier period, Dmin represents a size in which the minimum sampling time is embodied on a carrier, and DT represents a carrier maximum value;

when the sub-sector is located in the second-class sampling blind area, the calculation formula of the new comparison value in the second half-carrier period is as follows:

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS

7. The voltage vector adjustment method of claim 3, wherein when the sub-sector is located in a first sub-region in a non-equivalent sampling dead zone, the new comparison value in the first half carrier period is calculated by:

DDA＝DT，DDB＝DT-Dmin，DDC＝0

when the sub-sector is located in a second sub-region in the nonequivalent sampling blind region, the calculation formula of the new comparison value in the first half carrier period is as follows:

DDA＝DT，DDB＝Dmin，DDC＝0

DDA, DDB and DDC represent three-phase new comparison values in the first half carrier wave period, Dmin represents the size of the minimum sampling time reflected on the carrier wave, and DT represents the maximum value of the carrier wave;

when the sub-sector is located in the nonequivalent sampling blind area, the calculation formula of the new comparison value in the second half-carrier period is as follows:

DUA＝DUA1+DUS，DUB＝DUB1+DUS，DUC＝DUC1+DUS

wherein, the DUA, the DUB, and the DUC represent three-phase new comparison values in the second half-carrier period, the DDA0, the DDB0, and the DDC0 represent three-phase original comparison values in the first half-carrier period obtained according to the corrected target voltage vector, the DUA0, the DUB0, and the DUC0 represent three-phase original comparison values in the second half-carrier period obtained according to the corrected target voltage vector, the DUA1, the DUB1, and the DUC1 represent three-phase comparison values to be adjusted in the second half-carrier period, the DUS represents three-phase comparison value offsets to be adjusted in the second half-carrier period, and the DUMAX and the DUMIN represent maximum and minimum values in the DUA1, the DUB1, and the DUC1, respectively.

8. The voltage vector adjustment method of any one of claims 1 to 7, wherein determining the sub-sector in which the target voltage vector is located based on the original comparison values comprises:

determining the duration of two effective vectors forming the target voltage vector in a half-carrier period according to the original comparison value;

and determining the sub-sector where the target voltage vector is located according to the duration of the two effective vectors.

9. The voltage vector adjustment method of claim 8, wherein the two valid vectors include a first valid vector and a second valid vector;

determining the sub-sector where the target voltage vector is located according to the duration of the two effective vectors, including:

when the durations of the two effective vectors are both greater than the minimum sampling time, determining that the target voltage vector is in a sampleable region;

when the duration of the first effective vector is less than the minimum sampling time and the two effective vectors meet a first relation, determining that the target voltage vector is in a first sub-region in a class of sampling blind regions, wherein the first relation is as follows: 3 × Tmin is less than or equal to T1+2 × T2 is less than or equal to 2 × Tsh-Tmin;

when the duration of the second effective vector is less than the minimum sampling time and the two effective vectors meet a second relationship, determining that the target voltage vector is in a second sub-region of a class of sampling blind regions, wherein the second relationship is as follows: 3 × Tmin is less than or equal to T2+2 × T1 is less than or equal to 2 × Tsh-Tmin;

when the two effective vectors meet a third relationship, determining that the target voltage vector is in a first sub-area of the two types of sampling dead zones, wherein the third relationship is as follows: t1+ 2T 2 is not more than 3 Tmin;

when the duration of the first effective vector is less than the minimum sampling time, the duration of the second effective vector is less than the minimum sampling time obtained by subtracting 0.5 times from the half-carrier period, and the two effective vectors satisfy a fourth relationship, determining that the target voltage vector is in a second sub-region of the second type of sampling dead zone, where the fourth relationship is: t1+ 2T 2 is more than or equal to 2 Tsh-Tmin;

when the duration of the second effective vector is less than the minimum sampling time, the duration of the first effective vector is less than the minimum sampling time obtained by subtracting 0.5 times from a half-carrier period, and the two effective vectors satisfy a fifth relationship, determining that the target voltage vector is in a third sub-region of the second type of sampling dead zone, where the fifth relationship is: t2+ 2T 1 is more than or equal to 2 Tsh-Tmin;

determining a first sub-region of the target voltage vector in a nonequivalent sampling dead zone when the duration of the first effective vector is less than 0.5 times the minimum sampling time and the duration of the second effective vector is greater than the half-carrier period minus 0.5 times the minimum sampling time;

determining a second sub-region of the target voltage vector in a nonequivalent sampling dead zone when the duration of the second effective vector is less than 0.5 times the minimum sampling time and the duration of the first effective vector is greater than the half-carrier period minus 0.5 times the minimum sampling time;

wherein T1 represents the duration of the first significant vector, T2 represents the duration of the second significant vector, Tmin represents the minimum sampling time, and Tsh represents the half-carrier period.

10. A voltage vector adjustment apparatus, comprising:

11. A motor controller comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the voltage vector adjustment method according to any one of claims 1 to 9 when executing the computer program.

12. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the voltage vector adjustment method according to any one of claims 1 to 9.