CN113707536A - Back sealing process of wafer - Google Patents

Back sealing process of wafer Download PDF

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Publication number
CN113707536A
CN113707536A CN202110996641.7A CN202110996641A CN113707536A CN 113707536 A CN113707536 A CN 113707536A CN 202110996641 A CN202110996641 A CN 202110996641A CN 113707536 A CN113707536 A CN 113707536A
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Prior art keywords
wafer
gas
source gas
sealing process
silicon dioxide
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CN202110996641.7A
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Chinese (zh)
Inventor
安云富
丁振宇
侯龙
赵超
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Shanghai Dingtai Craftsman Core Technology Co ltd
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Shanghai Dingtai Craftsman Core Technology Co ltd
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Priority to CN202110996641.7A priority Critical patent/CN113707536A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)

Abstract

The invention provides a back sealing process of a wafer, which comprises the following steps: s1) placing the wafer in the reaction chamber for heating; s2) introducing silicon source gas and oxygen source gas to the back side of the wafer in the reaction chamber, and introducing protective gas to the front side of the wafer; the flow of the protective gas is larger than the flow of the silicon source gas and the oxygen source gas; s3) after the gas is introduced stably, loading radio frequency power on the back of the wafer to enable the gas to react and deposit silicon dioxide on the back of the wafer. Compared with the prior art, the method has the advantages that the silicon dioxide is directly grown on the back surface of the wafer, the protective gas is introduced into the front surface of the wafer while the silicon dioxide is grown so as to prevent the deposition of the silicon dioxide on the front surface, and the coverage range of the silicon dioxide on the edge of the back surface of the wafer can be adjusted by adjusting the flow of the protective gas, so that the back sealing process does not need a front surface process and does not have any contact or damage on the front surface.

Description

Back sealing process of wafer
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a wafer back sealing process.
Background
The processing of the monocrystalline silicon wafer polishing piece mainly comprises slicing, chamfering, lapping, corroding, back processing, polishing and cleaning processes, wherein the back processing process generally comprises back damage processing, back sealing processing and edge oxide film removing processing. The back sealing treatment is an important process for processing monocrystalline silicon wafers, and the quality of the back sealing surface plays a crucial role in the subsequent epitaxial process because: generally, epitaxially deposited wafers are heavily doped, and the dopant of the heavily doped wafer diffuses out of the heavily doped wafer and mixes with the flowing reactants at the temperature of the epitaxial growth process (around 1100 ℃), a phenomenon generally referred to as the "autodoping effect". When the epitaxial layer grows on the front surface of the silicon wafer, the effect is weakened, but the external diffusion of the back surface of the silicon wafer is continued; if a thin film is deposited on the back side of the wafer during this high temperature process, the out-diffusion of the dopant is effectively prevented and this layer prevents the escape of the dopant as an encapsulant. In the production of monocrystalline silicon crystal, the back sealing process is often a bottleneck process in the whole production line, so the improvement of the productivity is often the key to reduce the manufacturing cost.
The wafer usually adopts silicon dioxide grown on the back surface of the wafer to realize the function of back sealing, but the existing back sealing technology or method needs a front surface process, and the process is complex and high in cost.
Disclosure of Invention
The present invention is directed to a wafer backside sealing process, which does not require a front side process and does not have any front side contact or damage.
The invention provides a back sealing process of a wafer, which comprises the following steps:
s1) placing the wafer in the reaction chamber for heating;
s2) introducing silicon source gas and oxygen source gas to the back side of the wafer in the reaction chamber, and introducing protective gas to the front side of the wafer; the flow of the protective gas is larger than the flow of the silicon source gas and the oxygen source gas;
s3) after the gas is introduced stably, loading radio frequency power on the back of the wafer to enable the gas to react and deposit silicon dioxide on the back of the wafer.
Preferably, the wafer is fixed on the bearing ring and then placed in the reaction chamber.
Preferably, the heating temperature in the step S1) is 300 to 580 ℃.
Preferably, the silicon source gas in the step S2) is silane or tetraethoxysilane; the oxygen source gas is laughing gas or oxygen; the protective gas is nitrogen.
Preferably, the flow rate of the silicon source gas in the step S2) is 80 to 200 sccm; the flow rate of the oxygen source gas is 8000-16000 sccm; the flow rate of the protective gas is 16000-25000 sccm.
Preferably, the time for stabilizing the gas in the step S3) is 10 to 60 seconds.
Preferably, the loading radio frequency power is 3000-5000W.
Preferably, the pressure of the gas reaction in the step S3) is 1.2 to 2.0 Torr.
Preferably, the silica is deposited followed by purging with a protective gas.
The invention provides a back sealing process of a wafer, which comprises the following steps: s1) placing the wafer in the reaction chamber for heating; s2) introducing silicon source gas and oxygen source gas to the back side of the wafer in the reaction chamber, and introducing protective gas to the front side of the wafer; the flow of the protective gas is larger than the flow of the silicon source gas and the oxygen source gas; s3) after the gas is introduced stably, loading radio frequency power on the back of the wafer to enable the gas to react and deposit silicon dioxide on the back of the wafer. Compared with the prior art, the method has the advantages that the silicon dioxide is directly grown on the back surface of the wafer, the protective gas is introduced into the front surface of the wafer while the silicon dioxide is grown so as to prevent the deposition of the silicon dioxide on the front surface, and the coverage range of the silicon dioxide on the edge of the back surface of the wafer can be adjusted by adjusting the flow of the protective gas, so that the back sealing process does not need a front surface process and does not have any contact or damage on the front surface.
Drawings
FIG. 1 is a schematic view of a wafer backside sealing process provided by the present invention;
FIG. 2 is a graph showing the effect of the resistivity of the epitaxial layer after different back seal thicknesses in examples 1 to 3 of the present invention;
fig. 3 is a graph illustrating the effect of the thickness of the back growth edge of different edge rings according to embodiments 3 to 4 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a back sealing process of a wafer, which comprises the following steps: s1) placing the wafer in the reaction chamber for heating; s2) introducing silicon source gas and oxygen source gas to the back side of the wafer in the reaction chamber, and introducing protective gas to the front side of the wafer; the flow of the protective gas is larger than the flow of the silicon source gas and the oxygen source gas; s3) after the gas is introduced stably, loading radio frequency power on the back of the wafer to enable the gas to react and deposit silicon dioxide on the back of the wafer.
Referring to fig. 1, fig. 1 is a schematic view of a wafer back sealing process provided in the present invention.
In this case, the source of all the raw materials is not particularly limited.
Heating the wafer in a reaction chamber; the wafer is a wafer well known to those skilled in the art, and is not particularly limited, and in the present invention, a heavily doped low resistance wafer is preferred; the resistivity of the wafer is preferably less than 1.5mohm cm; the wafer is preferably fixed on the bearing ring and then placed in the reaction chamber; in the invention, the silicon dioxide coverage range of the edge of the back of the wafer can be adjusted by the width of the bearing ring; the material of the bearing ring is preferably ceramic; in the present invention, the wafer is preferably mechanically transferred into the reaction chamber; the heating temperature is preferably 300 to 580 ℃, more preferably 300 to 550 ℃, even more preferably 300 to 500 ℃, even more preferably 300 to 450 ℃, even more preferably 300 to 400 ℃, and most preferably 350 ℃. The invention adopts the low-temperature process to grow the silicon dioxide, and has lower thermal budget compared with the prior high-temperature back sealing process.
Then introducing silicon source gas and oxygen source gas into the back surface of the wafer in the reaction chamber, and simultaneously introducing protective gas into the front surface of the wafer; in the present invention, the pressure in the reaction chamber is preferably controlled to be 1.2 to 2.0Torr, more preferably 1.2 to 1.8Torr, still more preferably 1.4 to 1.6 Torr; the silicon source gas is preferably silane or Tetraethylorthosilicate (TEOS); the flow rate of the silicon source gas is preferably 80-200 sccm, more preferably 100-180 sccm, further preferably 100-160 sccm, and most preferably 120-140 sccm; the oxygen source gas is preferably laughing gas or oxygen; the flow rate of the oxygen source gas is preferably 8000-16000 sccm, more preferably 10000-15000 sccm, further preferably 11000-14000 sccm, and most preferably 13000 sccm; the protective gas is preferably nitrogen; the flow rate of the protective gas is preferably 16000-25000 sccm, more preferably 18000-23000 sccm, still more preferably 19000-21000 sccm, and most preferably 20000 sccm.
After the gas is introduced stably, preferably stabilizing for 10-60 s, more preferably stabilizing for 20-40 s, and further preferably stabilizing for 30s, loading radio frequency power on the back of the wafer to enable the gas to react and deposit silicon dioxide on the back of the wafer; in the invention, the radio frequency power is preferably loaded below the back surface of the wafer; the loaded radio frequency power is preferably 3000-5000W, more preferably 4000-5000W, and further preferably 4500W; the pressure of the gas reaction is preferably 1.2 to 2.0Torr, more preferably 1.2 to 1.8Torr, and still more preferably 1.4 to 1.6 Torr; the reaction time is adjusted according to the thickness of the deposit.
After deposition of the silica, purging is preferably performed with a protective gas; the protective gas is preferably nitrogen; the time for purging is preferably 10-60 s, more preferably 10-40 s, and further preferably 20-30 s.
After purging, the wafer after back sealing is preferably transferred to a cooling cavity by a mechanical transfer arm for cooling, thereby completing the back sealing process.
According to the invention, silicon dioxide is directly grown on the back surface of the wafer, protective gas is introduced to the front surface of the wafer while the silicon dioxide is grown to prevent the deposition of the silicon dioxide on the front surface, and the coverage range of the silicon dioxide on the edge of the back surface of the wafer can be adjusted by adjusting the flow of the protective gas, so that the back sealing process does not need a front surface process and does not have any contact or damage on the front surface.
In order to further illustrate the present invention, the following describes a wafer backside sealing process in detail with reference to the following embodiments.
The reagents used in the following examples are all commercially available.
Example 1
A heavily doped low-resistance (resistivity is less than 1.5mohm & cm) wafer substrate is adopted, a No. 2 bearing ring (made of ceramic, the inner diameter of the No. 2 bearing ring is 299 mm, and the diameter of the wafer is 300 mm) is used, 2000A silicon dioxide is grown as a back seal by a single-sided process back seal at the temperature of 350 ℃, and a substrate without the back seal is used as a contrast. Then, a phosphorus-doped silicon epitaxial layer having a thickness of 5 μm and a resistivity of 0.48ohm cm was grown and the resistivity of the epitaxial layer was tested to react and seal the barrier effect against external diffusion, and the results are shown in fig. 2 and table 1. The average value and the uniformity of the resistivity are obviously improved through testing, so that the wafer back surface barrier film has a good barrier effect on the external diffusion.
The method comprises the following specific implementation steps:
A. and conveying the clean monocrystalline silicon wafer to be processed into the reaction chamber through a machine, and keeping the surface processing temperature of the monocrystalline silicon wafer at 350 ℃.
B. Controlling the pressure of the reaction chamber to be 1.4T and introducing 120sccm of Silane (SiH) to the back surface of the wafer in the reaction chamber4) And laughing gas of 13000sccm (N)2O); simultaneously, nitrogen (N) with the flow rate of 20000sccm is introduced to the front surface of the wafer in the reaction chamber2) As a front shielding gas.
C. After gas stabilization for 30s RFpower of 4500W was loaded under the wafer backside to react the gas to deposit silicon dioxide on the wafer backside.
D. After the deposition of the silicon dioxide film is completed, nitrogen (N) is used2) Purge for 20 seconds.
E. The wafer is transferred to the cooling cavity by the mechanical transfer arm to be cooled and then is returned.
Example 2
Heavily doped low-resistance (resistivity <1.5mohm cm) wafer substrate is adopted, a No. 2 edge ring is used, silicon dioxide of 3500A is grown in a single-sided process back seal at the temperature of 350 ℃ to serve as a back seal, and a substrate without the back seal is used as a contrast. Then, a phosphorus-doped silicon epitaxial layer having a thickness of 5 μm and a resistivity of 0.48ohm cm was grown and the resistivity of the epitaxial layer was tested to block the external diffusion by reaction back-sealing, and the results are shown in fig. 2 and table 1. The average value and the uniformity of the resistivity are obviously improved through testing, so that the wafer back surface barrier film has a good barrier effect on the external diffusion.
The method comprises the following specific implementation steps:
A. and conveying the clean monocrystalline silicon wafer to be processed into the reaction chamber through a machine, and keeping the surface processing temperature of the monocrystalline silicon wafer at 350 ℃.
B. Controlling the pressure of the reaction chamber to be 1.4T and introducing 120sccm of Silane (SiH) to the back surface of the wafer in the reaction chamber4) And laughing gas of 13000sccm (N)2O); simultaneously, nitrogen (N) with the flow rate of 20000sccm is introduced to the front surface of the wafer in the reaction chamber2) As a front shielding gas.
C. After gas stabilization for 30s RFpower of 4500W was loaded under the wafer backside to react the gas to deposit silicon dioxide on the wafer backside.
D. After the deposition of the silicon dioxide film is completed, nitrogen (N) is used2) Purge for 20 seconds.
E. The wafer is transferred to the cooling cavity by the mechanical transfer arm to be cooled and then is returned.
Example 3
A heavily doped low-resistance (resistivity <1.5mohm & cm) wafer substrate is adopted, a No. 2 edge ring is used, silicon dioxide with 5000A growth in a single-sided process back seal at the temperature of 350 ℃ is used as a back seal, and a substrate without the back seal is used as a contrast. Then, a phosphorus-doped silicon epitaxial layer having a thickness of 5 μm and a resistivity of 0.48ohm cm was grown and the resistivity of the epitaxial layer was tested to block the external diffusion by reaction back-sealing, and the results are shown in fig. 2 and table 1. The average resistivity and the uniformity are obviously improved after testing, thereby reflecting that the invention has good barrier effect on the back side of the wafer against the out diffusion.
The method comprises the following specific implementation steps:
A. and conveying the clean monocrystalline silicon wafer to be processed into the reaction chamber through a machine, and keeping the surface processing temperature of the monocrystalline silicon wafer at 350 ℃.
B. Controlling the pressure of the reaction chamber to be 1.4T and introducing 120sccm of Silane (SiH) to the back surface of the wafer in the reaction chamber4) And laughing gas of 13000sccm (N)2O); simultaneously, nitrogen (N) with the flow rate of 20000sccm is introduced to the front surface of the wafer in the reaction chamber2) As a front shielding gas.
C. After gas stabilization for 30s RFpower of 4500W was loaded under the wafer backside to react the gas to deposit silicon dioxide on the wafer backside.
D. After the deposition of the silicon dioxide film is completed, nitrogen (N) is used2) Purge for 20 seconds.
E. The wafer is transferred to the cooling cavity by the mechanical transfer arm to be cooled and then is returned.
Example 4
The back sealing process flow is the same as that of the embodiment 3, except that the number 2 bearing ring is replaced by the number 1 bearing ring (the material is ceramic, and the inner diameter of the number 1 bearing ring is 298 mm).
Example 5
The back sealing process flow is the same as that of embodiment 3, except that the number 2 bearing ring is replaced by a number 3 bearing ring (the material is ceramic, and the inner diameter of the number 3 bearing ring is 306 mm).
FIG. 3 is a graph showing the effect of edge thickness on the backside of different carrier rings.
Table 1 results of resistivity test of epitaxial layers of examples 1 to 3
Thickness of silicon dioxide on back surface of wafer 200 nm 350 nm 500 nm 0 nm
Average resistivity value (ohm. cm) 0.477 0.472 0.476 0.434
Maximum value of resistivity (ohm. cm) 0.488 0.4822 0.4849 0.457
Minimum value of resistivity (ohm. cm) 0.464 0.458 0.462 0.305
Uniformity of resistivity 1.41％ 1.15％ 1.17％ 8.64％

Claims (9)

1. A wafer back sealing process is characterized by comprising the following steps:
s1) placing the wafer in the reaction chamber for heating;
s2) introducing silicon source gas and oxygen source gas to the back side of the wafer in the reaction chamber, and introducing protective gas to the front side of the wafer; the flow of the protective gas is larger than the flow of the silicon source gas and the oxygen source gas;
s3) after the gas is introduced stably, loading radio frequency power on the back of the wafer to enable the gas to react and deposit silicon dioxide on the back of the wafer.
2. The backside seal process of claim 1 wherein the wafer is mounted on a carrier ring and then placed in a reaction chamber.
3. The back sealing process of claim 1, wherein the heating temperature in step S1) is 300 ℃ to 580 ℃.
4. The back sealing process of claim 1, wherein in the step S2), the silicon source gas is silane or tetraethoxysilane; the oxygen source gas is laughing gas or oxygen; the protective gas is nitrogen.
5. The backside sealing process of claim 1, wherein the flow rate of the silicon source gas in the step S2) is 80-200 sccm; the flow rate of the oxygen source gas is 8000-16000 sccm; the flow rate of the protective gas is 16000-25000 sccm.
6. The back sealing process of claim 1, wherein the time for the gas to stabilize in step S3) is 10-60S.
7. The backside sealing process of claim 1, wherein the applied RF power is 3000-5000W.
8. The backside sealing process of claim 1, wherein the pressure of the gas reaction in step S3) is 1.2-2.0 Torr.
9. The backclosuring process of claim 1, wherein the silicon dioxide is deposited and then purged with a protective gas.
CN202110996641.7A 2021-08-27 2021-08-27 Back sealing process of wafer Pending CN113707536A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117004928A (en) * 2023-09-21 2023-11-07 上海谙邦半导体设备有限公司 Chemical vapor deposition wafer protection system

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910005410A (en) * 1989-08-25 1991-03-30 제임스 조셉 드롱 Method and apparatus for removing deposition from backside and end border of semiconductor wafers while preventing removal of materials from front surface of wafer
KR100676521B1 (en) * 2005-12-19 2007-02-01 주식회사 실트론 Producing method of low temperature oxide, and wafer made thereby
CN103021842A (en) * 2012-12-03 2013-04-03 天津中环领先材料技术有限公司 Back seal process for achieving high-speed SiO2 film sedimentation on monocrystalline silicon wafer
CN205069606U (en) * 2015-10-27 2016-03-02 上海集成电路研发中心有限公司 Silicon chip bears base and atomic layer deposition equipment
CN106158770A (en) * 2015-04-17 2016-11-23 上海申和热磁电子有限公司 For silicon chip without trimming super back of the body seal coat structure and manufacture method thereof
CN110945159A (en) * 2017-07-28 2020-03-31 东京毅力科创株式会社 System and method for backside deposition of substrates

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910005410A (en) * 1989-08-25 1991-03-30 제임스 조셉 드롱 Method and apparatus for removing deposition from backside and end border of semiconductor wafers while preventing removal of materials from front surface of wafer
KR100676521B1 (en) * 2005-12-19 2007-02-01 주식회사 실트론 Producing method of low temperature oxide, and wafer made thereby
CN103021842A (en) * 2012-12-03 2013-04-03 天津中环领先材料技术有限公司 Back seal process for achieving high-speed SiO2 film sedimentation on monocrystalline silicon wafer
CN106158770A (en) * 2015-04-17 2016-11-23 上海申和热磁电子有限公司 For silicon chip without trimming super back of the body seal coat structure and manufacture method thereof
CN205069606U (en) * 2015-10-27 2016-03-02 上海集成电路研发中心有限公司 Silicon chip bears base and atomic layer deposition equipment
CN110945159A (en) * 2017-07-28 2020-03-31 东京毅力科创株式会社 System and method for backside deposition of substrates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117004928A (en) * 2023-09-21 2023-11-07 上海谙邦半导体设备有限公司 Chemical vapor deposition wafer protection system
CN117004928B (en) * 2023-09-21 2023-12-26 上海谙邦半导体设备有限公司 Chemical vapor deposition wafer protection system

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