CN113703507A - Circuit for improving response speed of LDO (low dropout regulator) - Google Patents
Circuit for improving response speed of LDO (low dropout regulator) Download PDFInfo
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- CN113703507A CN113703507A CN202010444915.7A CN202010444915A CN113703507A CN 113703507 A CN113703507 A CN 113703507A CN 202010444915 A CN202010444915 A CN 202010444915A CN 113703507 A CN113703507 A CN 113703507A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
A circuit for improving the response speed of an LDO (low dropout regulator) is characterized in that an auxiliary loop which directly detects the change of an output voltage VOUT through a third resistor R0 is arranged on a main loop of the LDO, and the auxiliary loop comprises a second amplification module A2, a sixth NMOS transistor M0 and a first current source I0, so that the quick response can be realized while the stability of the output voltage of the LDO is improved, and the contradiction between the response speed and the stability of the LDO can be better accommodated.
Description
Technical Field
The invention relates to a technology of a linear voltage regulator for improving the LDO low dropout, in particular to a circuit for improving the response speed of the LDO, wherein an auxiliary loop for directly detecting the change of an output voltage VOUT through a third resistor R0 is arranged on a main loop of the LDO, and the auxiliary loop comprises a second amplification module A2, a sixth NMOS tube M0 and a first current source I0, so that the stability of the output voltage of the LDO can be improved, and meanwhile, the quick response can be realized, and the contradiction between the response speed and the stability of the LDO can be better regulated.
Background
LDO (low dropout regulator) is widely used in many fields, but there is often a compromise problem between response speed and stability, that is, increasing response speed reduces stability, and increasing stability reduces response speed. For example, as shown in fig. 1, fig. 1 is a schematic diagram of a circuit structure in which the response speed of the LDO is to be improved. The LDO main loop is composed of an LDO main loop, the LDO main loop is composed of a first amplification module A1, a second amplification module A2, a power NMOS tube M1, a first resistor R1 and a second resistor R2, a drain terminal of M1 is connected with an input voltage terminal IN, a gate terminal of M1 is respectively connected with an output terminal and a negative input terminal of A2, a source terminal of M1 is connected with an output voltage terminal OUT, OUT is connected with a feedback node FB through R1, FB is connected with a ground terminal GND through R2, a positive input terminal of A2 is connected with an output terminal of A1, a positive input terminal of A1 is connected with a reference voltage terminal REF, and a negative input terminal of A1 is connected with FB. As shown in fig. 1, the unity gain buffer formed by a2 blocks the direct connection between the output resistor a1 and the gate capacitor of the power output MOS transistor M1, otherwise the pole formed by the output resistor a1 and the gate capacitor of the power output MOS transistor M1 affects the system stability and reduces the small signal bandwidth. Although the circuit arrangement of fig. 1 can solve the stability problem well, it has the disadvantage of slow response speed in some applications, for example, it cannot respond to output changes quickly when there is a large signal. The inventor believes that if an auxiliary loop for directly detecting the change of the output voltage VOUT through the third resistor R0 is disposed on the main loop of the LDO, and the auxiliary loop includes the second amplifying module a2, the sixth NMOS transistor M0 and the first current source I0, the fast response can be achieved while the stability of the output voltage of the LDO is improved. In view of the above, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a circuit for improving the response speed of an LDO (low dropout regulator), wherein an auxiliary loop for directly detecting the change of an output voltage VOUT (volatile organic compounds) through a third resistor R0 is arranged on a main loop of the LDO, and the auxiliary loop comprises a second amplification module A2, a sixth NMOS (N-channel metal oxide semiconductor) tube M0 and a first current source I0, so that the stability of the output voltage of the LDO can be improved, and meanwhile, the quick response can be realized, and the contradiction between the response speed and the stability of the LDO can be better regulated.
The technical scheme of the invention is as follows:
a circuit for improving the response speed of an LDO (low dropout regulator), which is characterized in that an auxiliary loop for directly detecting the change of an output voltage through a third resistor is arranged on a main loop of the LDO, and the auxiliary loop comprises a second amplification module, a sixth NMOS (N-channel metal oxide semiconductor) tube and a first current source.
The drain terminal of the sixth NMOS tube is connected with the input voltage terminal, the gate terminal of the sixth NMOS tube is respectively connected with the output terminal of the second amplification module and the gate terminal of the power NMOS tube, the first path of the source terminal of the sixth NMOS tube is connected with the output voltage terminal through the third resistor, the second path is connected with the grounding terminal through the first current source, and the third path is connected with the negative input terminal of the second amplification module.
The LDO main loop comprises a first amplification module, a second amplification module, a power NMOS tube, a first resistor and a second resistor, wherein a drain end of the power NMOS tube is connected with an input voltage end, a source end of the power NMOS tube is connected with an output voltage end, the output voltage end passes through the first resistor and is connected with a feedback node, the feedback node passes through the second resistor and is connected with a grounding end, a positive input end of the second amplification module is connected with an output end of the first amplification module, a positive input end of the first amplification module is connected with a reference voltage end, and a negative input end of the first amplification module is connected with the feedback node.
The second amplification module comprises a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a second current source.
The gate terminal of the second NMOS transistor is connected to the ground terminal through the first current source, the drain terminal of the second NMOS transistor is connected to the drain terminal of the fourth PMOS transistor and then to the gate terminal of the power NMOS transistor and the charge pump, the source terminal of the second NMOS transistor is connected to the source terminal of the third NMOS transistor and then to the ground terminal through the second current source, the gate terminal of the third NMOS transistor is connected to the output terminal of the first amplification module, the drain terminal of the third NMOS transistor is connected to the drain terminal of the fifth PMOS transistor and then to the gate terminal of the fourth PMOS transistor and the gate terminal of the fifth PMOS transistor, and the source terminal of the fourth PMOS transistor is connected to the source terminal of the fifth PMOS transistor and then to the input voltage terminal.
The auxiliary loop circuit plays a role in blocking the electric connection between the first amplification module and the power NMOS tube in a steady state, namely, the output resistor of the first amplification module cannot form a low-resistance pole with the gate capacitor of the power NMOS tube, so that the circuit stability is improved, and the bandwidth is enlarged.
The variable quantity of the output voltage is transmitted to the negative input end of the second amplification module through the third resistor, so that the auxiliary loop responds earlier than the LDO main loop so as to inhibit the change of the output voltage by influencing the grid-source voltage of the power NMOS tube in time.
The invention has the following technical effects: according to the circuit for improving the response speed of the LDO, the auxiliary loop for directly detecting the change of the output voltage through the third resistor is arranged on the main loop of the LDO, so that the response speed and the stability can be improved by utilizing the auxiliary loop. For example, the first amplifying module and the power NMOS transistor are electrically disconnected in a steady state, that is, the output resistor of the first amplifying module and the gate capacitor of the power NMOS transistor cannot form a low-resistance pole, so that the circuit stability is improved and the bandwidth is enlarged; when the output voltage VOUT changes suddenly, the change quantity of the output voltage is transmitted to the negative input end of the second amplification module through the third resistor, so that the auxiliary loop responds earlier than the LDO main loop so as to inhibit the change of the output voltage by influencing the grid-source voltage of the power NMOS tube in time.
Drawings
Fig. 1 is a schematic diagram of a circuit structure in which the response speed of the LDO is to be improved. The LDO (low dropout regulator) in fig. 1 cannot respond quickly to output changes when the signal is large.
FIG. 2 is a schematic diagram of a circuit for increasing the response speed of LDO according to the present invention.
Fig. 3 is a schematic structural diagram of a circuit for increasing the response speed of the LDO, which is shown in fig. 2 by a second amplification module a 2.
The reference numbers are listed below: OUT-output voltage terminal (corresponding to output voltage VOUT); IN-input voltage terminal (corresponding to input voltage VIN); REF-reference voltage terminal; GND-ground; a1 — first amplification module; a2 — first amplification module; R1-R2-first to second resistors; r0 — third resistance; a FB-feedback node; i0 — a first current source; i1 — a second current source; m1-first NMOS transistor or power NMOS transistor M2-M3-second to third NMOS transistors; M4-M5-fourth to fifth PMOS tubes; m0-sixth NMOS transistor.
Detailed Description
The invention is described below with reference to the accompanying drawings (fig. 2-3).
FIG. 2 is a schematic diagram of a circuit for increasing the response speed of LDO according to the present invention. Fig. 3 is a schematic structural diagram of a circuit for increasing the response speed of the LDO, which is shown in fig. 2 by a second amplification module a 2. As shown in fig. 2 to 3, an auxiliary loop for directly detecting a change in output voltage VOUT through a third resistor R0 is disposed on a main loop of the LDO, and includes a second amplification module a2, a sixth NMOS transistor M0, and a first current source I0. The drain terminal of the sixth NMOS transistor M0 is connected to the input voltage terminal IN, the gate terminal of the sixth NMOS transistor M0 is connected to the output terminal of the second amplification module a2 and the gate terminal of the power NMOS transistor M1, respectively, the first path of the source terminal of the sixth NMOS transistor M0 is connected to the output voltage terminal OUT through the third resistor R0, the second path is connected to the ground terminal GND through the first current source I0, and the third path is connected to the negative input terminal (-) of the second amplification module a 2. The LDO main loop comprises a first amplification module A1, a second amplification module A2, a power NMOS tube M1, a first resistor R1 and a second resistor R2, wherein a drain terminal of the power NMOS tube M1 is connected with an input voltage terminal IN, a source terminal of the power NMOS tube M1 is connected with an output voltage terminal OUT, the output voltage terminal OUT is connected with a feedback node FB through the first resistor R1, the feedback node FB is connected with a ground terminal GND through the second resistor R2, a positive input terminal (+) of the second amplification module A2 is connected with an output terminal of the first amplification module A1, a positive input terminal (+) of the first amplification module A1 is connected with a reference voltage terminal REF, and a negative input terminal (-) of the first amplification module A1 is connected with the feedback node FB.
Referring to fig. 3, the second amplifying module a2 includes a second NMOS transistor M2, a third NMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, and a second current source I1. The gate end of the second NMOS transistor M2 is connected to a ground end GND through the first current source I0, the drain end of the second NMOS transistor M2 is connected to the drain end of the fourth PMOS transistor M4 and then connected to the gate end of the power NMOS transistor M1 and the charge pump, the source end of the second NMOS transistor M2 is connected to the source end of the third NMOS transistor M3 and then connected to the ground end GND through the second current source I1, the gate end of the third NMOS transistor M3 is connected to the output end of the first amplification module a1, the drain end of the third NMOS transistor M3 is connected to the drain end of the fifth PMOS transistor M5 and then connected to the gate end of the fourth PMOS transistor M4 and the gate end of the fifth PMOS transistor M5, and the source end of the fourth PMOS transistor M4 is connected to the input voltage terminal IN after being connected to the drain end of the fifth PMOS transistor M5.
The auxiliary loop circuit plays a role in blocking the electric connection between the first amplification module A1 and the power NMOS transistor M1 in a steady state, namely, the output resistor of the first amplification module A1 and the gate capacitor of the power NMOS transistor M1 cannot form a low-resistance pole, so that the circuit stability is improved, and the bandwidth is enlarged. The variation of the output voltage VOUT is transferred to the negative input (-) of the second amplification module a2 through the third resistor R0, so that the auxiliary loop responds earlier than the LDO main loop to suppress the variation of the output voltage VOUT by affecting the gate-source voltage of the power NMOS transistor M1 in more time.
The specific working principle of the present invention is further explained below with reference to fig. 2.
M1 is power NMOS tube, its drain terminal is connected with IN, source terminal is connected with OUT, grid terminal is connected with A2 amplifier module output;
m0 is NMOS tube, its drain terminal is connected with IN, source terminal is connected with positive terminal of current source I0, grid terminal is connected with output end of A2 amplifying module;
one end of the R0 resistor is connected with the positive end of a current source I0 (simultaneously connected with the negative input end of the A2 amplifying module), and the other end is connected with OUT;
one end of the R1 resistor is connected with OUT, and the other end is connected with the negative input end of the A1 amplifying module (the node is named FB and is simultaneously connected with the R2 resistor in series, and the other end of the R2 resistor is grounded;
a1 is an amplifying module, the positive input of which is connected with a REF signal which represents a reference voltage;
a2 is an amplifying module, the positive input of which is connected with the output end of the A1 amplifying module;
the loop consisting of M1, R1, R2, A1 and A2 stabilizes the output voltage VOUT, which is the main loop of the LDO, and the loop consisting of A2, M0 and I0 only plays a role in blocking the electric connection between A1 and M1 in a steady state, namely the output resistance of A1 cannot form a low-resistance pole with the gate capacitance of M1, so that the stability is improved and the bandwidth is enlarged;
8. when VOUT changes suddenly, the change quantity of VOUT can be quickly transmitted to the negative input end of A2 through R0, and then the loops of A2, M0 and I0 respond earlier than the main loop (M1, R1, R2, A1 and A2), so that the grid-source voltage of M1 can be influenced in time, and the change of VOUT is restrained;
as shown in fig. 3, M2 and M3 are NMOS transistors, M4 and M5 are PMOS transistors, and they constitute the a2 amplifier module of fig. 2 together with the current source I1.
The features of the invention can be seen from the above description: 1. as described in working principle 7, a2, M0, and I0 block the electrical connection of a1 and M1, thereby improving stability; 2, the loop consisting of A2, M0 and I0 can directly detect VOUT change through R0, thereby realizing quick response in large signal.
In the present invention, the NMOS transistor or the PMOS transistor as illustrated in fig. 2 to 3 can be replaced by each other in principle or in practice, and the equivalent circuit after replacement is well known to those skilled in the art. Therefore, the NMOS transistor or the PMOS transistor in the present specification and the claims should be understood as the MOS transistor with the technical features as an extension unless otherwise specified.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.
Claims (7)
1. A circuit for improving the response speed of an LDO (low dropout regulator), which is characterized in that an auxiliary loop for directly detecting the change of an output voltage through a third resistor is arranged on a main loop of the LDO, and the auxiliary loop comprises a second amplification module, a sixth NMOS (N-channel metal oxide semiconductor) tube and a first current source.
2. The circuit of claim 1, wherein a drain terminal of the sixth NMOS transistor is connected to the input voltage terminal, a gate terminal of the sixth NMOS transistor is connected to the output terminal of the second amplification module and the gate terminal of the power NMOS transistor, respectively, a first path of a source terminal of the sixth NMOS transistor is connected to the output voltage terminal through the third resistor, a second path is connected to the ground terminal through the first current source, and a third path is connected to the negative input terminal of the second amplification module.
3. The circuit of claim 2, wherein the main loop of the LDO comprises a first amplification module, the second amplification module, the power NMOS transistor, a first resistor, and a second resistor, a drain terminal of the power NMOS transistor is connected to an input voltage terminal, a source terminal of the power NMOS transistor is connected to the output voltage terminal, the output voltage terminal is connected to a feedback node through the first resistor, the feedback node is connected to a ground terminal through the second resistor, a positive input terminal of the second amplification module is connected to an output terminal of the first amplification module, a positive input terminal of the first amplification module is connected to a reference voltage terminal, and a negative input terminal of the first amplification module is connected to the feedback node.
4. The circuit of claim 3, wherein the second amplification module comprises a second NMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a second current source.
5. The circuit of claim 4, wherein a gate of the second NMOS transistor is connected to a ground terminal through the first current source, a drain of the second NMOS transistor is connected to a drain of the fourth PMOS transistor and then to a gate of the power NMOS transistor and a charge pump, respectively, a source of the second NMOS transistor is connected to a source of the third NMOS transistor and then to the ground terminal through the second current source, a gate of the third NMOS transistor is connected to an output of the first amplification module, a drain of the third NMOS transistor is connected to a drain of the fifth PMOS transistor and then to a gate of the fourth PMOS transistor and a gate of the fifth PMOS transistor, respectively, and a source of the fourth PMOS transistor is connected to a source of the fifth PMOS transistor and then to the input voltage terminal.
6. The circuit of claim 3, wherein the auxiliary loop circuit is configured to block the electrical connection between the first amplifier module and the power NMOS transistor in a steady state, i.e. the output resistor of the first amplifier module cannot form a low resistance pole with the gate capacitor of the power NMOS transistor, thereby improving the circuit stability and increasing the bandwidth.
7. The circuit of claim 3, wherein a change in the output voltage is transferred to the negative input of the second amplification module through the third resistor, such that the auxiliary loop responds earlier than the LDO main loop to suppress the change in the output voltage by affecting the gate-source voltage of the power NMOS transistor in more time.
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| CN202010444915.7A CN113703507B (en) | 2020-05-23 | 2020-05-23 | Circuit for improving response speed of LDO (low dropout regulator) |
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| CN202010444915.7A CN113703507B (en) | 2020-05-23 | 2020-05-23 | Circuit for improving response speed of LDO (low dropout regulator) |
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